目前，全球范围内，只有少数领先企业具备2.5D的量产能力，其中台积电、英特尔、三星电子合计占据 80%以上的市场规模，2024年度，公司2.5D的全球市场占有率约为8%。 此外，公司亦在持续丰富完善3D集成（3DIC）、三维封装（3D Package）等技术平台，以期在集成电 路制造产业更加前沿的关键技术领域实现突破，为未来经营业绩创造新的增长点。 财务数据显示，2022年度、2023年度、2024年度及2025年1—6月，盛合晶微分别实现营业收入约16.33 亿元、30.38亿元、47.05亿元、31.78亿元；同期实现净利润分别约为-3.29亿元、3413.06万元、2.14亿 元、4.35亿元。 在主营业务领域中，公司已大规模向客户提供的各类服务均在中国大陆处于领先地位，具体而言：在中 段硅片加工领域，公司是中国大陆最早开展并实现12英寸Bumping量产的企业之一，也是第一家能够提 供14nm先进制程Bumping服务的企业，公司具备2.5D/3DIC超高密度微凸块的大规模量产能力，填补了 中国大陆高端集成电路制造产业链的空白。根据灼识咨询的统计，截至2024年末，公司是中国大陆12英 寸Bumpin ...

Summary of Key Points from the Conference Call Industry Overview - The conference focused on the semiconductor industry, particularly advancements in AI chips, heterogeneous integration, advanced packaging, and optical interconnect technologies, reflecting the growing importance of these areas in the market [2][3][20]. Core Findings 1. **TSMC's Capacity Expansion**: TSMC is expected to expand its CoWoS capacity to 100kwpm by the end of 2026, up from 70kwpm at the end of 2025, driven by robust demand for Cloud AI GPUs and ASICs [3]. 2. **AI Computing Demand**: AI computing requirements have surged by 10x in the past year, necessitating advancements in chip scaling, memory, and interconnect technologies [3]. 3. **3.5D Advanced Packaging**: The event highlighted significant discussions around 3.5D advanced packaging, which is anticipated to become mainstream for high-performance computing, improving cost structures and product design speeds [3]. 4. **Heterogeneous Integration**: The trend towards co-packaged optics (CPO) is gaining traction, with expectations for power consumption to be optimized by 2028, allowing for the replacement of copper in AI server integrations [3]. 5. **Testing Innovations**: The complexity of die and package designs is increasing the need for more rigorous testing at the wafer/die level to identify yield issues early [3]. Stock Recommendations - Top stock picks in the Greater China semiconductor sector include TSMC, ASE, MediaTek, Alchip, and Aspeed, all rated as "Buy" due to their structural AI opportunities [4]. Additional Insights - **Optical Interconnects**: Nvidia's advancements in networking infrastructure, particularly with its Spectrum-X CPO solution, promise significant power savings and improved signal integrity [12]. - **AI Data Center Power Consumption**: The power consumption of AI data centers is projected to rise dramatically, with examples like Meta's Hyperion data center expected to consume 2GW by 2030 [16]. - **Challenges in Advanced Packaging**: The industry faces challenges in transitioning to panel-level packaging and CoWoP technologies, which require overcoming technical hurdles related to system design and materials [30][39]. Emerging Technologies - **Silicon Photonics**: TSMC's COUPE platform aims to enhance integration of optics and electrical signaling, addressing bandwidth bottlenecks in computing performance [12]. - **GaN Technology**: GaN is highlighted for its efficiency and potential in powering AI applications, with Texas Instruments and Infineon leading developments in this area [36][38]. Conclusion - The semiconductor industry is at a pivotal point, driven by AI advancements and the need for innovative packaging and integration solutions. Companies like TSMC, Nvidia, and MediaTek are positioned to capitalize on these trends, while challenges in testing and power consumption remain critical areas for development [3][4][16][20].

Core Viewpoint - The rapid development of artificial intelligence (AI) is pushing the limits of traditional computing technologies, necessitating sustainable and energy-efficient solutions for exponential scaling of parallel computing systems [1][2][30]. Group 1: Technological Advancements - The article emphasizes the importance of optimizing the entire system from software and system architecture to silicon and packaging to maximize performance, power consumption, and cost [2]. - Key technologies such as RibbonFET and PowerVia are highlighted for their potential to enhance performance and efficiency in semiconductor design [4][5]. - High NA EUV technology is noted for its ability to simplify electronic design automation (EDA) and improve yield and reliability [7][8]. Group 2: 3D Integration and Packaging - 3D Integrated Circuits (3DIC) are crucial for achieving higher computational power in smaller areas while reducing energy consumption [11]. - The need for advanced packaging techniques to enhance interconnect density and energy efficiency is discussed, with a focus on modular design environments [12][15]. - The integration of glass in packaging to scale interconnect geometries and improve power transmission efficiency is identified as a significant technological advancement [14]. Group 3: Power Delivery and Efficiency - The article discusses the increasing power demands for AI workloads and the limitations of traditional motherboard voltage regulators (MBVR) [21][22]. - Fully Integrated Voltage Regulators (FIVR) are proposed as a solution to improve power conversion efficiency by bringing voltage regulation closer to the chip [23][24]. - The potential of pairing high-voltage switch-capacitor voltage regulators with low-voltage integrated voltage regulators for enhanced power density and efficiency is explored [24]. Group 4: Software and Ecosystem Collaboration - Software is deemed a critical component of the innovation matrix, requiring collaboration within the open-source ecosystem to enhance security and streamline processes [25]. - The need for industry-wide collaboration to develop next-generation advanced computing systems is emphasized, ensuring alignment with market demands and sustainability [28]. Group 5: Industry Challenges and Opportunities - The article outlines the challenges faced in achieving exponential performance improvements for AI, including power, connectivity, and cost issues [30]. - It calls for innovative approaches across various domains, including process technology, 3DIC system design, and power delivery, to meet the industry's computational demands [30].