公众号记得加星标⭐️，第一时间看推送不会错过。 来源 ：内容来自 moneyDJ 。 台积电(2330)持续加快在美国布局，业界最新传出，台积电在美国所规划的两座先进封装厂(AP1、 AP2)刚进入整地工程，预计于2026年下半年开始盖厂，目标2028年开厂启用。在制程规划上，AP1 规划扩充最先进的SoIC及CoW，AP2则是锁定CoPoS，以因应当地生产AI、HPC芯片封装需求。 台积电先前表示，美国第三座晶圆厂(P3)将采用N2和A16制程技术，第四座晶圆厂(P4)也将采用N2 和A16制程技术，第五座和第六座晶圆厂(P5、P6)则将采用更先进的技术。这些晶圆厂的建设和量产 计划将依客户的需求而定，并计划在亚利桑那州兴建两座新的先进封装设施，以及设立一间研发中 心，以完善AI供应链。 台积电有了美国第一座晶圆厂所累积的经验后，目前整体扩厂进度加速中，且相当顺利。业界最新消 息指出，公司正计画美国第二座晶圆厂(P2)的B区提前导入2纳米制程(原本在P3)。而先进封装厂则位 于P3对面、隔一道马路，原本预计2027后才要兴建，现在大幅加快到2026年下半年。 业界人士表示，封装厂建置速度相较晶圆厂来得快，以 ...

Core Viewpoint - TSMC's CoWoS advanced packaging technology is experiencing a supply-demand imbalance, with a capacity utilization rate of only 60%, leading to supply chain disruptions [2][3] Group 1: Capacity Expansion Plans - TSMC plans to increase its CoWoS capacity by 33% by 2026, driven by strong demand for AI computing power [4][6] - The expansion will benefit the AI ASIC supply chain and companies like NVIDIA that rely heavily on advanced semiconductor technology [5][6] - The new facilities, including the AP8 wafer fab, will support various production lines, with a focus on AI applications [2][4] Group 2: Market Dynamics and Demand - Despite strong AI demand, there are indications that procurement of CoWoS equipment may slow down after existing orders are fulfilled [3][4] - The rapid expansion of TSMC's capacity may have outpaced actual demand, leading to potential adjustments in wafer production from clients like NVIDIA and AMD [2][3] - The semiconductor industry is witnessing increased investments to meet the growing demand for AI and high-performance computing solutions [6]

Core Insights - The article discusses the projected demand for CoWoS wafers, predicting that global demand will reach 1 million pieces by 2026, with TSMC dominating the capacity allocation and Nvidia securing 60% of the CoWoS capacity [1][2]. Group 1: TSMC and CoWoS Technology - TSMC is expected to produce approximately 510,000 CoWoS wafers for Nvidia's next-generation Rubin architecture AI chips, which will account for about 60% of the global market demand [1]. - The CoWoS technology is crucial for enhancing signal transmission efficiency and chip density while reducing power consumption and heat dissipation, making it the standard packaging method for high-end AI chips [3]. Group 2: US Manufacturing Expansion - TSMC plans to build an advanced packaging facility in Arizona, which will include CoWoS, SoIC, and CoW technologies, with 60% of the capacity dedicated to Nvidia [2]. - The establishment of the US facility aims to strengthen the local supply chain, mitigate geopolitical risks, and address the increasing demand for advanced packaging technologies driven by AI and high-performance computing chips [2]. Group 3: Investment and Future Projections - Since Trump's second term, TSMC has announced a total investment plan of up to $100 billion, covering wafer fabs, R&D centers, and advanced packaging facilities [2]. - The anticipated output from Nvidia's chips could reach 5.4 million units by 2026, with 2.4 million units coming from the Rubin platform [1].

Core Viewpoint - The article discusses the challenges faced by Rapidus in achieving its ambitious goals in the semiconductor industry, particularly in the context of AI chip production and the transition to 3D IC technology. Group 1: Rapidus and AI Chip Production - Rapidus is focusing on advanced packaging technologies to secure orders from major clients like GAFAM in the growing AI market [4][8] - The company aims to mass-produce 2nm chips by 2027, but there are doubts about its capability to achieve this in the front-end process [7][8] - The article argues that Rapidus's goal of ultra-short turnaround time (TAT) for AI chip packaging is unrealistic due to various technological and supply chain challenges [71] Group 2: Transition to 3D IC Technology - The semiconductor industry is experiencing a paradigm shift from front-end processing to back-end 3D IC technology, which integrates multiple chips into a single package [29][31] - This shift is driven by the limitations of traditional scaling methods and the need for higher performance in AI applications [26][29] - Rapidus's entry into the 3D IC field aligns with industry trends, but achieving its goals will require overcoming significant hurdles [31][71] Group 3: Challenges in HBM Production - The production of High Bandwidth Memory (HBM) is a bottleneck for AI chip manufacturing, with a lead time of approximately six months [67] - HBM production is complex and costly, with a significantly lower yield compared to standard DRAM, making it a critical factor for companies like Rapidus [66][67] - The current market for advanced HBM is dominated by suppliers like SK Hynix, which has sold out its 2025 production capacity, further complicating Rapidus's plans [68][71]

Investment Rating - The report initiates coverage of K&S (KLIC US) with a Buy rating, and BE Semiconductor (BESI NA) with a Neutral rating, while maintaining a Buy rating on ASMPT (522 HK) [3][6][11]. Core Insights - Advanced packaging (AP) is expected to evolve significantly from 2025 onwards, with a shift from CoWoS-S to CoWoS-L/R, increased adoption of SoIC driven by HBM5, and potential upgrades in InFO technology led by Apple [3][6]. - The semiconductor cycle's recovery is a key catalyst for K&S and ASMPT, given their substantial sales exposure to conventional packaging [3][6]. CoWoS Technology - CoWoS technology is transitioning from CoWoS-S to CoWoS-L, with TSMC expected to increase its CoWoS-L capacity from approximately 20% in 2024 to nearly 60% in 2025 [7][21]. - CoWoS-S is anticipated to face oversupply due to non-TSMC supply chain expansions, while CoWoS-L is expected to be in demand for high-end GPUs [7][28]. SoIC Technology - SoIC is projected to gain importance with the adoption of high-NA EUV technology, although headwinds are expected in 2025 due to limited new adopters and potential capex constraints from Intel [8][14]. - AMD is currently the major adopter of SoIC, with potential future demand driven by Apple and HBM technologies [8][14]. InFO Technology - Apple is likely to adopt upgraded InFO technology from 2026 onwards, necessitating capacity upgrades to accommodate new application processor designs [9][20]. - The transition from InFO-PoP to InFO-M is expected as the I/O count between DRAM and application processors becomes insufficient [9][20]. Company-Specific Insights - K&S is positioned to be the primary TCB supplier for TSMC's on-wafer process starting in 2025, benefiting from the shift towards CoWoS-L technology [3][6]. - ASMPT is expected to gain market share in the HBM market from a low base, with its TCB potentially adopted by TSMC and Apple in the future [3][6]. - BE Semiconductor faces challenges due to rich valuations and potentially disappointing hybrid bonding orders in 2025 [3][6].

Investment Rating - The report assigns an "Overweight" rating to TSMC with a price target of NT$1,275.0 by December 2025 [2][28]. Core Insights - TSMC is expected to maintain strong structural growth drivers due to its near-monopoly position in AI accelerators and edge AI, supported by a robust process roadmap and industry-leading packaging technology [28]. - The report anticipates a significant ramp-up in TSMC's wafer-level multichip module (WMCM) capacity, particularly for high-end iPhone models, which could lead to substantial revenue growth [5][11]. - CoWoS (Chips-on-Wafer-on-Substrate) capacity is projected to remain tight through the second half of 2025 but is expected to reach a more balanced situation by the second half of 2026 [3][4]. Summary by Sections CoWoS Capacity and Demand - TSMC's CoWoS capacity is expected to grow significantly, reaching 102,000 wafers per month (wfpm) by the end of 2027, with a growth rate of 138% in 2025 [3]. - NVIDIA's CoWoS demand is projected to grow by 25% in 2026, reaching 538,000 units, driven by the migration to the Rubin platform [4][9]. - Overall CoWoS consumption is forecasted to increase from 679,000 wafers in 2025 to 1,132,000 wafers in 2027, reflecting a year-on-year growth of 32% [9]. WMCM Capacity and Adoption - WMCM capacity is expected to reach 27,000 wfpm by the end of 2026 and ramp up to 40,000 wfpm by the end of 2027, driven by Apple’s adoption in high-end iPhone models [5][11]. - If all iPhones were to migrate to WMCM long-term, this would require approximately 90,000 wfpm of WMCM capacity, indicating a significant expansion plan [5]. Customer Demand and Projections - Broadcom is expected to see steady growth in CoWoS consumption, particularly for Google TPUs, while new customers like Meta are anticipated to ramp up in 2026 [4]. - AMD's CoWoS forecasts remain muted for 2025 and 2026, with potential growth expected in the MI450 series in late 2026 and beyond [4]. - The report highlights that the CoWoS ecosystem is maturing, with more non-AI processors beginning to adopt CoWoS packaging, indicating broader market adoption [4]. Future Outlook - TSMC's structural growth is expected to be supported by price hikes on leading-edge nodes and a strong ramp-up of N2 technology in 2026 [28]. - The report suggests that TSMC will likely raise its FY25 USD revenue guidance, alleviating concerns regarding gross margin impacts from overseas expansion and currency fluctuations [28].

Core Viewpoint - TSMC's CoPoS packaging technology is gaining attention in the market, with plans for its first production line set to be established by 2026 and large-scale production expected between late 2028 and 2029, with NVIDIA as the first customer [1][2] Group 1: CoPoS Technology Development - TSMC's CoPoS is a variant of the CoWoS technology, designed to optimize space and reduce costs, with dimensions of 310x310 mm [1] - The focus of CoPoS packaging will be on advanced applications such as AI, with specific processes targeting companies like Broadcom, NVIDIA, and AMD [1][2] Group 2: Production Timeline and Facilities - TSMC's AP7 facility in Chiayi is planned to have eight phases, with CoPoS expected to achieve large-scale production in phase P4 [2] - The AP7 site is strategically chosen for its larger area and advanced technology, allowing for the integration of multiple packaging technologies [2] Group 3: Future Production and Technology Integration - The timeline for CoPoS includes equipment testing starting mid-next year, with small-scale production anticipated in 2027, followed by process validation and large-scale production by the end of 2028 [2] - TSMC aims to provide optimal solutions by integrating various technologies such as SoIC, CoWoS, and CoPoS for HPC chip packaging below 2nm [2]

Core Viewpoint - TSMC is expanding its advanced packaging capacity, but the timeline for the AP7 plant in Chiayi has been delayed, raising concerns about the impact on global HPC chip supply [1][2]. Group 1: Plant Development and Delays - TSMC's AP7 plant in Chiayi was initially scheduled for equipment installation in Q3, but this has been postponed to Q4 due to recent safety incidents at the site [1][2]. - The Chiayi County Mayor mentioned that the first phase of the plant's construction is expected to proceed in Q3, despite industry reports indicating a delay [1][2]. - The Chiayi plant is set to focus on wafer-level multi-chip module (WMCM) packaging, which is anticipated to be used in Apple's self-developed chips [1][2]. Group 2: Safety Incidents and Their Impact - Two safety incidents involving different contractors have led to work stoppages at the Chiayi plant, which may affect the construction timeline [2]. - The Occupational Safety and Health Administration has stated that TSMC, as the owner, is involved in discussions to enhance safety measures following these incidents [2]. Group 3: Future Production Capacity - TSMC is planning to establish two advanced packaging plants in Chiayi, with recruitment for technical staff already underway, offering salaries above NT$700,000 [2]. - The AP7 plant is expected to have a monthly production capacity of 4,000 to 5,000 units for SoIC by 2024, with potential increases in subsequent years [4]. - TSMC's SoIC technology is set to be utilized by major clients, including AMD and Apple, with the latter expected to implement it in the M5 chip [5]. Group 4: Overall Industry Outlook - Despite concerns about capacity constraints due to TSMC's investments in the U.S., the progress of the AP8 and AP7 plants in Taiwan is reportedly accelerating [4]. - The industry anticipates growth in operations as new advanced packaging facilities come online and testing facilities continue to expand capital expenditures [6].

随着台积电拿走芯片制造更多利润，产业风险也在进一步聚集。 文丨 邱豪 贺乾明 编辑丨龚方毅 1990 年代，硅谷诞生数十家只设计、不制造的芯片公司（Fabless）。AMD 创始人杰瑞·桑德斯（Jerry Sanders）在一场行业会议上说："现在听我说，真正的 男人要有晶圆厂"。他认为，只做设计的芯片公司，只能在晶圆厂有空余产能时才能下单，还得把设计图纸无保留地交给竞争对手，容易让公司陷入困境。 十多年后，芯片行业沿着桑德斯预想的糟糕情况发展。按照他的标准，当前最强的一批芯片公司——苹果、英伟达、博通、高通等，都不是 "真男人"。AMD 也变成一家纯设计芯片的公司，经历多年阵痛后，在女性 CEO 苏姿丰带领下走出困境。 晶圆厂依旧重要，只是没几家能建得起最先进的。台积电保持绝对优势，生产全球 60% 的逻辑芯片、90% 的 5 纳米以内先进芯片。先进芯片制造领域，台积 电仅剩的两个对手各有各的困境： 与此同时，台积电董事长魏哲家在二季度财报电话会上提出 "Foundry 2.0" 的概念，称台积电的业务范围覆盖先进芯片的制造、封装、测试等流程。芯片设计 公司只要给台积电递交设计文件（GDS），几个月后就能收 ...