Group 1 - The core viewpoint of the article is that STMicroelectronics is investing over $60 million to develop next-generation panel-level packaging technology at its facility in Tours, France, with operations expected to start in Q3 2026 [2] - This investment is part of a broader plan to reshape the company's manufacturing footprint, focusing on advanced manufacturing infrastructure in France and Italy [2] - The company has been developing panel-level packaging using direct copper interconnect (PLP-DCI) since 2020, which improves electrical performance, heat dissipation, and miniaturization while reducing power loss [2] Group 2 - The current automated PLP-DCI production line in Malaysia produces over 5 million large panels (700x700 mm) daily [2] - The project is expected to benefit from synergies with the local research ecosystem, including the CERTEM R&D center [2] - Panel-level packaging is an advanced chip packaging and testing technology that enhances efficiency, reduces costs, and enables smaller, more powerful, and cost-effective devices [2]

Core Viewpoint - The article discusses the commercialization and development stages of panel-level packaging (PLP) technology, highlighting its potential advantages over traditional wafer-level packaging (WLP) and the challenges it faces in the industry [2][3][6]. Group 1: Panel-Level Packaging Development - Panel-level packaging is currently in the industry cultivation stage, focusing on application scenario development, with the first phase targeting discrete devices and power SiP adopting PLP technology [3]. - The second phase involves the integration of mixed-signal multi-chip packaging into PLP technology, primarily for consumer electronics and IoT products [3]. - The final phase will see the introduction of memory-compute integrated chips using PLP technology, expected to commence in 3-5 years, marking the competitive phase against wafer-level 2.5D/3D packaging [3]. Group 2: Technical and Operational Challenges - Panel-level packaging faces high operational costs, poor technical stability, and an incomplete industrial ecosystem, which are significant barriers to its widespread adoption [6]. - The large size of the panels complicates the chip placement and bonding processes, increasing the difficulty of controlling displacement, line width, and stress [6]. - Establishing a panel-level packaging ecosystem requires new equipment and material supply chains, which necessitates substantial investment, particularly in high-end memory-compute integrated chip sectors [6]. Group 3: Upcoming Events and Industry Collaboration - TrendBank plans to host the Heterogeneous Integration Annual Conference from November 17-19, 2025, in Ningbo, focusing on advanced packaging technologies and fostering collaboration between industry and academia [7]. - The conference will cover core technologies such as multi-material heterogeneous integration, optoelectronic co-packaging, and advanced packaging techniques like TGV and FOPLP [7].

Core Viewpoint - The article discusses the current state and future potential of Panel Level Packaging (PLP) technology in China, highlighting its market size, key players, and the anticipated growth in the industry [2][3][4]. Market Overview - The existing market size for PLP in China is estimated at 38 million USD, accounting for 20% of the global PLP market, with expectations to exceed 100 million USD by 2028 [2]. - The PLP technology is still in the trial-and-error phase, with major companies expressing high expectations for its future applications in storage and computing chip packaging [2]. Key Players - Major global players in the PLP market include Samsung Electronics, ASE Group, STMicroelectronics, Powertech Technology, Hefei Silan Microelectronics, and Chongqing Silan Microelectronics [2]. - Domestic companies like Silan Microelectronics and Yicheng Technology are emerging as significant competitors, with Silan Microelectronics ranking among the top two in market share for power semiconductor PLP solutions [3]. Technological Development - The article emphasizes that domestic companies are accelerating the development of PLP platforms, preparing for a new technological iteration cycle in the packaging industry over the next 2-3 years [4]. - The focus of the upcoming conference will be on advanced packaging technologies, including multi-material heterogeneous integration and optical-electrical co-packaging [6]. Upcoming Events - TrendBank is organizing the 2025 Heterogeneous Integration Annual Conference from November 17-19, 2025, in Ningbo, aimed at fostering collaboration and innovation in the advanced electronic information industry [5][6].