Core Viewpoint - The Third Integrated Chip and Chiplet Conference will be held from October 10-13, 2025, in Wuhan, focusing on collaborative design and packaging to advance chip technology [1]. Event Overview - The conference is organized by Wuhan University, the Institute of Computing Technology of the Chinese Academy of Sciences, and Fudan University, featuring 7 keynote speeches and 16 technical forums [1]. - The theme is "Design and Packaging Collaboration, Building the Future of Chips," aiming to foster discussions on cutting-edge topics such as 3D integration, heterogeneous integration, multi-physical field collaboration, high-speed interconnects, EDA design methods, and advanced storage and packaging technologies [1]. Schedule Highlights - The opening ceremony will take place on October 11, 2025, followed by various sessions including: - Keynote on cutting-edge technology research in integrated chips [1]. - Forums addressing topics like storage and computing integration, multi-physical field simulation, and thermal management technologies [4]. - Notable speakers include experts from prestigious institutions such as the Chinese Academy of Sciences and Fudan University [4][1]. Participation Information - Registration for the conference can be completed online or on-site, with a countdown of only 2 days remaining until the event [5].

Core Viewpoint - The third Integrated Chip and Chiplet Conference will be held from October 10-13, 2025, in Wuhan, focusing on "Design and Packaging Collaboration to Build the Future of Chips" [2] Conference Overview - The conference will feature 16 technical sub-forums aimed at professionals in the integrated chip and chiplet technology fields, covering topics such as 3D integration, heterogeneous integration, multi-physical field collaboration, high-speed interconnects, EDA design methods, and advanced storage and packaging processes [2] - The event aims to foster collaborative innovation in integrated chip and chiplet technology, address key bottlenecks, and accelerate industry implementation [2] Agenda Summary - Registration will take place on October 10, 2025, from 14:00 to 20:00 at Wanda Reign Hotel [3] - The opening ceremony and keynote presentations are scheduled for the morning of October 11, followed by technical sub-forum reports in the afternoon [3] - The conference will continue with additional keynote presentations and sub-forum reports on October 12, along with self-service lunches and dinners [3] Sub-Forum Topics - Forum 1: Fusion of Storage and Computing for Large Models [5] - Forum 2: Multi-Physical Field Simulation for Integrated Chips [5] - Forum 3: Heterogeneous Integration of Memory and Computing Chips [5] - Forum 4: Optical I/O and Ultra-High-Speed Interfaces for Integrated Chips [5] - Forum 5: Thermal Management and Packaging Heat Dissipation Technologies [5] - Forum 6: Top Conference Forum - System Architecture [6] - Forum 7: Open Source Community Competitions [7] - Forum 8: IEEE Chiplet Workshop on Standards, Circuits, and Systems [7] - Forum 9: Advanced Packaging Processes and Hybrid Bonding for Chiplets [7] - Forum 10: Wafer-Level/Ultra-Wafer Size High-Performance Chips [7] - Forum 11: Heterogeneous Integrated 3D Power Supply Architectures [7] - Forum 12: Advanced Storage Chips Based on 3D Integration [7] - Forum 13: Silicon Interposer and Glass Substrate for Integrated Chips [7] - Forum 14: EDA Layout and Testing for Chiplet Integration [7] - Forum 15: Post-Processing 3D Heterogeneous Integrated Devices and Processes [8] - Forum 16: Top Conference Forum - Packaging Materials and Processes [8] Registration Information - Early bird registration ends on September 20, 2025, with registration available through the conference website [2][15]

申请入围"中国IC独角兽" 半导体高质量发展创新成果征集 近日有网友 透露 了海光的x86处理器路线图，显示未来将带来C86-5G处理器，拥有128核心512线程， 支持16通道DDR5-5600内存，128条PCIe 5.0通道为加速器、NVMe存储和高速网络提供了充足的带宽， 另外还支持AVX-512和CXL 2.0，还会有更为先进的电源管理和强化的安全引擎。得益于重新设计的微 架构，C86-5G的IPC相比于前一代的C86-4G提高17%以上。 显然C86-5G处理器这样的规格是为了高度并行的工作负载而设计的，海光将这款旗舰产品将成为人工 智能训练集群、大规模分析平台和虚拟化企业环境的理想选择。不过暂时还不清楚，C86-5G处理器将 采用哪一种制造工艺。 在多核性能这块，C86-5G简直"杀疯了"。它有128个物理核心，还能用四路SMT技术，一个核心能处理 四个线程，加起来就是512个线程。像英特尔第五代至强Emerald Rapids，才48核96线程，AMD EPYC Genoa-X也才96核，和C86-5G比起来，核心数差了一大截。这么多核和线程，在云计算、AI训练这些需 要同时处理海量任务的场景 ...