随着AI技术不断发展落地，行业应用对于算力的需求与日俱增，这已经成为广泛共识。 编辑部 整理自 MEET2026 量子位 | 公众号 QbitAI 与此同时，算法本身的规模和复杂度也在成倍增长，让整个行业正式迈入一个更高强度的算力周期，对此 太初元碁联合创始人兼首席运营官 乔梁 表示： 当下行业应用对于算力的需求与日俱增，AI需要算法实现毫秒级精确度，而这恰好带动算力需求呈指数级增长。 这意味着，在未来的技术演进中，高性能计算将贯穿生产制造、科学研究到AI落地的全链路，成为各类计算场景的底层支撑力量。 在本次 量子位MEET2026智能未来大会 上，乔梁围绕超智融合、异构融合等关键词分享了自己对国产算力生态建设的看法： 目前，各类AI大模型、不同领域的AI Agent落地都需要大量算力来支撑，在这一背景下，"超智融合发展"已成为行业共识。 无论是AI算法的迭代，还是传统科学计算的发展，未来的趋势都会指向同一件事：在通用计算的场景下，通过硬件架构的设计来实现异构融 合。 为了完整体现乔梁的思考，在不改变原意的基础上，量子位对演讲内容进行了编辑整理，希望能给你带来更多启发。 MEET2026智能未来大会是由量子位 ...

Core Viewpoint - The Third Integrated Chip and Chiplet Conference will be held from October 10-13, 2025, in Wuhan, focusing on collaborative design and packaging to advance chip technology [1]. Event Overview - The conference is organized by Wuhan University, the Institute of Computing Technology of the Chinese Academy of Sciences, and Fudan University, featuring 7 keynote speeches and 16 technical forums [1]. - The theme is "Design and Packaging Collaboration, Building the Future of Chips," aiming to foster discussions on cutting-edge topics such as 3D integration, heterogeneous integration, multi-physical field collaboration, high-speed interconnects, EDA design methods, and advanced storage and packaging technologies [1]. Schedule Highlights - The opening ceremony will take place on October 11, 2025, followed by various sessions including: - Keynote on cutting-edge technology research in integrated chips [1]. - Forums addressing topics like storage and computing integration, multi-physical field simulation, and thermal management technologies [4]. - Notable speakers include experts from prestigious institutions such as the Chinese Academy of Sciences and Fudan University [4][1]. Participation Information - Registration for the conference can be completed online or on-site, with a countdown of only 2 days remaining until the event [5].

Core Viewpoint - The third Integrated Chip and Chiplet Conference will be held from October 10-13, 2025, in Wuhan, focusing on "Design and Packaging Collaboration to Build the Future of Chips" [2] Conference Overview - The conference will feature 16 technical sub-forums aimed at professionals in the integrated chip and chiplet technology fields, covering topics such as 3D integration, heterogeneous integration, multi-physical field collaboration, high-speed interconnects, EDA design methods, and advanced storage and packaging processes [2] - The event aims to foster collaborative innovation in integrated chip and chiplet technology, address key bottlenecks, and accelerate industry implementation [2] Agenda Summary - Registration will take place on October 10, 2025, from 14:00 to 20:00 at Wanda Reign Hotel [3] - The opening ceremony and keynote presentations are scheduled for the morning of October 11, followed by technical sub-forum reports in the afternoon [3] - The conference will continue with additional keynote presentations and sub-forum reports on October 12, along with self-service lunches and dinners [3] Sub-Forum Topics - Forum 1: Fusion of Storage and Computing for Large Models [5] - Forum 2: Multi-Physical Field Simulation for Integrated Chips [5] - Forum 3: Heterogeneous Integration of Memory and Computing Chips [5] - Forum 4: Optical I/O and Ultra-High-Speed Interfaces for Integrated Chips [5] - Forum 5: Thermal Management and Packaging Heat Dissipation Technologies [5] - Forum 6: Top Conference Forum - System Architecture [6] - Forum 7: Open Source Community Competitions [7] - Forum 8: IEEE Chiplet Workshop on Standards, Circuits, and Systems [7] - Forum 9: Advanced Packaging Processes and Hybrid Bonding for Chiplets [7] - Forum 10: Wafer-Level/Ultra-Wafer Size High-Performance Chips [7] - Forum 11: Heterogeneous Integrated 3D Power Supply Architectures [7] - Forum 12: Advanced Storage Chips Based on 3D Integration [7] - Forum 13: Silicon Interposer and Glass Substrate for Integrated Chips [7] - Forum 14: EDA Layout and Testing for Chiplet Integration [7] - Forum 15: Post-Processing 3D Heterogeneous Integrated Devices and Processes [8] - Forum 16: Top Conference Forum - Packaging Materials and Processes [8] Registration Information - Early bird registration ends on September 20, 2025, with registration available through the conference website [2][15]

Core Viewpoint - The article discusses the advancements and specifications of the C86-5G processor developed by Haiguang, highlighting its potential applications in AI training, cloud computing, and large-scale data analysis due to its high core count and memory capabilities [2][3][5]. Processor Specifications - The C86-5G processor features 128 physical cores and supports 512 threads through four-way SMT technology, significantly outperforming competitors like Intel's Emerald Rapids and AMD's Genoa-X in core count [3][4]. - It supports 16-channel DDR5-5600 memory with a maximum capacity of 1TB, offering an 80% increase in data transfer bandwidth compared to Intel's 8-channel DDR5-4800 [5]. - The processor includes advanced connectivity options such as CXL 2.0 and PCIe 5.0, placing it on par with leading competitors [5]. Performance Insights - The C86-5G's IPC (Instructions Per Cycle) has improved by over 17% compared to its predecessor, the C86-4G, making it suitable for high-parallel workloads [2][6]. - While it excels in multi-threaded tasks, it has some limitations in single-core performance and cache capacity compared to AMD's offerings [5][6]. Development Timeline - Haiguang's development trajectory shows a clear evolution from reliance on AMD's Zen architecture (2016-2020) to self-developed microarchitectures starting in 2021, with the C86-4G marking a significant step in AI computing capabilities [6]. - The C86-5G represents an enhanced version of the self-developed architecture, incorporating hardware acceleration for national encryption algorithms, which is crucial for sectors requiring high security [6]. Future Prospects - Future iterations, such as the anticipated C86-6G, are expected to adopt smaller process nodes (5nm, 3nm), potentially increasing core counts and improving energy efficiency [6]. - Haiguang is also exploring heterogeneous integration, similar to AMD's MI300, to combine general computing and AI acceleration within a single chip [6]. Ecosystem and Collaboration - Haiguang has formed a coalition with over 5,000 partners and aims to optimize its processors with domestic operating systems, facilitating lower migration costs for core financial systems [7]. - The company is considering open-sourcing parts of its IP cores to foster a developer community around the C86 architecture, similar to the RISC-V model [7].