如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容编译自IEEE，谢谢。 中国科学家称，一块微芯片拥有近 6,000 个晶体管，每个晶体管只有三个原子厚，是迄今为止用 二维材料制成的最复杂的微处理器。 新器件采用半导体二硫化钼制成，这种材料由一层钼原子夹在两层硫原子之间构成。科学家们希 望，一旦硅材料无法继续发展，二硫化钼等二维材料能够使摩尔定律得以延续。 上海复旦大学微电子学院教授包文忠表示："尽管二维材料十多年来一直被广泛推崇，但其当前发 展的真正限制因素并非单一器件的性能，因为许多二维电子设备在实验室水平上已经运行良好。人 们之所以不断质疑二维材料的实用性，是因为缺乏可扩展、可重复且与工业流程兼容的集成技术体 系。" 这款名为RV32-WUJI的新微芯片拥有5931个采用现有CMOS技术制造的二硫化钼晶体管。研究人 员表示，相比之下，此前最大的二维逻辑电路由156个二硫化钼晶体管组成。鲍哲南表示，这些新 发现标志着"二维半导体材料从器件级实验室研究向系统级工程应用的转变，为后硅时代的半导体 技术提供了一种可行的替代方案"。 RV32-WUJI 搭 载 RISC-V 架 构 ， 能 够 执 行 标 准 ...

如果您希望可以时常见面，欢迎标星收藏哦~ IEEE IEDM 会议由 IEEE 电子器件学会主办，是全球规模最大、最具影响力的论坛，旨在展 示晶体管及相关微纳电子器件领域的突破性进展。 台积电研究人员发布了全球最先进的逻辑技术。这是该公司即将推出的 2 纳米 CMOS（即 N2） 平台，旨在实现人工智能、移动和高性能计算 (HPC) 应用的节能计算。与目前量产的最先进的逻 辑技术——台积电自主研发的 3 纳米 CMOS（N3）平台（于 2022 年底推出）相比，该平台在芯 片密度增加 1.15 倍以上的情况下，速度提升 15%（功耗降低 30%）。 全新 N2 平台采用 GAA 纳米片晶体管；中/后端线路互连，以及迄今为止密度最高的 SRAM 宏 （约 38Mb/mm²）；以及一个整体的、系统技术协同优化 (STCO) 架构，可提供出色的设计灵活 性。该架构包括可扩展的铜基重分布层和平坦钝化层（用于实现更佳性能、强大的 CPI 和无缝 3D 集成）；以及硅通孔 (TSV)（用于通过 F2F/F2B 堆叠传输电源/信号）。研究人员表示，N2 平台 目前处于风险生产阶段，计划于 2025 年下半年实现量产。 N2 ...

Core Viewpoint - A new microchip named RV32-WUJI, made from molybdenum disulfide, features nearly 6,000 transistors, marking a significant advancement in two-dimensional semiconductor technology and a potential alternative for the post-silicon era [1][2]. Group 1: Microchip Development - The RV32-WUJI microchip contains 5,931 transistors, significantly surpassing the previous record of 156 transistors in two-dimensional logic circuits [1]. - The chip is built on an insulating sapphire substrate, which isolates the transistors electronically [2]. - Researchers have developed a complete standard cell library with 25 logic units for basic functions like AND and OR [2]. Group 2: Manufacturing and Performance - The manufacturing yield achieved is 99.77%, despite the complexity of two-dimensional semiconductors and wafer-level processes [2]. - The transistor channel length is currently 3 micrometers, with plans to use better lithography tools to further reduce channel size and increase integration density [2]. Group 3: Power Consumption and Future Prospects - At a frequency of 1 kHz, the RV32-WUJI consumes only 0.43 milliwatts of power [3]. - While silicon chips have millions of times more transistors and operate at much higher frequencies, the researchers believe that embracing two-dimensional semiconductors could lead to performance surpassing silicon-based semiconductors faster than expected [3].

Core Viewpoint - The article discusses the transition of former Intel CEO Pat Gelsinger to xLight, a startup focused on revolutionizing EUV lithography technology through the use of particle accelerators, aiming to enhance semiconductor manufacturing efficiency and reduce costs significantly [1][5][6]. Group 1: Company Overview - xLight aims to commercialize Free Electron Lasers (FEL) powered by particle accelerators to produce EUV light, which is essential for advanced semiconductor manufacturing [4][6]. - The company claims its EUV light source will be four times more powerful than current technologies, potentially generating billions in additional annual revenue for semiconductor fabs [6][11]. Group 2: Technology and Innovation - Current EUV light generation methods, such as Laser Produced Plasma (LPP), are highly energy-intensive, producing only 500 watts of light from 1.5 megawatts of power [1][4]. - xLight's FEL technology is designed to be fully compatible with existing ASML tools, addressing the need for higher power sources (up to 2 kW) for future semiconductor manufacturing [4][5]. Group 3: Economic and Strategic Implications - The advancements in EUV technology are critical for maintaining the U.S.'s leadership in the semiconductor industry, which is vital for economic prosperity and national security [6][11]. - xLight's system is expected to reduce wafer costs by approximately 50% and lower capital and operational expenditures by over three times [6][11]. Group 4: Future Prospects - xLight is currently developing a fully functional prototype that will connect to ASML scanners and is expected to be operational by 2028 [6][8]. - The company believes its technology will not only enhance semiconductor applications but also address challenges in national security and biotechnology [7][8].

Core Viewpoint - The article draws a parallel between Tesla's Roadster and the current state of the chip industry, suggesting that the introduction of "optical-electrical hybrid computing" marks a new era in computing, similar to how the Roadster initiated the electric vehicle revolution [1][6]. Group 1: Industry Challenges - The traditional chip industry is facing limitations due to the failure of Moore's Law, which has been a guiding principle for over 60 years, with performance improvements slowing down significantly [3][4]. - The demand for computing power has surged, particularly driven by advancements in artificial intelligence, leading to a doubling of computational needs every 4-6 months [3][4]. - Current innovations, such as near-storage computing and non-GPU architectures, address bandwidth and transistor utilization issues but do not fundamentally resolve the limitations of transistor density and absolute computing power [4][5]. Group 2: New Paradigm Introduction - The company proposes a new paradigm called "optical-electrical hybrid computing," which aims to overcome the limitations of traditional transistors by utilizing optical components [5][6]. - The introduction of the "Tianshu" system represents a significant advancement, integrating optical chips with electrical chips in a novel 3D stacked architecture to enhance computational capabilities [7][9]. Group 3: Technical Innovations - The optical chip in the Tianshu system employs Optical Multiply Accumulate (oMAC) technology for integer operations, significantly improving computational power without additional energy consumption [8][10]. - The electrical chip is a custom ASIC designed for floating-point operations, and the integration of over 40,000 optical devices allows for high bandwidth and low latency in processing complex algorithms [9][10]. Group 4: Software and Ecosystem Development - The company has developed a software framework to support popular programming languages like PyTorch, facilitating the integration of complex algorithms into the Tianshu system [12][13]. - A performance index called Equivalent Optical Processing Power (EOPP) has been introduced, which combines peak processing power, output precision, and weight refresh rates to provide a more comprehensive measure of performance [14]. Group 5: Future Prospects - The company is exploring further applications of its technology in various fields, including EDA systems, quantitative trading, and security recognition, with plans to expand into more scenarios [14][15]. - Innovations in optical interconnect technologies, such as Optical Network on Chip (oNOC) and Optical inter-chip Networking (oNET), are being developed to enhance data transmission efficiency and flexibility in chip architectures [15][16].

当国内70%的IC企业聚焦Finfet工艺时，你的技术储备却还停留在28nm平面工艺？某头部企业HR透露： 掌握FinFET工艺的工程师薪资溢 价达35%！ 近两年来，不少芯片企业的项目招标明确要求需要具备 12nm及以上工艺项目经验 ！华为、TI、艾为等芯片行业大厂也在逐 渐做技术升级，FinFet将逐渐一步步替代平面工艺！比如华为最新发布的昇腾AI芯片就已采用了12nm的FinFET工艺，与台积电合作流片 之后，直接取代了早期28nm平面工艺方案。 随手一搜，现在的招聘网站上很多公司的模拟版图工程师的岗位要求里也都明确要求有FinFet项目经验！有FinFet项目经验者通常都会被优先考 虑，在求职找工作过程中能获得更大的优势和筹码！ 根据多家招聘平台数据，华为海思、艾为电子等企业自2023年起， 模拟版图工程师岗位明确要求12nm/7nm FinFET工艺项目经验 ，而 平面工艺相关岗位需求锐减70%。 之前，集成电路常见的制造工艺是CMOS工艺，但随着时代进步， 芯片工艺方面的发展趋势集中体现在持续的技术创新与进步，正朝着 更小的制程节点如12nm、7nm纳米乃至更精细尺度迈进，以此实现更高的集成度、更 ...

Core Insights - The semiconductor industry is experiencing an insatiable demand for high-performance, energy-efficient logic technologies, particularly driven by advancements in AI and 5G [2][5]. Group 1: 2nm Technology Development - TSMC's 2nm logic platform, showcased at the IEDM conference, emphasizes energy-efficient computing as a key pillar for mobile, AI PCs, and AI processing [1]. - The N2 platform utilizes nanosheet transistors, replacing FinFETs, achieving a 15% speed increase, 30% power improvement, and a 1.15x area increase compared to previous nodes [1]. - The N2 technology is expected to enter mass production in the second half of 2025 [1]. Group 2: Demand and Performance Optimization - The introduction of TSMC's NanoFlex technology allows for optimization of standard cells for performance, power, or density, enhancing energy efficiency at low operating voltages [2]. - At voltages below 0.6 Vdd, the N2 technology shows a 20% speed increase and significantly better performance per watt [2]. - Innovations in interconnect energy efficiency have led to a 55% improvement in gate contact resistance and a 20% reduction in resistance and capacitance in the middle of the line [3]. Group 3: SRAM Density and Future Projections - The SRAM density for the N2 platform is reported at 38.1 Mb/mm², surpassing the N5 generation's 32 Mb/mm² [4]. - TSMC anticipates that AI will drive substantial growth in various sectors, including personal computers, smartphones, robotics, and automotive applications, with AI smartphone growth projected to quadruple from 2024 to 2028 [5]. Group 4: Advanced Transistor Architectures - The industry is transitioning to Gate-All-Around (GAA) architectures as FinFET technology reaches its limits, with GAA providing better control over channel thickness and improved performance [8]. - TSMC researchers have developed a fully functional 3D monolithic CFET inverter, enhancing performance and design flexibility through vertical stacking of n-FET and p-FET transistors [9]. Group 5: Manufacturing Innovations - The introduction of back-side powered CFET devices is expected to increase device density while maintaining performance, despite the complexity of the manufacturing process [11][12]. - The industry is focused on overcoming challenges related to alignment, bonding, and ensuring comparable electron and hole mobility in vertically stacked devices [12][13].

Core Viewpoint - The strategic partnership agreement between Imec and Zeiss Semiconductor Manufacturing Technology aims to advance semiconductor technology development, particularly for research and development below 2 nanometers, extending their collaboration until 2029 [3][7]. Group 1: Partnership Details - The new agreement extends the existing partnership established in 2019, emphasizing the importance of collaboration in advancing semiconductor technology [3]. - Imec and Zeiss have been working together since 1997 on various joint projects to further develop Moore's Law, which continues to enhance microchip and memory processor performance [3][5]. - The partnership focuses on key semiconductor manufacturing technologies, including high numerical aperture EUV lithography, which is essential for producing more powerful and energy-efficient microchips [3][5]. Group 2: Technological Advancements - Imec's NanoIC pilot line is being expanded to cover the entire value creation process and various technology chains in semiconductor manufacturing [5]. - The pilot line aims to provide groundbreaking and advanced semiconductor technologies and platforms for industry representatives, enabling them to explore, develop, and test innovations [5]. - Both companies are committed to optimizing existing equipment, processes, and measurement methods to achieve smaller, more powerful, and energy-efficient microchips, driving global digitalization [5][8]. Group 3: European Chip Act Compliance - The collaboration aligns with the goals of the European Chip Act, which aims to strengthen Europe's technological sovereignty, competitiveness, and resilience [7]. - Zeiss's investment in the NanoIC pilot line contributes significantly to maintaining Europe's leadership in the latest generation of semiconductor equipment [7]. - The partnership highlights the strong cohesion among European partners, which is crucial for establishing the NanoIC pilot line, recognized as the world's most advanced R&D infrastructure below 2 nanometers [8].

Core Viewpoint - The research from the University of California, Santa Barbara (UCSB) introduces a significant advancement in semiconductor technology through the development of new 3D transistors utilizing 2D semiconductor technology, paving the way for energy-efficient and high-performance electronic products [1][2]. Group 1: Breakthrough in Transistor Miniaturization - The strategy to enhance device performance involves miniaturizing transistors to allow for denser packaging and more operations on the same chip size [2]. - Traditional silicon technology faces limitations in miniaturization due to the "short-channel effect," which leads to subthreshold leakage and poor switching performance, making it challenging to maintain low power consumption while reducing transistor size [2][3]. - The introduction of Fin-FET technology over a decade ago has alleviated many of these limitations, but scaling down to channel lengths below 10 nanometers while maintaining performance and low power consumption is increasingly difficult [2]. Group 2: 2D Semiconductor Integration - UCSB's research demonstrates that using 2D semiconductors in 3D gate-all-around (GAA) transistor structures can enhance electrostatic characteristics, enabling the creation of transistors with channel lengths reduced to a few nanometers, significantly improving performance and energy efficiency [3][5]. - The newly introduced nanosheet FET architecture maximizes the unique properties of atomically thin 2D materials, such as tungsten disulfide (WS₂), achieving a tenfold increase in integration density while maintaining performance metrics [5]. Group 3: Advanced Simulation Tools - The research team employed cutting-edge simulation tools, including QTX, to evaluate the performance of their designs, allowing for the simulation of critical factors such as non-parabolic energy bands and contact resistance [7]. - The combination of advanced quantum transport methods with practical considerations like non-ideal contact resistance and capacitance results in a comprehensive and realistic framework for transistor design [7]. Group 4: Future Prospects - The findings indicate that 3D-FETs based on 2D semiconductors outperform silicon-based 3D-FETs in key metrics such as drive current and energy-delay product, with the thinness of 2D materials reducing device capacitance and power consumption [8]. - The UCSB team plans to deepen collaborations with industry partners to accelerate the adoption of these technologies and improve models by incorporating real-world factors [8]. - This research not only showcases the potential of 2D materials but also provides a detailed blueprint for their integration into 3D transistor designs, marking a crucial step in the semiconductor industry's pursuit of continuing Moore's Law [8].

作者 | Simple Investment Ideas 编译 | 华尔街大事件 台积电 ( NYSE: TSM ) 有望在未来几年内占据 AI 行业的大部分利润。该公司将最先进的技术 和不断增长的财务实力相结合，以巩固其作为全球领先专用芯片代工厂的地位。这一优势使台 积电在日益激烈的 AI 军备竞赛中从激增的 AI 芯片需求中获取价值。虽然许多公司都在设计 AI 硬件，但台积电在大规模生产这些芯片方面拥有无与伦比的能力，这意味着它在未来可能会 获得更大的行业利润份额。 台积电在工艺节点工程方面 领先多年 ，在大规模生产高产量芯片方面也有成功记录。台积电 的财务实力只会进一步巩固该公司的主导地位。台积电的专业芯片制造知识和资本密集度创造 了一条似乎越来越难以逾越的竞争护城河。与此同时，当前的人工智能趋势正在改变芯片设 计，这只会进一步巩固台积电的主导地位。 台积电能够超越那些最积极进取、资金最雄厚的竞争对手的一个核心原因是其拥有丰富的专业 知识。先进的半导体制造工艺处于无法轻易复制或购买的顶端。相反，它是数十年工艺改进、 边学边做和克服无数工程挑战的结晶。台积电的晶圆厂本身就是 极其复杂的运营 ，充满了数 十 ...