芯粒技术

Search documents
清华大学集成电路学院副院长唐建石:高算力芯片,如何突破瓶颈?
Xin Lang Cai Jing· 2025-10-03 07:16
为突破现有瓶颈,唐建石团队将芯片算力拆解为"晶体管集成密度 × 芯片面积 × 单个晶体管算力" 三个 核心要素,针对每个要素展开技术探索。 来源:半导体产业纵横 2025 年9月24日,清华大学集成电路学院副院长、长聘副教授唐建石在2025 IC WORLD 高峰论坛上, 发表题为《高算力芯片发展路径探索与存算一体芯片》的演讲。演讲围绕学院近年在高算力芯片与存算 一体芯片领域的思考、探索及实践展开,系统阐述了行业现状、技术突破与未来规划。 从他的演讲中,我们获取了以下关键信息: 唐建石指出,当前人工智能领域对算力的需求呈爆发式增长,国家计算力指数与数字经济、GDP 增长 紧密相关。其中,中国智能算力规模 2025 年已突破数十万亿亿次,且 AI 算力需求每不到六个月便实 现翻倍,这一增速远超摩尔定律驱动的硬件算力提升速度,构建更强力的芯片算力底座成为行业迫切需 求。 同时,计算芯片与存储芯片存在显著差异:存储芯片拥有统一的标准接口与定义,而计算芯片需依赖指 令集、工具链、操作系统构成的完整生态支撑。从行业格局看,美国长期主导计算芯片体系,我国则面 临双重硬件制约:一是摩尔定律逐步放缓,晶体管尺寸微缩难度加大, ...
AI时代芯片设计复杂度大幅提升,Arm提出新解题思路
2 1 Shi Ji Jing Ji Bao Dao· 2025-04-30 08:25
Core Insights - The report by Arm highlights the increasing complexity in chip design due to the slowing of Moore's Law and the rising demands of AI workloads, emphasizing energy efficiency as a primary consideration for AI computing [1][2] - The semiconductor industry is shifting towards innovative alternatives such as custom chips, compute subsystems (CSS), and chiplets to enhance performance and efficiency [1][2] Chip Design Challenges - Achieving a balance between computing power and energy efficiency is a significant challenge, necessitating close collaboration with foundries to optimize transistors for both dynamic and leakage power [2] - Optimization must occur at various levels, from transistor to architecture, including SoC design and data center operations, with a focus on protecting data during transmission to reduce power consumption [2] Custom Chip Trends - Custom chips are becoming a crucial trend in the semiconductor industry, with major cloud service providers accounting for nearly half of global cloud server procurement spending in 2024 [3] - The key to custom chip design lies in ensuring high reusability between chips and software, which helps address cost and time-to-market challenges [3] Security Considerations - As AI technology evolves, so do security threats, prompting the semiconductor industry to develop multi-layered hardware and software protection systems [3] - AI is also being leveraged to enhance security measures, enabling rapid identification of suspicious activities and potential vulnerabilities [3] Software Ecosystem Importance - The software ecosystem is vital for unlocking the potential of new chip architectures, requiring seamless compatibility with AI frameworks and optimization support for custom chips [4] - The slowing of Moore's Law necessitates closer collaboration between chip design and manufacturing, with advanced packaging technologies driving innovation [4] Chiplet Technology - Chiplet technology is still in its early exploratory phase, with standardization of design and interfaces being critical for effective integration and communication between chiplets [5] - Arm's Chiplet System Architecture (CSA) aims to standardize communication methods among chiplets, ensuring interoperability across different suppliers [5] Advanced Packaging and Performance - The demand for AI computing is accelerating the convergence of various technologies, with chiplet designs allowing for modular isolation of different functional blocks to enhance cost-effectiveness [6] - Advanced packaging techniques, such as 3D packaging, improve performance and efficiency by reducing data transmission distances and power consumption [6] Standardization Benefits - The true value of advanced packaging and chiplet technology lies in standardization, enabling rapid configuration of chiplets to meet diverse performance needs, thus shortening product time-to-market [7]