Core Viewpoint - The 2026 Munich Shanghai Optical Expo will be held from March 18 to 20, showcasing cutting-edge technologies and quality resources in the optoelectronic field, with a focus on driving high-quality industry development [1][2]. Group 1: Event Overview - The expo will feature a dedicated semiconductor display area, co-hosted by Semiconductor Industry Observer, covering 27 square meters [2]. - The event aims to connect industry value and support the innovative development of the semiconductor industry in advanced packaging, silicon photonics integration, and chip design [4]. Group 2: Participating Companies - Four leading companies will participate: Zhuhai Silicore Technology Co., Ltd., Guokai Guangxin (Haining) Technology Co., Ltd., Shanghai Langxi Technology Co., Ltd., and Shenzhen Guangjian Technology Co., Ltd. [4][5]. - These companies are recognized for their core technological breakthroughs and mature industrial practices, contributing significantly to the upgrade of the domestic semiconductor industry [5]. Group 3: Company Highlights - **Zhuhai Silicore Technology Co., Ltd.** focuses on EDA software for 2.5D/3D stacked chips, with a closed-loop design platform that supports various chip applications, addressing industry pain points [7][8]. - **Guokai Guangxin (Haining) Technology Co., Ltd.** specializes in silicon nitride silicon photonics technology, achieving high yield production with transmission loss at 0.1 dB/cm and over 95% process yield [13][14]. - **Shanghai Langxi Technology Co., Ltd.** leads in silicon-based passive devices, with breakthroughs in 3D silicon capacitors that exceed traditional ceramic capacitors in lifespan and reliability [18][19]. - **Shenzhen Guangjian Technology Co., Ltd.** has developed a full-stack solution for nano-photonics chips and 3D visual perception, successfully overcoming overseas patent barriers [23][24]. Group 4: Industry Impact - The semiconductor display area will serve as a vital platform for showcasing core strengths and linking industry resources, facilitating discussions on industry trends and potential collaborations [26].

Core Viewpoint - The article highlights the upcoming Munich Shanghai Optical Expo as a key platform for the semiconductor and optoelectronics industry, focusing on collaborative innovation from devices to networks, particularly in the context of CPO (Co-Packaged Optics) technology [1][2]. Group 1: Industry Trends - The semiconductor industry is evolving towards "device miniaturization, advanced packaging, and high-speed networking," with collaborative innovation from devices to networks being crucial for overcoming computational and communication bottlenecks [2]. - CPO technology is identified as a pivotal hub connecting "devices, packaging, and networks," necessitating higher requirements for collaborative design due to its role in AI data centers and high-speed interconnect scenarios [2]. Group 2: Challenges in the Industry - The increasing complexity of heterogeneous integration, higher adaptability requirements between devices and networks, and the challenges in design-process-application collaboration are significant pain points hindering large-scale industry advancement [2]. - The bottleneck in CPO development has shifted from optimizing individual components to achieving overall system-level collaboration, which includes considerations for thermal, stress, and signal integrity [2]. Group 3: Company Contributions - Zhuhai Silicore Technology, a leading domestic EDA company, will participate in the forum, showcasing its next-generation 2.5D/3D stacked chip EDA solutions aimed at addressing design bottlenecks in the "device-packaging-network" collaboration [1][3]. - The company's 3Sheng Integration Platform has been validated by leading domestic advanced packaging manufacturers and supports mainstream processes like CoWoS and high-density substrate fan-out, facilitating complex scenarios in silicon photonics integration [3]. Group 4: Forum Highlights - The forum will feature three core technology presentations from Zhuhai Silicore Technology, focusing on EDA solutions for silicon photonics chips, collaborative breakthroughs in CPO technology, and the establishment of an advanced packaging ecosystem [7][9][11]. - The EDA+CPO technology collaboration aims to address core challenges in the entire link, including signal integrity, thermal reliability, and packaging parasitics, facilitating scalable deployment of CPO solutions [9][10]. Group 5: Networking Opportunities - The forum will provide a platform for industry professionals, including semiconductor manufacturers, network equipment vendors, and advanced packaging practitioners, to engage in discussions and find collaborative innovation solutions [15].

Core Insights - Nvidia's investment in Synopsys and collaboration with EDA tool providers highlights a shift in the semiconductor industry towards system-level optimization rather than just process competition [3] - The trend indicates that advanced packaging and EDA tools are becoming critical for enhancing performance and controlling costs in semiconductor design [3][13] - The local semiconductor industry is encouraged to leverage this paradigm shift to create opportunities for growth and innovation [3][15] Group 1: EDA+ Concept - The EDA+ framework proposed by Silicon Chip Technology aims to reconstruct the design, simulation, and verification processes for advanced packaging [7] - EDA+ is not merely an addition to traditional EDA tools but represents a comprehensive redesign focused on 2.5D/3D integration [7][13] - The 3Sheng Integration Platform serves as the foundational technology for EDA+, facilitating a complete engineering loop from system architecture to manufacturing verification [12] Group 2: Industry Trends - The semiconductor industry's shift towards advanced packaging is driven by the need for enhanced computational power and the limitations of Moore's Law [13] - EDA's role is evolving to become a critical link between design and manufacturing, necessitating a unified environment for considering various design factors [13][14] - Major players like TSMC and Nvidia are establishing partnerships to secure competitive advantages through deep integration of EDA and manufacturing processes [15] Group 3: Implementation and Value - EDA+ has already been implemented in several 2.5D/3D projects, significantly reducing design convergence time from three months to approximately ten days [14] - The platform is also exploring the development of reusable chiplet models, which will enhance collaboration across different manufacturers and technology nodes [14] - EDA+ provides a framework for deep industry collaboration, allowing for the transfer of manufacturing knowledge to the design phase and vice versa [14] Group 4: Opportunities for Local Industry - The local semiconductor industry can adopt a strategy of vertical and horizontal collaboration to compete with international giants [15] - Vertical collaboration involves strengthening the connections between different stages of the supply chain using platforms like EDA+ [15] - Horizontal collaboration focuses on cooperation among local EDA firms to cover the complex advanced packaging design process, potentially leading to a unified approach in the Chiplet and 3DIC markets [15][18]

Core Insights - The 2025 New Domain New Quality Innovation Competition concluded successfully, attracting participation from 31 provinces and 43 top universities in China, with a total of 770 innovative projects submitted [1] - Zhuhai Silicore Technology Co., Ltd. won the grand prize for its project on the development and industrialization of next-generation 2.5D/3D stacked chip EDA, becoming the only company in Guangdong to receive this honor [1] Company Highlights - Silicore Technology has developed the "3Sheng Integration Platform," which provides a complete domestic toolchain from modeling, design, simulation, verification to testing, addressing the needs of domestic Chiplet integration and multi-chip system verification [3] - The platform has successfully overcome key bottlenecks in enhancing the performance of high-computing chips under advanced process limitations and has been applied in the design and optimization of AI, GPU, and CPU chips [3] - The company promotes a collaborative ecosystem by integrating design, advanced packaging EDA, and manufacturing, thereby enhancing resource integration within the semiconductor and integrated circuit industry [3] Industry Trends - The Xiangzhou District has implemented an innovation-driven development strategy, focusing on critical technology challenges in areas such as high-energy lasers, MOF materials, synthetic biology, aerospace, high-performance chips, and connectors [4] - The district aims to continue developing new quality productivity and support high-quality regional economic development by leveraging its industrial foundation and resource endowments [4]

Core Viewpoint - The article emphasizes the significance of the 3Sheng Integration Platform developed by Silicon Chip Technology for the design and testing of 2.5D/3D stacked chips, highlighting its innovative features and capabilities in enhancing reliability and performance in chip systems [3][34]. Group 1: 3Sheng Integration Platform - The 3Sheng Integration Platform integrates system-level planning, physical implementation, analysis, testability, and reliability design for 3D stacked chips, supporting agile development and customizable collaborative design optimization [3][34]. - The platform features a unified data foundation and combines five engines: system, test, synthesis, simulation, and verification, showcasing originality in multiple functionalities and performance [3]. Group 2: Importance of DFT in Stacked Chips - Design for Testability (DFT) is crucial in stacked chip systems due to the unique interconnect testing requirements arising from multiple chiplets, necessitating specific testing before and after interconnection [6][10]. - The interconnect interfaces in stacked chips introduce new testing demands, including compatibility, connectivity integrity, and defect detection, which are not present in conventional chips [10][12]. Group 3: Testing Processes and DFT Requirements - The testing process for stacked chips includes pre-bond, mid-bond, post-bond, and final tests, with the accuracy and completeness of these tests being vital for product quality and cost-effectiveness [13][15]. - DFT plays a significant role in ensuring testability, controllability, and self-repair capabilities within the stacked chip systems, addressing various reliability concerns [15][16]. Group 4: Cross-Die Testing Solutions - The SiChip DFT technology offers a mixed testing solution that includes scan chains, boundary scan, built-in self-test (BIST), and diagnostic channels, adhering to various IEEE standards [17][19]. - The architecture design phase must consider DFT testing access mechanisms to ensure compatibility and universality across different manufacturers' dies [19][20]. Group 5: Diagnostic Testing and Functional Simulation - The 3Sheng Ocean EDA testing solution integrates fault diagnosis, functional simulation, and adaptive repair technologies, covering wafer-level circuit testing and final functional testing [25][27]. - The solution aims to optimize testing resources and reduce testing time while enhancing fault coverage, achieving a 50% reduction in testing costs and a 99.99% fault coverage rate [27]. Group 6: Fault Tolerance Design - The SiChip EDA DFT solution supports comprehensive redundancy and fault tolerance, utilizing eFPGA technology to create a full-process redundancy solution from top-level planning to physical implementation [29][31]. - The design allows for dynamic routing and protocol conversion, enhancing interconnect channel utilization and addressing thermal coupling and signal interference issues [31].

Core Viewpoint - The article discusses the advancements and importance of 3D integrated circuits (3D IC) and the role of EDA tools like 3Sheng Stratify™ in ensuring the accuracy and integrity of stacked chip designs, which are crucial for high-performance applications in various industries [3][30]. Group 1: 3D IC and Advanced Packaging - 3D IC technology provides significant flexibility and reusability in product design, particularly for AI computing and high-end mixed-signal integration [3]. - Stacked chips utilize advanced packaging techniques that are essential for performance, functionality, cost, and iteration methods [3]. - The demand for high-density interconnect advanced packaging is growing across various applications, including military, aerospace, and consumer electronics [4]. Group 2: EDA Tools and Verification - 3Sheng Stratify™ EDA tool offers rapid and accurate assembly-level verification for interconnections between dies and intermediary layers in stacked chip designs [10]. - The tool supports design rule checks (DRC) and layout versus schematic (LVS) checks to ensure consistency and compliance with design specifications [10][12]. - The verification process includes checks for signal integrity and functionality across complex interconnect structures [9]. Group 3: Key Performance Indicators - The EDA tool provides various functionalities, including high-density interconnect verification, static timing analysis, and design rule compliance checks [12][13]. - It also features automated detection of anomalies and supports multi-file collaborative checks to enhance design efficiency [13][14]. - The tool aims to improve manufacturability and reliability of 2.5D designs by ensuring that physical layouts meet manufacturing process specifications [23]. Group 4: Design Rule Checks and Automation - The 3Sheng DRC tool supports a wide range of design rule checks, including geometric rules and special process checks, to ensure compliance with foundry specifications [25][28]. - The tool incorporates machine learning algorithms for anomaly detection in 2.5D designs, enhancing the accuracy of network connection checks [18][20]. - Automated repair features are included to address design rule violations, thereby reducing manual intervention and speeding up the design iteration process [28][29]. Group 5: Future Directions - The company aims to enhance the automation design capabilities for 2.5D/3D/3.5D systems, providing comprehensive design and verification solutions to the industry [31]. - The integration of various design engines within the 3Sheng Integration Platform facilitates rapid design and verification processes, ensuring a balance between performance, power consumption, area, and cost [30].

Core Viewpoint - The article discusses the advancements and challenges in the field of Electronic Design Automation (EDA) for 2.5D/3D stacked chip design, emphasizing the need for innovative tools and methodologies to enhance design efficiency and address the complexities of multi-chip integration [2][5][9]. Group 1: EDA Tools and Innovations - EDA suppliers are exploring new methods to improve the efficiency of design and verification engineers, particularly in the context of advanced chips that require early-stage multi-physical field analysis [2]. - The 3Sheng Integration Platform developed by Silicon Chip Technology integrates system-level planning, physical realization, analysis, testability, and reliability design, supporting agile development and customizable collaborative design optimization for 3D heterogeneous integration systems [3][5]. - The introduction of the 3Sheng_Zenith system modeling tool aims to address key challenges in Chiplet and advanced packaging design, facilitating system-level planning, interconnect design, and early system analysis [9][10]. Group 2: System-Level Planning and Design - System-level planning involves partitioning a System on Chip (SoC) into smaller Chiplet modules, allowing for flexible layout planning and resource optimization [13][15]. - Chiplet modeling is a core step in system-level planning, ensuring design repeatability and scalability, with each Chiplet being treated as an independent IP for physical planning [16]. - The floorplan optimization ensures efficient resource allocation among Chiplets in 2.5D/3D integrated circuits, preparing for subsequent routing and simulation [19]. Group 3: Testing and Reliability - The design of multi-chip integrated systems requires careful planning for testability and fault tolerance, as the complexity of interconnects can pose risks to system stability and quality [19]. - The 3Sheng_Zenith tool incorporates early DFT (Design for Testability) and FT (Fault Tolerance) design resources to ensure the stability and integrity of 3D systems [19][21]. Group 4: Early System Analysis - Early system analysis involves multi-level co-design and simulation, utilizing various analysis tools to ensure the reliability and stability of the designed system [30][32]. - The robustness of interconnect routing is assessed to ensure performance, particularly in high-bandwidth, high-power scenarios, by checking parasitic parameters and overall routing constraints [33]. - Manufacturing cost assessments are integral to Chiplet architecture design, considering wafer, packaging, bonding, and testing design costs to ensure the feasibility of the new system [34][36].

Market Overview - The main board saw significant gains with Aerospace Changfeng (+10.02%), Vision China (+10.02%), and Tianjian Technology (+10.01) leading the charge [1] - The ChiNext board experienced a surge with Jinlong Machinery (+20.08%) and AVIC Chengfei (+20.01%) showing strong performance [1] - The Sci-Tech Innovation board also led with Aerospace Nanhu (+20.02%) and Youfang Technology (+13.14%) [1] - Active sub-industries included SW Communication Network Equipment and Devices (+5.77%) and SW Military Electronics III (+3.62%) [1] Domestic News - Semiconductor industry research indicates that Silicon Core Technology has developed a self-research 3Sheng Integration Platform, achieving system-level planning for 3D stacked chips [1] - Semiconductor Investment Alliance reports that Maijie Technology plans to invest 10 million yuan to acquire a 10% stake in Zhongke Hongjing, enhancing its layout in the magnetic materials sector [1] - CINNO confirms that Jiangsu Gaoguang's first 8.6-generation AMOLED metal mask production line has officially entered Jiangsu Zhenjiang, marking a significant step for China's AMOLED industry [1] - CATL has launched the world's first 9MWh energy storage system, improving volume utilization by 45% and energy density by 50%, capable of charging 150 electric vehicles [1] Company Announcements - Weicet Technology announced financial support for its subsidiaries, providing up to 1.3 billion yuan for business expansion focused on high-performance chips and advanced packaging [2] - Dash Smart announced a contract for a smart hospital project with a total value of 58.13 million yuan [2] - Huahong Semiconductor reported a total revenue of 3.913 billion yuan for Q1 2025, a year-on-year increase of 18.66%, but a net profit decline of 89.73% [2] - Shengtian Network has repurchased 2,786,660 shares, accounting for 0.57% of total equity, with a total transaction amount of 29.76 million yuan [2] Semiconductor Industry Insights - AMD anticipates a revenue loss of $1.5 billion due to new U.S. restrictions on chip exports to China [3] - Broadcom has been sending termination letters to VMware license holders, potentially leading to significant legal repercussions [3] - Samsung and SK Hynix are collaborating on hybrid bonding technology for next-generation HBM products, with Samsung expected to apply it to HBM4 next year [3] - Hanwha Semiconductor has established an advanced packaging equipment development center to expand its capabilities into next-generation technologies [3]

来源： 硅芯科技官微 硅芯科技自研3Sheng Integration Platform，实现三维堆叠芯片的系统级规划、物理实现与分 析、可测性与可靠性设计等，集成"系统-测试-综合-仿真-验证"五引擎合一，具有统一数据底 座，支持三维异构集成系统的敏捷开发与可定制化的协同设计优化，并在多个功能和性能上具有 独创性。 直面需求 3月在HiPi联盟大会，已听到 多位业内顶级设计专家发声Chiplet和3D IC对设计和EDA挑战。 近年来国内设计三维异构集成芯片的困扰似乎集中于设计出的堆叠结构，却在仿真和验证以后 仍然发现诸多问题！于是 "缺乏架构设计，急需设计协同和优化，设计要素全线左移" 已经成 为了业界对三维芯片堆叠设计的共识！ 要做一个设计，初心始于SoC的迭代，如果没有架构设计，严格说是能融合支持IP划分、工艺 选择、版图探索、前仿真、互连检查与优化、基于电源和热的物理实现、跨Die物理签核的多 点协同设计的架构设计和早期分析工具，那这样的设计通常会南辕北辙。 在近期硅芯科技的行业分享讲座上，创始人赵毅博士 基于业界3D IC设计遇到的问题 做了又 一轮的总结。其中提到：顶层架构对于应用场景、有效探索 ...

"宁波膜智信息科技有限公司"为势银（TrendBank）唯一工商注册实体及收款账户 势银研究： 势银产业研究服务 势银数据： 势银数据产品服务 势银咨询： 势银咨询顾问服务 重要会议： 4月29日，2025势银异质异构集成封装产业大会（浙江宁波） 点此报名 添加文末微信，加 先进封装 群 珠海硅芯科技有限公司 诚邀您莅临于2025年4月29日在浙江 · 宁波 （ 甬江实验室） 举办的 2025势银异质异构集成封装产业大会 公司介绍 珠海硅芯科技有限公司主要从事新一代2.5D/3D堆叠芯片EDA软件设计的研发及产业化。创始人团队从2008年开始研究2.5D/3D芯片设计方法，是世界最 早期研究设计方法的研究团队之一，并在堆叠芯片EDA后端布局、布线、可测试、可靠性等方面均有世界领先成果。 公司自主研发3Sheng Integration Platform，分为系统级架构设计、物理实现、Multi-die测试容错、分析仿真、多Chiplet集成验证五大中心，涵盖堆叠 芯片设计所需环节的全流程工具。目前，硅芯科技系列产品已通过先进封装产业验证，完成设计制造闭环，并打造首批客户案例，全方位助力 AI,GPU,CPU, ...