1月16日，半导体设备ETF（159516）大涨3%，根据wind数据，半导体设备ETF（159516）盘中流 入6.25亿份，资金抢筹布局。 风险提示：提及个股仅用于行业事件分析，不构成任何个股推荐或投资建议。指数等短期涨跌仅供 参考，不代表其未来表现，亦不构成对基金业绩的承诺或保证。观点可能随市场环境变化而调整，不构 成投资建议或承诺。提及基金风险收益特征各不相同，敬请投资者仔细阅读基金法律文件，充分了解产 品要素、风险等级及收益分配原则，选择与自身风险承受能力匹配的产品，谨慎投资。 每日经济新闻 （责任编辑：董萍萍 ） 【免责声明】本文仅代表作者本人观点，与和讯网无关。和讯网站对文中陈述、观点判断保持中立，不对所包含内容 的准确性、可靠性或完整性提供任何明示或暗示的保证。请读者仅作参考，并请自行承担全部责任。邮箱： news_center@staff.hexun.com 华泰证券指出，AI数据中心建设驱动的超级周期仍然是2026年科技行业最主要的投资主线。存储 在AI算力产业链中的重要性有望显著提升，HBM4e和新型存储系统（如Context Memory Storage System）将驱动存储行业进 ...

1月16日，信创ETF（159537）涨超1%，行业技术演进与需求复苏受关注 华泰证券指出，2026年科技行业最主要的投资主线依然是AI数据中心建设驱动的超级周期，AI算力需 求保持高增长。存储行业正在进入一个由AI驱动的"超级周期"，HBM4e和新型存储系统（如Context Memory Storage System）需求增长显著。同时，2026年可能是"物理AI元年"，人形机器人取代智能电动 车成为最受关注的硬件形态，中国电子供应链在机器人核心零部件上具先发优势。智能硬件方面，微显 示和光波导等核心技术取得显著进展，市场期待Android XR生态产品上市带动新周期；云台相机已进入 普及期，成为新增量赛道。 （文章来源：每日经济新闻） 信创ETF（159537）跟踪的是国证信创指数（CN5075），该指数从市场中选取业务涉及软件开发、计 算机设备等信息技术领域的上市公司证券作为指数样本，以反映信息技术创新相关上市公司证券的整体 表现。 ...

（文章来源：每日经济新闻） 消电ETF（561310）跟踪的是消费电子指数（931494），该指数从市场中选取从事消费电子产品设计、 制造与销售的相关上市公司证券作为指数样本，覆盖智能手机、家用电器、可穿戴设备等领域，以反映 消费电子行业具有技术驱动和消费升级特征的整体表现。 1月16日，消电ETF（561310）涨超2.2%，行业景气获市场关注。 华泰证券指出，AI数据中心建设驱动的超级周期仍然是2026年科技行业最主要的投资主线，计算芯 片、存储、网络设备、电力需求旺盛。存储行业正进入一个由AI驱动的"超级周期"，HBM4e和新型存 储系统需求增长显著。同时，2026年可能是"物理AI元年"，人形机器人取代智能电动车成为最受关注的 硬件形态，中国电子供应链在机器人核心零部件上具先发优势。半导体设备环节因先进制程与封装需求 持续扮演重要角色。 ...

风险提示：提及个股仅用于行业事件分析，不构成任何个股推荐或投资建议。指数等短期涨跌仅供 参考，不代表其未来表现，亦不构成对基金业绩的承诺或保证。观点可能随市场环境变化而调整，不构 成投资建议或承诺。提及基金风险收益特征各不相同，敬请投资者仔细阅读基金法律文件，充分了解产 品要素、风险等级及收益分配原则，选择与自身风险承受能力匹配的产品，谨慎投资。 每日经济新闻 （责任编辑：董萍萍 ） 【免责声明】本文仅代表作者本人观点，与和讯网无关。和讯网站对文中陈述、观点判断保持中立，不对所包含内容 的准确性、可靠性或完整性提供任何明示或暗示的保证。请读者仅作参考，并请自行承担全部责任。邮箱： news_center@staff.hexun.com 1月16日，科创芯片ETF国泰（589100）涨超1.7%，行业需求复苏获关注。 华泰证券指出，2026年科技行业最主要的投资主线依然是AI数据中心建设驱动的超级周期，计算 芯片、存储、网络设备、电力需求旺盛。存储行业正进入一个由AI驱动的"超级周期"，HBM4e需求强 劲且制造难度上升，同时新型存储系统（如Context Memory Storage System）旨在解决大 ...

Core Viewpoint - Intel has made significant advancements in chip packaging technology under the leadership of new CEO Chen Liwu, particularly with the introduction of the EMIB-T technology, which enhances chip packaging size and power delivery capabilities to support new technologies like HBM4/4e [1][9]. Group 1: EMIB-T Technology Advancements - EMIB-T integrates TSV (Through-Silicon Via) for vertical signal transmission between chips, reducing power transmission resistance by over 30%, which minimizes voltage drop and signal noise [2][6]. - The technology incorporates high-density MIM (Metal-Insulator-Metal) capacitors to suppress power noise, ensuring signal integrity, especially in high-performance applications like AI accelerators and data center processors [2][7]. - EMIB-T supports a maximum package size of 120x180 mm, allowing integration of over 38 bridges and 12 dies, with plans to reduce bump pitch from 45 microns to as low as 25 microns in the future [2][7]. Group 2: Strategic Importance and Market Position - Intel's foundry aims to leverage cutting-edge process node technologies to manufacture chips for both internal and external clients, enhancing performance, cost, and energy efficiency through complex heterogeneous designs [4][5]. - The EMIB-T technology is crucial for supporting HBM4 memory and UCIe interconnect requirements, making it an ideal packaging solution for AI accelerators, data center processors, and supercomputing chips [7][8]. - Intel plans to achieve mass production of EMIB-T packaging by the second half of 2025, with a vision to integrate over 24 HBM chips in a single package by 2028, significantly impacting global semiconductor packaging technology [9].

Core Viewpoint - SK Hynix emphasizes that the commercialization of the next generation of HBM (High Bandwidth Memory) requires technological advancements across various fields, particularly in power efficiency, and closer collaboration with major foundries is expected [1][3]. Group 1: Development Focus of HBM - SK Hynix's next generation HBM development focuses on three main tasks: bandwidth, power, and capacity [3]. - The bandwidth is a critical measure of data transfer speed, with the number of I/O ports for HBM4 expected to double compared to HBM3E, reaching 2,048 [3]. - Future HBM is anticipated to improve in power consumption and capacity, with the number of DRAM stacks expected to increase from a maximum of 12 to 16 or even 20 layers [3][4]. Group 2: Challenges in HBM Production - To stack more layers of the next generation HBM within a limited height specification of 775 micrometers, the spacing between each DRAM must be reduced [4]. - SK Hynix is advancing hybrid bonding technology, which connects DRAMs directly without bumps, thus reducing chip thickness and improving power efficiency [4][5]. - However, hybrid bonding faces challenges in commercialization due to high technical difficulty and issues with mass production and reliability [5]. Group 3: Competitive Landscape - Samsung has successfully produced 16-layer stacked HBM3 memory using hybrid bonding technology and plans to mass-produce HBM4 using this technology [6][8]. - Micron Technology is on track with its HBM4 development, expecting to start mass production in 2026, with HBM4E following shortly after [12]. - Micron's HBM4 will utilize 1β (5th generation 10nm class) DRAM technology, integrating up to 16 DRAM chips per stack, each providing 32 GB capacity, with a peak bandwidth of 1.64 TB/s [12][13]. Group 4: Future Projections - The HBM4 and HBM4E are seen as crucial for the ongoing expansion of AI performance, with expectations for significant improvements in density and bandwidth [22]. - Nvidia's upcoming AI accelerators are projected to utilize HBM4 technology, with the Rubin Ultra expected to feature up to 1TB of memory capacity [20][22]. - The competitive landscape is intensifying, with both Samsung and SK Hynix planning to adopt advanced foundry processes for HBM4 production, aiming for enhanced performance and efficiency [16][17].