Core Viewpoint - TSMC is developing the second generation of its System on Wafer (SoW) technology, which integrates various components onto a large 300mm silicon wafer, enhancing performance and efficiency in semiconductor packaging [1][2]. Group 1: SoW Technology Overview - The SoW technology integrates chiplets, stacked chip modules, memory modules, power modules, I/O boards, and heat dissipation boards on both sides of a 300mm wafer [1]. - The first generation of SoW, named SoW-P, focuses on integrating System on Chip (SoC) as the main circuit, while the second generation, SoW-X, will combine SoC with High Bandwidth Memory (HBM) for heterogeneous integration [2]. Group 2: CoWoS Technology - The second generation of SoW is an upgrade of the CoWoS (Chip on Wafer on Substrate) technology, which uses an intermediate substrate to enhance data transmission speed and density [7]. - CoWoS technology has evolved since its introduction in 2012, with significant advancements in the size and efficiency of silicon interposers, particularly after 2016 [8][9]. Group 3: Future Developments and Roadmap - TSMC's roadmap includes expanding the size of the intermediate substrate in CoWoS technology, with plans for a substrate size 5.5 times larger than the photomask by 2025-2026 and 8 times larger by 2026-2027 [13]. - The SoW-X technology is expected to be implemented by 2027, with anticipated challenges related to high manufacturing costs and customer acceptance [24]. Group 4: Performance Metrics - The SoW-X module, arranged in a 4x4 matrix, is designed to achieve a performance per watt that is 65% higher than a PCIe cluster system, although it is 27% lower than a single CoWoS-L module [20]. - The total power consumption for SoW-X is projected to reach 17kW, with water cooling solutions being considered for heat dissipation [22].

Core Viewpoint - The cooling technology will become a key competitive factor in the high bandwidth memory (HBM) market as HBM5 is expected to commercialize around 2029, shifting the focus from packaging to cooling solutions [1][2]. Summary by Sections HBM Technology Roadmap - The roadmap from HBM4 to HBM8 spans from 2025 to 2040, detailing advancements in HBM architecture, cooling methods, TSV density, and interposer layers [1]. - HBM4 is projected to be available in 2026, with a data rate of 8 Gbps, bandwidth of 2.0 TB/s, and a capacity of 36/48 GB per HBM [3]. - HBM5, expected in 2029, will double the bandwidth to 4 TB/s and increase capacity to 80 GB [3]. - HBM6, HBM7, and HBM8 will further enhance data rates and capacities, reaching up to 32 Gbps and 240 GB respectively by 2038 [3]. Cooling Technologies - HBM5 will utilize immersion cooling, where the substrate and package are submerged in cooling liquid, addressing limitations of current liquid cooling methods [2]. - HBM7 will require embedded cooling systems to inject coolant between DRAM chips, introducing fluid TSVs for enhanced thermal management [2]. - The introduction of new types of TSVs, such as thermal TSVs and power TSVs, will support the cooling needs of future HBM generations [2]. Performance Factors - Bonding techniques will also play a crucial role in HBM performance, with HBM6 introducing a hybrid interposer of glass and silicon [2]. - The integration of advanced packaging technologies will allow base chips to take on GPU workloads, necessitating improved cooling solutions due to increased temperatures [2].

Core Viewpoint - The article discusses the significant rise of TSMC's CoWoS packaging technology, driven by the increasing demand for GPUs in the AI sector, particularly through its partnership with NVIDIA, which has deepened over time [1][3]. Group 1: CoWoS Technology and NVIDIA Partnership - NVIDIA has emphasized its reliance on TSMC for CoWoS technology, stating that it has no alternative partners in this area [1]. - TSMC has reportedly surpassed ASE Group to become the largest player in the global packaging market, benefiting from the growing demand for advanced packaging solutions [1]. - NVIDIA's upcoming Blackwell series will utilize more CoWoS-L packaging, indicating a shift in production focus from CoWoS-S to CoWoS-L to meet the high bandwidth requirements of its GPUs [3]. Group 2: Challenges and Innovations in CoWoS - The increasing size of AI chips poses challenges for CoWoS packaging, as larger chips reduce the number of chips that can fit on a 12-inch wafer [4]. - TSMC is facing difficulties with the use of flux in CoWoS, which is essential for chip bonding but becomes problematic as the size of the interposer increases [4][5]. - TSMC is exploring flux-free bonding technologies to improve yield rates and address the challenges posed by flux residue [5]. Group 3: Future Developments and Alternatives - TSMC plans to introduce CoWoS-L with a mask size of 5.5 times larger by 2026 and aims for a record 9.5 times larger version by 2027 [8]. - The company is also developing CoPoS technology, which replaces traditional wafers with panel substrates, allowing for higher chip density and efficiency [9][10]. - CoPoS is positioned as a potential alternative to CoWoS-L, targeting high-performance applications in AI and HPC systems [12]. Group 4: Technical Comparisons - FOPLP and CoPoS both utilize large panel substrates but differ in architecture; FOPLP does not use an interposer, while CoPoS does, enhancing signal integrity for high-performance chips [11]. - CoPoS is transitioning to glass substrates, which offer better performance characteristics compared to traditional organic substrates [12]. - The shift from round wafers to square panels in CoPoS aims to improve yield and reduce costs, making it more competitive in the AI and 5G markets [12]. Group 5: Challenges Ahead - Transitioning to square panel technology requires significant investment in materials and equipment, along with overcoming technical challenges related to pattern precision [14]. - The demand for finer RDL line widths poses additional challenges for suppliers, necessitating breakthroughs in RDL layout technology [14]. Conclusion - The future of TSMC's packaging technologies appears promising, with ongoing innovations and adaptations to meet the evolving demands of the semiconductor industry [14].