Core Viewpoint - The research team led by Professor Peng Hailin from Peking University has developed the world's first low-power, high-performance two-dimensional gate-all-around (GAA) transistor, which surpasses the physical limits of silicon-based transistors in both speed and energy efficiency, potentially driving a new wave of technological innovation in the chip industry [1][9][19]. Group 1: Technology Development - The two-dimensional gate-all-around transistor represents a significant advancement in integrated circuit technology, addressing the limitations of traditional silicon-based transistors by enhancing electrostatic control over the channel, thereby reducing leakage current and power consumption [4][6]. - The new transistor utilizes a novel high-mobility bismuth-based two-dimensional semiconductor material (Bi2O2Se) and a high dielectric constant oxide gate dielectric (Bi2SeO5), achieving superior performance compared to existing silicon-based transistors [9][12]. - The team has successfully created a small logic unit using the two-dimensional gate-all-around transistor and is working towards scaling up for mass production, with applications in high-performance sensors and flexible electronic devices [12][19]. Group 2: Research and Innovation - The development of the two-dimensional gate-all-around transistor is seen as a "cross-generation upgrade," moving beyond the limitations of silicon materials, which are nearing their physical limits [9][16]. - The research team emphasizes the importance of meticulous experimental detail and the ability to recognize and analyze unusual results, which can lead to significant breakthroughs in material science [17][24]. - The team has a strong interdisciplinary background, fostering a culture of innovative thinking and collaboration, which is crucial for advancing semiconductor technology [18][24]. Group 3: Future Prospects - The new transistor technology is projected to achieve speeds approximately 1.4 times that of the most advanced silicon chips while consuming only 90% of their energy, indicating a substantial competitive advantage as manufacturing processes improve [19][21]. - The research team is committed to further exploring the potential of bismuth-based two-dimensional materials, aiming for integrated functionalities in sensing, storage, and computation, which could lead to significant technological advancements [12][16]. - The ongoing research and development efforts are aligned with China's goals for technological self-reliance and innovation in the semiconductor industry, with a focus on practical applications and industrialization of new materials [22][24].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容来自technews，谢谢。 报导提到Rapidus 最大不安因素，是目前没有足够客户需求。一旦开始生产，出货量将达到数亿 颗，但目前没有足够的客户需求作为支撑。目前先进半导体主要应用于智能手机或盛怒据中心服务 器处理器，但Rapidus 并未掌握这类客户。井上弘基质疑，「Rapidus 大量生产的芯片，究竟有谁 会购买？购买量又会有多少？」 台积电和三星电子开发先进半导体时，会事先与苹果、高通、英伟达等大型客户建立合作关系，确 保订单，并与客户步调一致地推进技术开发。这与Rapidus 的做法完全不同。客观来说，即使 Rapidus 成功建造最先进的产能基地，如果缺少买家，导致产能闲置，恐进而造成财务危机。 除了井上弘基负面看待日本对Rapidus 经营模式，过去日本政府和经济评论员古贺茂明也提到认为 目前Rapidus 失败的机率不断升高。 Rapidus 所需资金预估为5 万亿日圆，但来自民间投资的出资额为73 亿日圆，之后就再也没增 加，意味民间部门没人愿意接手这个专案。古贺茂明指出，虽然Rapidus 北海道千岁市工厂的开工 仪式，有许多企业高层助 ...

Core Insights - The article discusses the history and key moments of TSMC, particularly focusing on its relationship with Nvidia and the evolution of the semiconductor industry under the leadership of Morris Chang [2][3][4]. Group 1: TSMC's Relationship with Nvidia - TSMC's relationship with Nvidia began in 1997 when Nvidia's CEO, Jensen Huang, reached out for manufacturing support, highlighting the importance of potential clients regardless of their size [3][4]. - At the time, Nvidia was a small company facing bankruptcy, while TSMC had already surpassed $1 billion in revenue [4][5]. - The partnership proved successful, with Nvidia becoming one of TSMC's major clients within a few years, significantly contributing to TSMC's growth [7][9]. Group 2: Challenges and Resolutions - In 2009, TSMC faced manufacturing and quality issues at the 40nm process node, which affected clients like Nvidia, leading to financial and operational challenges [10][12]. - Morris Chang returned as CEO to address these issues, emphasizing the importance of maintaining strong relationships with clients and resolving disputes amicably [12][25]. - A significant resolution occurred when TSMC proposed a settlement of over $100 million to Nvidia, which was accepted, reinforcing their long-term partnership [30][32]. Group 3: Strategic Decisions and Market Positioning - TSMC decided to invest heavily in the 28nm process node, which was seen as a pivotal moment for the company, coinciding with the rise of the smartphone market [34][42]. - The company set a research and development budget at 8% of revenue to ensure consistent innovation and competitiveness in the semiconductor industry [35][36]. - TSMC's strategic focus on advanced technology and market needs allowed it to maintain a leading position in the semiconductor manufacturing sector [42][43]. Group 4: Engagement with Apple - TSMC's relationship with Apple began when Apple sought TSMC's manufacturing capabilities, leading to discussions about economic terms and production timelines [60][62]. - The initial engagement with Apple highlighted TSMC's competitive edge in technology and manufacturing efficiency, which was crucial for securing Apple's business [63][66]. - TSMC faced challenges in meeting Apple's demands for new process nodes, but the company strategically managed its resources to accommodate these requests while maintaining its operational integrity [67][73].

Core Viewpoint - The article discusses the end of Moore's Law and the rise of artificial intelligence (AI), highlighting the shift from traditional computing to AI-driven systems that can self-improve and process vast amounts of data more efficiently [1][3][6]. Group 1: The End of Moore's Law - Moore's Law, which predicted that the number of transistors on a chip would double every two years, is losing its effectiveness as transistors reach atomic limits, making further miniaturization costly and complex [1][3]. - Traditional computing faces challenges such as heat accumulation, power limitations, and rising chip production costs, which hinder further advancements [3][4]. Group 2: Rise of AI and Self-Learning Systems - AI is not constrained by the need for smaller transistors; instead, it utilizes parallel processing, machine learning, and specialized hardware to enhance performance [3][4]. - The demand for AI computing power is increasing rapidly, with AI capabilities growing fivefold annually, significantly outpacing Moore's Law's predicted doubling every two years [3][6]. - Companies like Tesla, Nvidia, Google DeepMind, and OpenAI are leading the transition with powerful GPUs, custom AI chips, and large-scale neural networks [2][4]. Group 3: Approaching the AI Singularity - The concept of the AI singularity refers to a point where AI surpasses human intelligence and begins self-improvement without human input, potentially occurring as early as 2027 [2][6]. - Experts have differing opinions on when Artificial General Intelligence (AGI) and subsequently Artificial Superintelligence (ASI) will be achieved, with predictions ranging from 2027 to 2029 [6][7]. Group 4: Implications of ASI - ASI has the potential to revolutionize various industries, particularly in healthcare, economics, and environmental sustainability, by accelerating drug discovery, automating repetitive tasks, and optimizing resource management [8][9][10]. - However, the rapid advancement of ASI also poses significant risks, including the potential for AI to make decisions that conflict with human values, leading to unpredictable or dangerous outcomes [10][12]. Group 5: Safety Measures and Ethical Considerations - Organizations like OpenAI and DeepMind are actively researching AI safety measures to ensure alignment with human values, including reinforcement learning from human feedback [12][13]. - The need for ethical guidelines and regulatory frameworks is critical to guide AI development responsibly and ensure it benefits humanity rather than becoming a threat [13][14].

图 6A 和图 6B ：传统模式（应用程序和数据分散在多个微型 GPU 上）与局部模式（应用程序部分限制在各 自微型 GPU 及其本地内存中）的比较 NVIDIA 的专利设想了实现这种本地化的三个主要组件： 如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容编译自wccftech，谢谢。 NVIDIA 仍然稳坐GPU 计算领域的前沿，因此在整个 AI 领域享有无与伦比的主导地位。然而， 科技行业的领导地位需要近乎不断的创新。而 NVIDIA 似乎正在提供大量的创新，至少目前是这 样。 NVIDIA于2025年3月6日申请了一项新专利，专利号为US20250078199A1。专利中提出的"局部 模式统一内存GPU"解决了现代GPU计算中的一个重大挑战：如何在不牺牲速度的情况下构建越来 越强大的GPU。随着当今GPU的规模越来越大，通常跨越多个物理芯片，从远端内存访问数据变 得明显更慢——就像从城另一头的图书馆拿书与从你的书桌上拿书一样。 该专利设想 GPU 的离散部分在本地范围内工作以存储和访问数据并执行计算，从而减少访问远程 计算资源所固有的延迟。毋庸置疑，这项专利的物理表现将大大加快基于 GPU 的计算速 ...

Core Viewpoint - EUV technology is overcoming challenges such as high costs and complex optical systems, showing significant advantages in processes of 10nm and below, with recent advancements from major companies indicating a new phase of commercial application and development [1]. Group 1: High NA EUV Developments - Intel is the first chip manufacturer to purchase High NA EUV lithography machines, with each machine valued at €350 million, currently used for R&D purposes [3]. - Intel's early results show that High NA machines can complete tasks with fewer exposures and processing steps compared to earlier machines, indicating a strong commitment to leading in the High NA EUV era [3][4]. - imec demonstrated a 90% yield in electrical testing of 20nm spaced metal lines using High NA EUV lithography, confirming the technology's capability at such small dimensions [6][10]. Group 2: Competitive Landscape in DRAM - Micron has introduced its first EUV-based 1γ (1-gamma) 16Gb DDR5 devices, achieving a 20% reduction in power consumption and a 30% increase in bit density compared to previous generations [11][15]. - Micron's transition to EUV is expected to improve economic efficiency for new nodes, combining EUV with multiple patterning DUV technology [15][16]. - The competition among major memory manufacturers is intensifying as Micron adopts EUV, with Samsung and SK Hynix also investing in High NA EUV machines to enhance their competitive edge [17]. Group 3: EUV Mask Technology - Samsung has decided to procure EUV pellicles from Mitsui Chemicals to improve production efficiency, following challenges in yield for its 3nm process [22][23]. - The development of EUV pellicles is crucial for reducing pattern defects in chip manufacturing, with ongoing efforts to enhance the performance and lifespan of these films [21][25]. Group 4: Future of EUV Technology - The ongoing innovation in EUV technology is expected to lead to more efficient, precise, and cost-effective chip manufacturing processes, supporting the semiconductor industry's growth and competitiveness [29].

Core Viewpoint - The article discusses the surprising connection between supernovae and the technology used in manufacturing semiconductor chips, particularly focusing on the development of extreme ultraviolet (EUV) lithography technology essential for modern microchip production [1][2][3]. Group 1: EUV Technology Development - ASML, a Dutch company, specializes in developing equipment for semiconductor chip manufacturing, particularly focusing on EUV lithography technology, which was still in development about a decade ago [2][4]. - The process of generating EUV light involves focusing powerful laser pulses on tin droplets, creating a plasma that emits intense ultraviolet light, crucial for producing advanced microchips [2][6]. - The challenge of producing a reliable EUV light source was significant, as the available sources were only about one-tenth as powerful as needed, leading to doubts about the commercial viability of EUV technology [7][9]. Group 2: Connection to Supernovae - The physical processes involved in generating EUV light from tin plasma exhibit interesting similarities to supernova explosions, such as the sudden explosion and the expansion of plasma clouds [3][11]. - The Taylor-von Neumann-Sedov formula, originally developed for calculating the yield of atomic bombs, also describes the evolution of shock waves in both supernovae and the tin plasma used in EUV systems [13][14]. - Observations of the plasma's behavior and the resulting shock waves have provided insights that have helped improve the reliability and efficiency of EUV light sources for chip manufacturing [12][14]. Group 3: Industry Implications - The advancements in EUV technology are critical for the semiconductor industry, as they enable the production of smaller and faster circuits, continuing the trend of Moore's Law, which predicts the doubling of transistor counts approximately every two years [6][8]. - The successful development of EUV lithography is essential for the future of the electronic industry, which is valued at nearly a trillion dollars, as it allows for the creation of more complex and powerful microchips [6][7].

Summary of Conference Call Records Industry Overview - The discussion primarily revolves around the semiconductor testing equipment industry, focusing on various types of testing machines used for different chip categories, including general-purpose and specialized testing machines [1][2][3]. Key Points and Arguments Types of Testing Machines - Testing machines can be categorized based on their application and chip type, primarily into two main categories: general-purpose testing machines and specialized testing machines [1][2]. - General-purpose testing machines are exemplified by leading companies such as Tereda and Edward, while specialized testing machines offer low-cost solutions tailored for specific chip types like microcontrollers (MCUs) [2][3]. System-Level Testing (SLT) - SLT is emphasized as a critical testing method, particularly for mobile devices, where the application processor (AP) is tested for its performance before delivery [3][5]. - The SLT market faces challenges in China due to low entry barriers, leading to high competition and the need for customized solutions based on specific product applications [5]. Chip Packaging and Complexity - The complexity of chip packaging has increased, with System In Package (SiP) technology becoming prevalent, which integrates multiple chips into a single package [4][5]. - The demand for testing machines is driven by the need to ensure high-quality delivery and performance of these complex packages [5]. AI Chip Testing Requirements - The rise of AI chips has significantly influenced the testing machine market, with a notable increase in the demand for testing capabilities that can handle the unique requirements of AI chips [9][12]. - Approximately 60% of the testing for AI chips involves Design for Test (DFT) methodologies, which are crucial for ensuring the chips meet performance standards [12]. Challenges in Domestic Testing Equipment - Domestic testing machine manufacturers in China face limitations in acquiring advanced chips due to geopolitical factors, restricting their ability to produce high-end AI chips [18][19]. - The testing capabilities of Chinese manufacturers are often limited to lower-performance chips, which affects their competitiveness in the global market [18][19]. Storage Testing Machines - The discussion also covers storage testing machines, highlighting their differences from SoC testing machines. Storage testing requires more complex testing protocols and longer testing times [30][32]. - HBM (High Bandwidth Memory) testing presents unique challenges due to its complex packaging and high-speed requirements, necessitating advanced testing solutions [37][39]. Market Outlook and Capital Expenditure (CAPEX) - The overall market for semiconductor testing equipment is expected to face pressures in 2023, with a potential recovery in CAPEX anticipated in 2024 and 2025, driven by AI and other technological advancements [42][43]. - The importance of being on the "white list" for semiconductor testing and packaging is emphasized, as it affects the ability of Chinese companies to participate in advanced technology markets [43][44]. Conclusion - The conference call highlights the evolving landscape of the semiconductor testing equipment industry, with a focus on the increasing complexity of chips, the rise of AI technology, and the challenges faced by domestic manufacturers in China. The need for advanced testing solutions and the impact of geopolitical factors on the industry are critical themes throughout the discussion [1][18][43].

以下文章来源于南风窗 ，作者荣智慧 南风窗 . 冷静地思考，热情地生活。 芯片必须越来越小。 作者 | 荣智慧 来源 | 南风窗 （ID：SouthReviews） 半导体领域的事儿，越来越"矛盾"。 晶体管的通道、软硬件之间的"次元壁"越来越小。而国家之间的"墙"越来越大。 在越来越小的领域，英伟达、AMD和台积电赚得盆满钵满。在越来越大的领域，金钱像 筹码一样押在跷跷板的两头——一头是美国，身后坐着拉美"后院"伙伴，非洲国家跟随 其后；一头是中国，东南亚和南亚正等着溢出的供应链；中国台湾、日本和韩国首鼠两 端。 更顽固的是消费者，今年大伙儿牢牢捂紧钱包，什么也不想买。随着当选总统特朗普第 二任期的逼近，更多的出口禁令、更高的关税、供应过剩和更富创造性的制裁规避方法 将在2025年出现。 越来越小 按价值计算，半导体现在是世界上交易量第三大的商品，仅次于石油和汽车。 处理能力每两年翻一番的摩尔定律，成功运行了半个多世纪。2 0 1 7年，英伟达创始人黄 仁勋宣布摩尔定律已死。2 024年，摩尔创立的英特尔的首席执行官帕特·基辛格坚称摩尔 定律还活着，年底，基辛格被大失所望的股东"炒了鱿鱼"。 在2024年， ...

随着台积电拿走芯片制造更多利润，产业风险也在进一步聚集。 文丨 邱豪 贺乾明 编辑丨龚方毅 1990 年代，硅谷诞生数十家只设计、不制造的芯片公司（Fabless）。AMD 创始人杰瑞·桑德斯（Jerry Sanders）在一场行业会议上说："现在听我说，真正的 男人要有晶圆厂"。他认为，只做设计的芯片公司，只能在晶圆厂有空余产能时才能下单，还得把设计图纸无保留地交给竞争对手，容易让公司陷入困境。 十多年后，芯片行业沿着桑德斯预想的糟糕情况发展。按照他的标准，当前最强的一批芯片公司——苹果、英伟达、博通、高通等，都不是 "真男人"。AMD 也变成一家纯设计芯片的公司，经历多年阵痛后，在女性 CEO 苏姿丰带领下走出困境。 晶圆厂依旧重要，只是没几家能建得起最先进的。台积电保持绝对优势，生产全球 60% 的逻辑芯片、90% 的 5 纳米以内先进芯片。先进芯片制造领域，台积 电仅剩的两个对手各有各的困境： 与此同时，台积电董事长魏哲家在二季度财报电话会上提出 "Foundry 2.0" 的概念，称台积电的业务范围覆盖先进芯片的制造、封装、测试等流程。芯片设计 公司只要给台积电递交设计文件（GDS），几个月后就能收 ...