广发证券发布研报称，在高并发、长上下文的密集型推理中，MRDIMM与CXL形成"近端高带宽+远端 大容量"的分层协同，以更低TCO增加AI服务器内存供给与弹性扩展。CXL3.1对KVCache的性能提升尤 为明显，特别适用于高并发、超长上下文的负载。建议关注产业链核心受益标的。 CXL提供远端/池化拓展，在KVCache密集型推理中形成显著TCO优势 CXL3.1对KVCache的性能提升尤为明显，特别适用于高并发、超长上下文的负载。具体体现为：(1)内 存池化与扩展：在CPU/GPU/加速器间做内存池化，将部分KVCache从昂贵的GPU显存弹性卸载到CXL 设备，在不增加GPU成本前提下扩大有效容量至TB级;(2)低时延访问：CXL访问时延可逼近 CPUDRAM，使置于CXL的KVCache在高负载下亦能维持接近实时的解码性能;(3)解耦式KVCache架 构：在字节跳动LLM服务栈中，将KVCache卸载至CXL可使batch size提高30%、GPU需求降低87%、 prefill阶段GPU利用率提升7.5倍;(4)分层内存管理：CXL支持冷热分层，允许根据访问频率对KVCache 进行动态放置。热 ...

Group 1: Company Overview - Wuxi Dike Electronic Materials Co., Ltd. focuses on storage chip packaging and testing services, with major clients including subsidiaries of Yimeng Holdings and Chengdu Electric Science and Technology [2] - The packaging capacity of Jiangsu Jinkai is approximately 3KK/month, with testing capacity at about 2.5KK/month, planning to expand to 4KK/month [2] Group 2: Competitive Advantages - Post-acquisition, the company will be one of the few in the industry with an integrated layout covering DRAM chip application development, wafer testing, and storage packaging, providing a significant competitive edge [2] - Jiangsu Jinkai's gross margin for DRAM chip packaging is between 20%-30%, while the testing business has a gross margin of around 50%, slightly higher than industry peers [3] Group 3: Future Revenue Projections - The storage business is expected to maintain good growth due to a favorable market outlook and rising prices, with Yimeng Holdings leveraging integrated cost and quality advantages to expand into the consumer electronics market [3] - The company aims to enhance collaboration with mainstream SOC chip design firms to mutually empower and expand market presence, while also accelerating the production of AI-related products [3]

Core Insights - Astera Labs is leading the development of semiconductor-based connectivity solutions for rack-scale AI infrastructure, emphasizing the shift towards unified computing platforms rather than individual servers [1][2] - The company is showcasing its ecosystem collaborations at the 2025 OCP Global Summit, highlighting the importance of open standards for AI Infrastructure 2.0 [1][2] Industry Trends - The AI infrastructure landscape is transitioning from server-level architectures to rack-scale systems, driven by significant investments from hyperscalers [2] - Open standards are essential for integrating diverse accelerators, interconnects, and management tools, enabling optimized solutions for specialized AI workloads [2] Ecosystem Collaborations - Astera Labs is collaborating with various industry leaders, including AMD, Arm, and Molex, to enhance AI infrastructure through high-performance connectivity solutions [3][4][9] - These partnerships focus on delivering reliable, high-speed cable solutions and ensuring robust signal integrity across rack-scale distances [3][9] Technical Innovations - The company is presenting technical sessions on UALink deployment strategies and PCIe 6 security considerations at the OCP Global Summit [2] - Astera Labs' Intelligent Connectivity Platform integrates multiple semiconductor-based technologies, including CXL, Ethernet, PCIe, and UALink, to create cohesive systems [13] Market Position - Astera Labs positions itself as a key player in the AI infrastructure market by providing purpose-built connectivity solutions grounded in open standards [13] - The company's collaborations aim to accelerate the adoption of open rack architectures, enhancing performance, interoperability, and scalability for customers [10][12]

Investment Rating - The report maintains an "Outperform" rating for the communication industry, indicating an expected performance exceeding the benchmark index by more than 10% [36]. Core Insights - Huawei's new Ascend roadmap was unveiled at the 2025 Connectivity Conference, showcasing significant advancements in supernode capabilities, with the upcoming 950PR architecture expected to achieve 1P FP8/2P FP4 computing power and 2TB/s interconnect bandwidth [2][11]. - The collaboration between NVIDIA and Intel aims to create a new order in data centers, with NVIDIA acquiring a 4% stake in Intel and both companies working on customized data center and PC products [4][14]. - The report highlights the potential acceleration of domestic AI chip shipments in 2026, driven by Huawei's leadership in the domestic computing sector [11][12]. Summary by Sections Industry Trends - Huawei's Ascend AI chip roadmap indicates a significant leap in domestic computing capabilities, with the 950 series expected to surpass NVIDIA's previous flagship in interconnect bandwidth [2][11]. - The Atlas 950 SuperPoD supernode utilizes a hybrid copper-optical architecture, enhancing cost-effectiveness and potentially setting a benchmark for domestic computing cluster design [3][12]. Market Overview - The overall market saw an increase during the week of September 22-26, 2025, with the STAR Market index rising by 6.47% and the ChiNext index by 1.96% [6][15]. - The top-performing sectors included liquid cooling (+7.16%), IoT (+5.95%), and IDC (+1.54%) [15]. Stock Performance - Leading stocks included Cambridge Technology (+18.77%), Inspur Information (+11.86%), and Zhongtian Technology (+9.08%) [15][29]. - Stocks with the largest declines were Bochuang Technology (-14.77%), Changfei Fiber (-14.61%), and Yihua Technology (-8.95%) [15][29]. Companies to Watch - Key companies to monitor include Cambricon, Haiguang Information, and ZTE Corporation in the domestic computing sector, as well as Inspur Information and Ziguang Corporation in the supernode market [15].

Core Viewpoint - The release of the PCIe 8.0 standard marks a significant milestone in the evolution of PCIe technology, doubling the data transfer rate to 256GT/s and reinforcing its critical role in high-speed data transfer across various computing environments [1][38]. Group 1: Evolution of PCIe Technology - PCIe, introduced by Intel in 2001, has evolved from the original PCI standard, which had a maximum bandwidth of 133 MB/s, to a series of iterations that have consistently doubled the data transfer rates [3][14]. - The transition from PCI to PCIe represents a shift from parallel bus technology to a serial communication mechanism, significantly enhancing data transfer efficiency and reducing signal interference [9][11]. - The PCIe 1.0 standard initiated the serial interconnect revolution with a transfer rate of 2.5GT/s, while subsequent versions have seen substantial increases, culminating in the upcoming PCIe 8.0 [14][38]. Group 2: Key Features of PCIe - PCIe's architecture includes three core features: serial communication, point-to-point connections, and scalable bandwidth capabilities, which collectively enhance performance and reduce latency [9][11]. - The introduction of advanced signal processing techniques, such as CTLE in PCIe 3.0 and PAM4 modulation in PCIe 6.0, has been pivotal in maintaining signal integrity and supporting higher data rates [18][24]. - PCIe 8.0 is set to introduce new connector technologies and optimize latency and error correction mechanisms, ensuring reliability and efficiency in high-bandwidth applications [42][38]. Group 3: Market Applications and Trends - PCIe technology is predominantly utilized in cloud computing, accounting for over 50% of its market share, with increasing adoption in automotive and consumer electronics sectors [46][49]. - The demand for high-speed interconnects is driven by the growth of AI applications, high-performance computing, and data-intensive workloads, positioning PCIe as a foundational technology in these areas [45][51]. - Predictions indicate that the PCIe market in AI applications could reach $2.784 billion by 2030, with a compound annual growth rate of 22% [51]. Group 4: Competitive Landscape and Challenges - PCIe faces competition from proprietary interconnect technologies like NVLink and CXL, which offer higher bandwidth and lower latency for GPU communications [55][63]. - The establishment of the UALink alliance aims to create open standards for GPU networking, challenging the dominance of proprietary solutions and enhancing interoperability [56]. - Despite its established position, PCIe must navigate challenges related to bandwidth limitations and evolving market demands, necessitating continuous innovation and adaptation [64][71].

Company Overview - Astera Labs is a network infrastructure company focused on selling Ethernet, CXL, and PCIe-based products aimed at enhancing connectivity between various chips in data centers designed for AI and cloud computing [1]. Industry Context - The products developed by Astera Labs are critical for improving data center operations, particularly in the growing fields of artificial intelligence and cloud computing, which are increasingly reliant on efficient chip connectivity [1].

Summary of Key Points from the Conference Call Industry Overview - **Industry**: Semiconductor Storage Industry, specifically focusing on DRAM, NAND Flash, and related technologies [1][3][5][21] Core Insights and Arguments - **DRAM Market Trends**: The DRAM market is expected to see price increases in Q2 and Q3 of 2025 due to supply constraints from manufacturers ceasing production of DDR3 and DDR4, alongside significant demand for server DDR4 modules and consumer electronics DDR4 chips [1][4][16] - **NAND Flash Demand**: The NAND Flash market is experiencing price increases driven by international circumstances, with enterprise SSD demand expected to support price growth in Q3 [1][21] - **AI Impact on Storage**: The global AI-driven storage market is projected to grow from $28.7 billion in 2024 to $255.2 billion by 2034, with a compound annual growth rate (CAGR) of 22.4% [1][5] - **CXL Technology**: CXL (Compute Express Link) is anticipated to reach a market size of nearly $16 billion by 2028, with China accounting for approximately $8 billion. CXL enhances memory utilization and reduces costs by about 50% per GB compared to traditional solutions [2][9][10] - **HBM Advantages**: High Bandwidth Memory (HBM) is expected to constitute over 10% of global DRAM capacity by 2025, with a market size projected to grow from $697.9 billion in 2024 to $893.4 billion in 2029, reflecting a CAGR of about 5% [1][8] Additional Important Insights - **Domestic Market Growth**: The Chinese enterprise SSD market is projected to recover to $6.25 billion in 2024, with expectations to reach $9.1 billion by 2029, indicating significant growth potential for local storage module manufacturers [3][24] - **3D DRAM Development**: The transition to 3D DRAM is gaining momentum, with manufacturers focusing on advanced packaging technologies to enhance performance and efficiency [6][18] - **Market Dynamics**: The DRAM market is witnessing a reshaping of niche market dynamics, with a notable shift towards 3D DRAM production as manufacturers pivot to DDR5 and HBM technologies [16][19] - **Emerging Applications**: The demand for NOR Flash is increasing due to growth in IoT, automotive electronics, and 5G applications, with specific requirements for capacity, lifespan, and reliability [25][26] - **Investment in AI Infrastructure**: Major cloud service providers are significantly increasing their capital expenditures for AI infrastructure, with companies like Meta, Google, and Alibaba planning substantial investments [22][23] Companies to Watch - **Key Companies**: Notable companies in the storage IC design and module sectors include Zhaoyi Innovation, Beijing Junzheng, Dongxin Technology, and others involved in various aspects of the semiconductor storage industry [28] Risks and Considerations - **Supply Chain Risks**: Potential disruptions in supply chains due to international policy changes could impact pricing and market conditions. Additionally, if the AI industry does not develop as expected, overall growth may be constrained [29]

Summary of Rambus Conference Call Company Overview - Rambus is a leading memory IP supplier with a history of 35 years in the semiconductor industry, focusing on foundational memory interface technology [3][4] - The company generates over 75% of its revenue from the data center end market [3] Revenue Streams - **Patent Licensing Program**: - Generates stable cash flow between $200 million to $210 million annually [4] - Supported by a robust portfolio of approximately 2,700 patents [4] - **Silicon IP Business**: - Revenue of about $120 million last year, with expected growth of 10% to 15% [5][46] - Focuses on security IP and interface controller IP [5] - **Memory Interface Chip Solutions**: - Revenue reached approximately $250 million last year, driven by leadership in DDR5 technology [6] Market Trends and Dynamics - The company has not seen direct impacts from tariffs, as it operates with manufacturing partners in Taiwan and Korea [9][10] - Inventory levels are described as reasonable, influenced by past DDR4 overhang and the introduction of DDR5 [11] - Rambus has nearly doubled its market share in DDR5, achieving around 40% compared to 20% in DDR4 [13][14] Growth Opportunities - **Companion Chips**: - Market opportunity of $600 million, with expected revenue contributions starting in the second half of 2025 [15] - **MRDIMM Solutions**: - First revenue contributions anticipated in the second half of 2026 [16] - **Client Opportunities**: - Growth in the client space as data center technology transitions into client applications [18] AI and Data Center Impact - AI is driving demand for higher memory density in servers, leading to increased DIMM counts [23][28] - The company sees AI as a tailwind for its product business, enhancing traditional content in AI servers [23] Custom ASIC and CXL Opportunities - The custom silicon market is expanding, with Rambus providing essential building blocks for faster time-to-market [30] - CXL technology is seen as a way to augment memory capacity and bandwidth, although its adoption has been delayed [39][40] Strategic Positioning - Rambus benefits from being the last U.S.-based supplier in its market, which is viewed as a long-term strategic advantage [44] - The company is transitioning from a patent licensing model to a semiconductor product solution company, with a roadmap extending through the DDR5 cycle and into DDR6 [48][49] Conclusion - Rambus is well-positioned for growth with diverse revenue streams, strong market share in DDR5, and strategic advantages in the evolving semiconductor landscape [47][50]

Core Viewpoint - Samsung Electronics is actively developing next-generation DRAM solutions to replace HBM (High Bandwidth Memory), with technologies like PIM (Processing-In-Memory) currently under standardization discussions in semiconductor organizations [1][2]. Group 1: Next-Generation DRAM Technologies - Key next-generation DRAM technologies include PIM, VCT (Vertical Channel Transistor), CXL (Compute Express Link), and LLW (Low Latency, High Bandwidth) DRAM, which are being developed for various potential customers and applications in the AI era [1][2]. - LPDDR (Low Power Double Data Rate) is currently commercialized up to LPDDR5X, with the standardization of the next generation, LPDDR6, nearing completion [2]. - PIM technology, which allows data processing capabilities within memory chips, is expected to enhance energy efficiency when combined with LPDDR [2]. - CXL is a next-generation interconnect interface designed for high-performance servers, enabling efficient connections between CPUs, GPU accelerators, DRAM, and storage devices, expanding memory bandwidth and capacity [2]. Group 2: Customization in HBM Market - The importance of "Custom HBM" in the next-generation HBM market is emphasized, with the base die of HBM4 being manufactured by foundries, allowing for product customization based on customer needs [3][4]. - This shift marks a significant transformation for Samsung's memory division, indicating a move towards tailored memory products for clients [4].