Core Viewpoint - The article emphasizes the significance of the 3Sheng Integration Platform developed by Silicon Chip Technology for the design and testing of 2.5D/3D stacked chips, highlighting its innovative features and capabilities in enhancing reliability and performance in chip systems [3][34]. Group 1: 3Sheng Integration Platform - The 3Sheng Integration Platform integrates system-level planning, physical implementation, analysis, testability, and reliability design for 3D stacked chips, supporting agile development and customizable collaborative design optimization [3][34]. - The platform features a unified data foundation and combines five engines: system, test, synthesis, simulation, and verification, showcasing originality in multiple functionalities and performance [3]. Group 2: Importance of DFT in Stacked Chips - Design for Testability (DFT) is crucial in stacked chip systems due to the unique interconnect testing requirements arising from multiple chiplets, necessitating specific testing before and after interconnection [6][10]. - The interconnect interfaces in stacked chips introduce new testing demands, including compatibility, connectivity integrity, and defect detection, which are not present in conventional chips [10][12]. Group 3: Testing Processes and DFT Requirements - The testing process for stacked chips includes pre-bond, mid-bond, post-bond, and final tests, with the accuracy and completeness of these tests being vital for product quality and cost-effectiveness [13][15]. - DFT plays a significant role in ensuring testability, controllability, and self-repair capabilities within the stacked chip systems, addressing various reliability concerns [15][16]. Group 4: Cross-Die Testing Solutions - The SiChip DFT technology offers a mixed testing solution that includes scan chains, boundary scan, built-in self-test (BIST), and diagnostic channels, adhering to various IEEE standards [17][19]. - The architecture design phase must consider DFT testing access mechanisms to ensure compatibility and universality across different manufacturers' dies [19][20]. Group 5: Diagnostic Testing and Functional Simulation - The 3Sheng Ocean EDA testing solution integrates fault diagnosis, functional simulation, and adaptive repair technologies, covering wafer-level circuit testing and final functional testing [25][27]. - The solution aims to optimize testing resources and reduce testing time while enhancing fault coverage, achieving a 50% reduction in testing costs and a 99.99% fault coverage rate [27]. Group 6: Fault Tolerance Design - The SiChip EDA DFT solution supports comprehensive redundancy and fault tolerance, utilizing eFPGA technology to create a full-process redundancy solution from top-level planning to physical implementation [29][31]. - The design allows for dynamic routing and protocol conversion, enhancing interconnect channel utilization and addressing thermal coupling and signal interference issues [31].

Core Viewpoint - The article discusses the current state and future potential of the mask and blank mask industry in China, particularly in the semiconductor and display panel sectors, highlighting the gaps in technology and production capabilities compared to international players [2][3][4]. Industry Overview - The mask plays a crucial role in the production of semiconductors and display panels, with domestic companies primarily focusing on 8.5 generation lines and below, lacking capabilities for high-generation and high-precision masks [2]. - In the semiconductor sector, while some domestic manufacturers can produce masks for 90nm and above processes, only a few can develop products for 65nm and 55nm nodes, indicating significant room for localization in the market for masks below 90nm [2]. Key Players and Product Layout - Major players in the mask industry include: - Qingyi Optoelectronics, which has achieved mass production of 180nm node masks and is developing 130nm-65nm node products [3]. - Huazhong Dishi Microelectronics, aiming for 90nm mass production in 2024 and 40nm by 2025 [4]. - Other notable companies include Longtu Photomask, Jinan Quanyi, and Shanghai Toppan, each focusing on various segments of the mask market [4][5]. Upcoming Events - The 2025 TrendBank (Fifth) Lithography Materials Industry Conference will be held from July 8 to 10 in Hefei, focusing on new applications, trends, and the supply chain in the lithography materials sector [8].

Core Viewpoint - The article discusses the competitive analysis of the capacitive touch chip industry in China, highlighting market demand, driving forces, development trends, domestic market share, and key players' business layouts in the touch IC sector [1][2]. Group 1: Capacitive Touch Chip Concept - Capacitive touch technology is based on capacitive sensing principles to detect the proximity or contact of conductive objects, converting changes in electric fields into digital signals for human-computer interaction. The main application markets include smartphones, tablets, laptops, smart wearables, smart home devices, and industrial control HMI products [1]. Group 2: Market Trends - The penetration rate of capacitive touch solutions in industrial control HMI products is stable at 35%, while in smart home applications, it has reached 60% due to increasing performance demands and smart home functionalities. Capacitive touch solutions have largely replaced resistive touch solutions in other application scenarios. TrendBank forecasts that by 2030, the market size for capacitive touch chips in China will reach 7.513 billion yuan, with a compound annual growth rate (CAGR) of 3.2% from 2020 to 2030. The largest application markets are smartphones and smart wearables, while the fastest-growing markets are smart home and automotive electronics, with CAGRs of 16.92% and 15.18%, respectively [2][4]. Group 3: Competitive Landscape - The capacitive touch chip market is primarily dominated by established players, with major manufacturers diversifying their product offerings as industry growth has slowed. Key domestic companies include Goodix Technology, GigaDevice (Silicon Motion), Jichuang North, Betley, and Hailuochuang, among others. Major international clients include Sony, Samsung, Apple, and Bosch, with a significant presence in China. According to TrendBank, Goodix Technology leads the market with a shipment share of 16%, primarily in the smartphone sector, followed by Hailuochuang with 15% in smart wearables, and Betley focusing on smart home products, especially smart door locks [4][6].

Core Viewpoint - The article discusses the advancements and challenges in lithography technology, particularly in the semiconductor industry, highlighting the need for innovative solutions to meet the growing demand for high-performance, low-energy, and scalable manufacturing processes [2][6][7]. Group 1: Industry Developments - The ability to manufacture nanoscale components is crucial for producing high-performance devices and driving technological advancements across various industries [2]. - Significant investments are being made in semiconductor research, with the U.S. government committing $280 billion through the CHIPS and Science Act, and the EU proposing $50 billion to double its chip production by 2023 [2]. - Taiwan Semiconductor Manufacturing Company plans to invest $33 billion by 2025 to keep pace with Moore's Law by entering new microchip markets [2]. Group 2: Lithography Technology Overview - Lithography is a manufacturing technique that creates patterned structures on substrates, with common methods including photolithography and electron beam lithography [3]. - Traditional lithography methods face challenges related to resolution, position control, and throughput, necessitating the development of new techniques to meet commercial application demands [3][7]. - Emerging lithography technologies are being developed to overcome the limitations of traditional methods, focusing on flexibility, scalability, and cost-effectiveness [6][7]. Group 3: Emerging Lithography Techniques - Various new lithography techniques are summarized, including: - **Nanoimprint Lithography**: High throughput and low cost, but may face issues with pattern replication [8]. - **Two-Photon Lithography**: Capable of generating smaller structures but has high time costs for large structures [8]. - **Block Copolymer Lithography**: Low cost but limited by the periodicity of microdomains [8]. - Each emerging technique has its advantages and disadvantages, with potential applications in various fields, including electronics and biomedicine [8][9]. Group 4: Upcoming Industry Events - The 2025 TrendBank (Fifth) Lithography Materials Industry Conference will be held from July 8-10 in Hefei, focusing on new applications, trends, and in-depth discussions on the lithography materials supply chain [11].

"宁波膜智信息科技有限公司"为势银（TrendBank）唯一工商注册实体及收款账户 添加文末微信，加 光刻胶 群 乙烯共聚物市场规模和份额预测 （2025年-2035年） 到2025年，全球电子材料和化学品市场估计为599亿美元。到2035年，预计将达到约986亿美元。从 2025年到2035年，这种扩张将以5.1%的复合年增长率发生。 这一增长主要是由对先进半导体、平 板显示器和光伏设备的需求不断增长的推动。 来源：网络 AI 数据中心和5G基础设施的广泛部署推动了需求。 在2025年第一季度财报电话会议上，空气产品 公司董事长兼首席执行官葛思民（Seifi Ghasemi）表示，"为了满足全球芯片制造商前所未有的需 求，人们对高纯度工艺化学品进行了创纪录的投资"，据报道，美国、台湾和韩国的需求强劲。英 特尔（俄亥俄州，2025 年）和台积电（日本，2025 年）的新制造厂导致 CMP 浆料、光刻胶和超 高纯度湿化学品的采购增加。 太阳能投资进一步加速了消费。 在Shin-Etsu Chemical Co. 于 2025 年 2 月发布的投资者更新中，该 公司确认将扩大为印度和中国的太阳能电池制造商生产高纯 ...

Core Viewpoint - The 2025 TrendBank (Fifth) Photoresist Materials Industry Conference will be held on July 9-10, 2025, in Hefei, Anhui, focusing on the collaboration between industry, academia, and research to promote industry development [14]. Group 1: Conference Details - The conference will take place at the Sheraton Hotel in Hefei, with an expected attendance of 300 participants [7]. - The agenda includes discussions on semiconductor, display, and packaging photoresists, wet electronic chemicals, mask plates, and specialty gases, covering technological breakthroughs and application trends [7][12]. - Over 10 academic and research institutions have confirmed participation and will present at the conference [4]. Group 2: Agenda Highlights - The first day will feature an opening ceremony, speeches from guiding and organizing units, and sessions on advanced lithography technology and industry development [5]. - The second day will include topics such as the latest advancements in extreme ultraviolet lithography technology, electron beam lithography, and the development of new display technologies [6]. - The third day will focus on the application mechanisms and key technologies of wet electronic chemicals, the current state of the electronic specialty gas market, and advancements in lithography equipment [6]. Group 3: Market Context - The global competition in the photoresist materials market is intensifying, with increasing technological innovation and rising barriers to technology protection [12]. - The semiconductor chip industry demands high-performance and high-precision manufacturing processes, making photoresist materials critical components [12]. - China's share in the global photoresist market is steadily increasing, supported by various government policies aimed at fostering a favorable development environment for the industry [13].

Core Viewpoint - The article discusses the advancements and challenges in Fan-Out Wafer-Level Packaging (FOWLP) technology, emphasizing the need for new materials and processes to enhance chip integration and performance [1][2][3]. Group 1: FOWLP Development - FOWLP aims to address the limitation of insufficient external contacts on chips by cutting wafers into pieces and reassembling them into a new wafer, increasing the chip's surface area for more external contacts [1]. - The manufacturing of FOWLP faces challenges such as the need for new high-temperature dielectrics that can cure at significantly lower temperatures, around 200°C, compatible with epoxy molding materials used in FOWLP [1][2]. Group 2: Process Challenges - Key challenges include eliminating unnecessary warping of the reconstructed wafer due to mismatched thermal expansion coefficients between the silicon epoxy layer and the polymer RDL layer [2]. - Designers must choose between "face-up" and "face-down" configurations to manage high profiles and non-planarity between chips and molds [2]. - Reliable connections for copper RDL lines are critical, as damaged lines can lead to electrical failures between chips and PCBs [2]. Group 3: Advanced Packaging Techniques - The application of stepper lithography in next-generation advanced packaging faces limitations, particularly in accurately reconstructing wafers from different manufacturers [3]. - The use of maskless exposure lithography technology is proposed as a solution to overcome the challenges posed by traditional stepper lithography, allowing for high-resolution patterns essential for advanced devices [3][4]. Group 4: MLE Technology - MLE technology has been demonstrated to achieve resolutions as low as 1.5 µm and high aspect ratios up to 1:7, successfully applied in standard copper plating processes [5]. - The dual-embedding process using MLE technology aims to reduce the number of lithography steps by 50%, showcasing its economic feasibility in advanced packaging applications [5][6]. Group 5: Industry Event - The 2025 TrendBank (Fifth) Lithography Materials Industry Conference will be held from July 8-10 in Hefei, focusing on new applications, trends, and in-depth discussions on the lithography materials supply chain [8].

Core Viewpoint - The 2025 TrendBank (Fifth) Photoresist Materials Industry Conference will be held on July 9-10, 2025, in Hefei, Anhui, focusing on the collaboration between industry, academia, and research to promote industry development [15][9]. Conference Overview - The conference will feature over 20 speakers from the photoresist materials industry, covering various topics related to application terminals, materials, equipment, and processes, providing new insights and prospects for the industry [8][10]. - The event aims to create an interactive platform for upstream and downstream supply chain connections [10]. Agenda Highlights - The agenda includes sessions on advanced lithography technology, market analysis of the Chinese photoresist market, and discussions on challenges and opportunities in new display technologies [5][7]. - Specific topics include the latest advancements in extreme ultraviolet lithography technology, electron beam lithography, and the development of new photoresists for displays [5][7]. Industry Context - The photoresist materials market is characterized by increasing global competition, accelerated technological innovation, and rising barriers to technology protection [13][14]. - The demand for high-performance and high-precision manufacturing processes in the semiconductor chip industry is driving the need for advancements in photoresist materials [14]. Participation and Registration - The conference is expected to host around 300 participants, with registration fees set at RMB 2600 before June 30 and RMB 2800 thereafter [11][9]. - Participants will receive conference materials, guest speaker presentations, and access to meals and a banquet [11]. Background and Significance - The development of the photoresist materials market is crucial for achieving breakthroughs in cutting-edge technology and ensuring the stability and diversification of the supply chain [14]. - Recent government policies at various levels aim to create a favorable environment for the growth of the photoresist materials industry, emphasizing the importance of achieving "win-win" scenarios across the industry chain [14].

Core Viewpoint - The 2025 TrendBank Photoresist Materials Industry Conference will focus on the collaboration between industry, academia, and research to promote the development of the photoresist materials sector, amidst increasing global competition and technological innovation in the semiconductor industry [4][6]. Group 1: Conference Background - The photoresist materials market is experiencing intensified global competition, accelerated technological innovation, and rising barriers to technology protection as of 2025 [4]. - The demand for high-performance and high-precision manufacturing processes in the semiconductor chip industry is driving the need for advancements in photoresist materials [4]. - The international landscape is marked by a blend of cooperation and competition, presenting both significant opportunities and challenges for the photoresist materials industry [4]. Group 2: Industry Development - The growth of China's photoresist materials market is not only a trend but also a crucial element for achieving breakthroughs in cutting-edge technology at the national level [5]. - Various supportive policies have been introduced at both national and provincial levels to create a favorable environment for the development of photoresist materials and related industries [5]. - Companies in the photoresist materials supply chain should seize the opportunity to strengthen their capabilities and pursue a "win-win" strategy across the industry [5]. Group 3: Conference Details - The 2025 TrendBank Photoresist Materials Industry Conference will be held on July 9-10, 2025, in Hefei, Anhui, with a focus on "collaboration between industry, academia, and research to support industry development" [6]. - The conference will cover discussions on semiconductor, display, and packaging photoresists, as well as wet electronic chemicals and specialty gases, addressing technological breakthroughs and application trends [6][9]. - The event will feature over 20 industry chain guest speakers, academic discussions, and a combination of conference and exhibition formats to foster industry interaction and supply chain connections [8][9].

Core Viewpoint - The article discusses the advancements and importance of 3D integrated circuits (3D IC) and the role of EDA tools like 3Sheng Stratify™ in ensuring the accuracy and integrity of stacked chip designs, which are crucial for high-performance applications in various industries [3][30]. Group 1: 3D IC and Advanced Packaging - 3D IC technology provides significant flexibility and reusability in product design, particularly for AI computing and high-end mixed-signal integration [3]. - Stacked chips utilize advanced packaging techniques that are essential for performance, functionality, cost, and iteration methods [3]. - The demand for high-density interconnect advanced packaging is growing across various applications, including military, aerospace, and consumer electronics [4]. Group 2: EDA Tools and Verification - 3Sheng Stratify™ EDA tool offers rapid and accurate assembly-level verification for interconnections between dies and intermediary layers in stacked chip designs [10]. - The tool supports design rule checks (DRC) and layout versus schematic (LVS) checks to ensure consistency and compliance with design specifications [10][12]. - The verification process includes checks for signal integrity and functionality across complex interconnect structures [9]. Group 3: Key Performance Indicators - The EDA tool provides various functionalities, including high-density interconnect verification, static timing analysis, and design rule compliance checks [12][13]. - It also features automated detection of anomalies and supports multi-file collaborative checks to enhance design efficiency [13][14]. - The tool aims to improve manufacturability and reliability of 2.5D designs by ensuring that physical layouts meet manufacturing process specifications [23]. Group 4: Design Rule Checks and Automation - The 3Sheng DRC tool supports a wide range of design rule checks, including geometric rules and special process checks, to ensure compliance with foundry specifications [25][28]. - The tool incorporates machine learning algorithms for anomaly detection in 2.5D designs, enhancing the accuracy of network connection checks [18][20]. - Automated repair features are included to address design rule violations, thereby reducing manual intervention and speeding up the design iteration process [28][29]. Group 5: Future Directions - The company aims to enhance the automation design capabilities for 2.5D/3D/3.5D systems, providing comprehensive design and verification solutions to the industry [31]. - The integration of various design engines within the 3Sheng Integration Platform facilitates rapid design and verification processes, ensuring a balance between performance, power consumption, area, and cost [30].