Core Viewpoint - TSMC is actively developing advanced packaging technology called System over Wafer (SoW), which integrates large-scale, high-speed systems on 300mm silicon wafers or similar-sized substrates, offering high computational power, fast data transmission, and reduced power consumption [1][3]. Group 1: InFO Technology Development - The origin of SoW technology lies in TSMC's InFO (Integrated Fan-Out) packaging technology, designed for mobile processors, which allows for miniaturization and thin packaging [3]. - TSMC provided CoWoS (Chip on Wafer) packaging technology for high-performance large-scale logic (FPGA, GPU) around 2020, utilizing silicon interposers for high-density connections [3]. - TSMC has also prepared and mass-produced InFO_oS (Chip on Wafer) technology, which uses InFO for high-density connections between chips, serving as a low-cost packaging solution for high-performance large-scale logic [3][5]. Group 2: InFO_SoW Application - InFO_SoW extends the RDL size of InFO_oS to 300mm silicon wafers, placing multiple silicon chips face down on the RDL, with power modules and I/O IC connectors installed on the back [5][6]. - The basic structure of InFO_SoW features a six-layer wiring design with different rules for the silicon side and the back, capable of handling approximately 7,000W of power through water cooling [6][19]. Group 3: Cerebras Systems and WSE Technology - Cerebras Systems has applied InFO_SoW technology in its deep learning accelerator, the WSE (Wafer Scale Engine), which has a surface area of 46,225 square mm [10][19]. - The main difference between InFO_SoW and WSE technology lies in how they handle silicon chips; InFO_SoW assumes small chips are placed on a wafer-sized RDL, while WSE manufactures 84 microchips on a 300mm wafer [10][11]. - Cerebras has released multiple generations of WSE, with the first generation using 16nm technology, the second generation using 7nm, and the third generation using 5nm technology, significantly increasing transistor counts [17][18]. Group 4: Performance and Future Developments - The performance of InFO_SoW technology shows a reduction in wiring width/spacing by half compared to multi-chip modules (MCM), doubling the wiring density and data transmission rate per unit length [19]. - TSMC is also developing the next generation of InFO_SoW technology, named SoW-X (eXtreme), which differs from SoW-P by distributing components across processors and memory modules [21][23].

Core Viewpoint - Company Qizhong Technology plans to raise up to 850 million yuan through convertible bonds to invest in two projects aimed at enhancing its advanced packaging and testing capabilities for integrated circuits [1][5]. Investment Projects - The total investment for the high-pin-count micro-sized bump packaging and testing project is approximately 41.95 million yuan, with the company planning to use 41.9 million yuan from the raised funds [3]. - The advanced power and flip-chip packaging technology renovation project at Qizhong Technology (Suzhou) has a total investment of about 43.17 million yuan, with 43.1 million yuan expected to be funded from the new issuance [3]. - The combined total investment for both projects is around 85.11 million yuan, with the company intending to utilize 85 million yuan from the fundraising [3]. Business Focus and Market Position - Over half of the raised funds will be allocated to enhance the packaging and testing capacity for non-display chips, which currently contribute less than 10% to the company's revenue in 2024 [5]. - Qizhong Technology is one of the few domestic firms capable of large-scale production of various bump manufacturing technologies and has maintained a leading position in advanced packaging technology [6]. - The company reported a projected revenue of nearly 2 billion yuan in 2024, with its display driver chip packaging business expected to sell 1.845 billion units, generating 1.758 billion yuan in revenue, ranking third globally in this sector [6]. Financial Performance and Stock Status - Since its IPO in April 2023, Qizhong Technology's stock has underperformed, trading below its initial offering price of 12.1 yuan per share, with a notable drop to around 8 yuan [9]. - The company has experienced a decline in net profit, reporting 313 million yuan in 2024, a decrease of 15.71% year-on-year, attributed to rising costs such as equipment depreciation and employee compensation [10]. - The company plans to repurchase shares at a price not exceeding 16.61 yuan per share, with a total repurchase amount between 75 million and 150 million yuan [9].

Core Viewpoint - Yongxi Electronics (Ningbo) Co., Ltd. is issuing convertible bonds with a total amount not exceeding 1.2 billion yuan, with a term of 6 years and an annual interest payment structure [3][4]. Company Overview - Yongxi Electronics was established on November 13, 2017, and was listed on the Shanghai Stock Exchange's Sci-Tech Innovation Board in November 2022 [8]. - The company primarily engages in integrated circuit packaging and testing, with a focus on advanced packaging technologies [8][12]. Financial Performance - The company reported total assets of 123.31 billion yuan and total liabilities of 83.33 billion yuan as of 2023 [6]. - The operating revenue for 2023 was 23.91 billion yuan, showing a growth trend in recent years [8][12]. - The net profit for 2023 was 1.37 billion yuan, indicating a recovery from previous losses [6][22]. Rating and Outlook - The credit rating assigned to Yongxi Electronics is A+ with a stable outlook, indicating a solid credit level expected to remain stable over the next 12 to 18 months [3][4]. - Factors that could lead to an upgrade include significant improvements in industry position and profitability, while factors for downgrade include adverse changes in supply chain stability and demand [4][5]. Industry Context - The global outsourced packaging market was valued at 85.7 billion USD in 2023, with advanced packaging accounting for 48.8% of the market [12]. - The semiconductor packaging industry is experiencing a shift towards advanced packaging technologies due to increasing demand for high-performance computing [12][11]. - The industry is characterized by high technical and financial requirements, with leading companies holding significant market shares [11][12]. Operational Strengths - The company has established long-term partnerships with major domestic chip manufacturers, enhancing customer loyalty [5][16]. - Yongxi Electronics has a diverse product range in advanced packaging, including QFN/DFN and system-in-package (SiP) technologies [13][15]. - The company has been increasing its R&D investment, with a focus on high-density packaging technologies and maintaining a competitive edge [20][21]. Challenges and Risks - The company faces challenges related to its relatively short establishment period and lower production capacity compared to industry leaders [5][17]. - The financial leverage is high due to ongoing capital expenditures, which may impact profitability if not managed effectively [21][22]. - The company’s ability to maintain profitability is under pressure from declining product prices and increased operational costs [22].

Core Viewpoint - Huawei has applied for a "quad-chiplet" packaging design patent, potentially for next-generation AI chips, which may allow it to compete with TSMC and NVIDIA in the AI GPU market [2][4]. Group 1: Patent and Technology Development - The "quad-chiplet" design is similar to NVIDIA's Rubin Ultra architecture, but Huawei appears to be developing its own advanced packaging technology [4]. - The patent indicates a bridging technology, akin to TSMC's CoWoS-L, rather than a simple intermediate layer [4]. - To meet the demands of AI training processors, the chips are expected to be paired with multiple HBM (High Bandwidth Memory) through interconnections [4]. Group 2: Competitive Positioning - Although Huawei currently lags in advanced process technology by one generation, its advanced packaging capabilities may be on par with TSMC [4]. - This advancement allows Chinese manufacturers to use mature process technologies to produce multiple chips, which can then be integrated through packaging to enhance performance, potentially narrowing the gap with advanced process chips [4]. - Ren Zhengfei, Huawei's founder, has stated that concerns over chip technology are unwarranted, suggesting that methods like stacking and clustering can yield results comparable to the most advanced levels [4].

Core Viewpoint - The article discusses the significant advancements and challenges in TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging technology, particularly in relation to NVIDIA's evolving needs in the AI sector, highlighting the shift towards CoWoS-L and the emergence of CoPoS (Chip-on-Panel-on-Substrate) as a potential alternative [1][3][10]. Group 1: TSMC and NVIDIA Collaboration - TSMC has become a crucial partner for NVIDIA, especially in the CoWoS domain, with NVIDIA's CEO Jensen Huang stating that they have no alternative to TSMC for this advanced packaging technology [1]. - NVIDIA is transitioning to use more CoWoS-L packaging for its latest Blackwell series products, which require high bandwidth interconnects between chips [3][5]. Group 2: CoWoS Technology Evolution - The CoWoS technology is facing challenges due to increasing chip sizes, with AI chips potentially reaching dimensions of 80x84 mm, limiting the number of chips per wafer [5]. - TSMC is exploring alternatives to traditional solder paste bonding methods due to difficulties in maintaining yield rates, including the development of no-solder paste bonding technology [6][9]. Group 3: Future Developments in Packaging - TSMC plans to introduce CoWoS-L with a mask size of 5.5 times the current size by 2026, and a record 9.5 times mask size CoWoS by 2027 [9]. - CoPoS technology is being developed as a next-generation packaging solution, with plans for mass production by 2029, aiming to enhance efficiency and reduce costs by utilizing larger rectangular substrates [12][14]. Group 4: Comparison of Packaging Technologies - CoPoS differs from FOPLP (Fan-out Panel-Level Packaging) in that it uses an interposer for better signal integrity and power delivery, making it suitable for high-performance applications [13]. - The transition from traditional organic substrates to glass substrates in CoPoS is expected to improve interconnect density and thermal stability, positioning it as a potential successor to CoWoS-L [14].

Core Viewpoint - Intel has made significant advancements in chip packaging technology under the leadership of new CEO Chen Liwu, particularly with the introduction of the EMIB-T technology, which enhances chip packaging size and power delivery capabilities to support new technologies like HBM4/4e [1][9]. Group 1: EMIB-T Technology Advancements - EMIB-T integrates TSV (Through-Silicon Via) for vertical signal transmission between chips, reducing power transmission resistance by over 30%, which minimizes voltage drop and signal noise [2][6]. - The technology incorporates high-density MIM (Metal-Insulator-Metal) capacitors to suppress power noise, ensuring signal integrity, especially in high-performance applications like AI accelerators and data center processors [2][7]. - EMIB-T supports a maximum package size of 120x180 mm, allowing integration of over 38 bridges and 12 dies, with plans to reduce bump pitch from 45 microns to as low as 25 microns in the future [2][7]. Group 2: Strategic Importance and Market Position - Intel's foundry aims to leverage cutting-edge process node technologies to manufacture chips for both internal and external clients, enhancing performance, cost, and energy efficiency through complex heterogeneous designs [4][5]. - The EMIB-T technology is crucial for supporting HBM4 memory and UCIe interconnect requirements, making it an ideal packaging solution for AI accelerators, data center processors, and supercomputing chips [7][8]. - Intel plans to achieve mass production of EMIB-T packaging by the second half of 2025, with a vision to integrate over 24 HBM chips in a single package by 2028, significantly impacting global semiconductor packaging technology [9].

Core Insights - The rigid copper-clad laminate (CCL) industry in China experienced rapid growth from 2019 to 2021 due to accelerated 5G base station construction, surging demand for electronic components in electric vehicles, and increased consumer electronics demand driven by the pandemic. However, starting in 2022, the industry entered an adjustment phase due to global economic recession, weak consumer electronics demand, and semiconductor supply chain disruptions. In 2023, the industry continued to contract, with sales volume slightly decreasing to 524.9 million square meters and sales revenue shrinking to 9.334 billion yuan, representing a year-on-year decline of 16.3% [2]. Industry Overview - Rigid copper-clad laminates, also known as copper foil laminated boards, play a crucial role in electronic circuit manufacturing, providing conductivity, insulation, and support. They significantly impact signal transmission speed, energy loss, and characteristic impedance. Rigid copper-clad laminates are characterized by their hardness and toughness, making them suitable for applications in communication devices, household appliances, electronic toys, and computer peripherals [3]. Policy Background - China's policy support for the rigid copper-clad laminate industry is characterized by multi-level and multi-dimensional collaborative promotion, focusing on technological upgrades, intelligent equipment transformation, and green transition. Key policy areas include supporting the R&D breakthroughs of high-frequency and high-speed copper-clad laminates and high-performance substrates, optimizing production processes, and establishing standardized testing systems to enhance product reliability. Additionally, policies encourage enterprises to strengthen pilot testing capabilities through advanced equipment updates and promote sustainable development through the adoption of environmentally friendly materials and clean production processes [5][6]. Industry Chain - The rigid copper-clad laminate industry chain in China consists of upstream suppliers of key raw materials such as electronic-grade glass fiber cloth, copper foil, resin, and wood pulp paper, which provide the foundational materials for laminate manufacturing. The midstream focuses on the production and manufacturing of rigid copper-clad laminates through processes like lamination and coating. The downstream applications cover communication devices, household appliances, electronic toys, and computer peripherals, directly serving the demands of consumer electronics, communication technology, and home appliance industries [7]. Current Industry Status - In 2023, the global rigid copper-clad laminate market faced a decline due to macroeconomic fluctuations, with total sales revenue dropping by 16.3% to 12.734 billion USD and sales volume slightly decreasing by 1.1% to 656.8 million square meters. Among the product categories, conventional FR-4 maintained the largest sales revenue share at 33.38%, while special resin-based and dedicated CCL (including high-speed, high-frequency, and IC carrier boards) increased their share to 32.88%, driven by resilient high-end demand from AI servers, 5G communication, and advanced packaging technologies. The demand for halogen-free FR-4 and high Tg FR-4 has contracted due to weakened consumer electronics and automotive electronics demand, while composite and paper-based CCL accounted for less than 10% of the market, leading to a rapid exit of traditional low-end products. Notably, high-speed CCL (including halogen-free types) showed outstanding performance among the three special laminates, with sales revenue increasing by 5.5% despite market challenges, driven by rising technical barriers [9].

Group 1 - Glass substrates are characterized by high transparency, excellent flatness, and good stability, serving as a support carrier to ensure the reliable fixation of functional materials and the overall stability and lifespan of devices [1][2] - The global advanced packaging market is projected to grow from $28.8 billion in 2019 to $42.5 billion by 2024, indicating a rising penetration rate [1][13] - The introduction of glass substrates can reduce capacitance between interconnections, leading to faster signal transmission and improved overall performance, particularly in data centers, telecommunications, and high-performance computing applications [1][15] Group 2 - The glass substrate industry chain includes key segments such as raw materials, equipment, technology, production, packaging testing, and applications, with special glass materials being crucial for semiconductor manufacturing [6] - The TGV (Through Glass Via) technology is a core technique for glass substrate packaging, enabling vertical electrical interconnections and addressing challenges associated with traditional TSV technology [19][20] - The glass substrate market is expected to reach over $400 million by 2030, with a penetration rate exceeding 2%, although organic substrates will continue to dominate the semiconductor packaging field in the near term [15][17] Group 3 - The glass substrate technology is anticipated to play a significant role in the semiconductor industry, with ongoing advancements focusing on process optimization, improving via precision and density, and expanding the functional applications of glass substrates [25] - The global semiconductor market is projected to reach $635.1 billion in 2024, reflecting a 19.8% year-on-year growth, driven by the increasing demand for high-performance semiconductor products [9]

Investment Rating - The report does not explicitly provide an investment rating for the advanced packaging equipment industry. Core Insights - The advanced packaging technology aims to enhance chip performance, increase functional integration, reduce product size, and improve thermal management capabilities, driven by the demand for high-performance electronic products. The key to achieving these advanced packaging technologies lies in advanced packaging equipment [2]. Summary by Sections Semiconductor Packaging Equipment Industry Overview - Traditional packaging focuses on low cost and simple structures, while advanced packaging utilizes high-density interconnects, heterogeneous integration, and 3D stacking technologies to meet the demands of high-performance computing, 5G, and AI [16]. - The global semiconductor manufacturing equipment sales are projected to grow from $106.3 billion in 2023 to $117.1 billion in 2024, with advanced packaging driving an increase in the share of packaging equipment sales [21][22]. Required Semiconductor Equipment for Packaging Processes - Advanced packaging introduces new applications such as wafer thinning, RDL (Redistribution Layer) production, bump production, and TSV (Through-Silicon Via) production, necessitating both existing backend packaging equipment and new front-end equipment [9][27]. - The traditional backend packaging equipment must undergo technological upgrades to accommodate smaller sizes, higher integration, and more complex structures, focusing on precision, material compatibility, process control, and automation [32]. Advanced Packaging Equipment Analysis - The report highlights the need for various semiconductor equipment types, including thinning machines, dicing machines, and bonding machines, to support advanced packaging processes [35][45]. - The global thinning machine market is dominated by Japanese companies, with a concentration ratio of approximately 85%, while domestic companies like Huahai Qingke and Jing Sheng Machinery are emerging players [40][44]. Traditional Backend Equipment Upgrades and Manufacturers - Traditional backend packaging equipment requires upgrades to meet the demands of advanced packaging, focusing on precision enhancement, material compatibility, process control, and automation [32]. - Key domestic suppliers for thinning machines include Huahai Qingke, Jing Sheng Machinery, and China Electronics Technology Group [32].

Core Viewpoint - The article discusses the advancements and importance of 3D integrated circuits (3D IC) and the role of EDA tools like 3Sheng Stratify™ in ensuring the accuracy and integrity of stacked chip designs, which are crucial for high-performance applications in various industries [3][30]. Group 1: 3D IC and Advanced Packaging - 3D IC technology provides significant flexibility and reusability in product design, particularly for AI computing and high-end mixed-signal integration [3]. - Stacked chips utilize advanced packaging techniques that are essential for performance, functionality, cost, and iteration methods [3]. - The demand for high-density interconnect advanced packaging is growing across various applications, including military, aerospace, and consumer electronics [4]. Group 2: EDA Tools and Verification - 3Sheng Stratify™ EDA tool offers rapid and accurate assembly-level verification for interconnections between dies and intermediary layers in stacked chip designs [10]. - The tool supports design rule checks (DRC) and layout versus schematic (LVS) checks to ensure consistency and compliance with design specifications [10][12]. - The verification process includes checks for signal integrity and functionality across complex interconnect structures [9]. Group 3: Key Performance Indicators - The EDA tool provides various functionalities, including high-density interconnect verification, static timing analysis, and design rule compliance checks [12][13]. - It also features automated detection of anomalies and supports multi-file collaborative checks to enhance design efficiency [13][14]. - The tool aims to improve manufacturability and reliability of 2.5D designs by ensuring that physical layouts meet manufacturing process specifications [23]. Group 4: Design Rule Checks and Automation - The 3Sheng DRC tool supports a wide range of design rule checks, including geometric rules and special process checks, to ensure compliance with foundry specifications [25][28]. - The tool incorporates machine learning algorithms for anomaly detection in 2.5D designs, enhancing the accuracy of network connection checks [18][20]. - Automated repair features are included to address design rule violations, thereby reducing manual intervention and speeding up the design iteration process [28][29]. Group 5: Future Directions - The company aims to enhance the automation design capabilities for 2.5D/3D/3.5D systems, providing comprehensive design and verification solutions to the industry [31]. - The integration of various design engines within the 3Sheng Integration Platform facilitates rapid design and verification processes, ensuring a balance between performance, power consumption, area, and cost [30].