Summary of Semiconductor Advanced Packaging Industry Conference Call Industry Overview - The advanced packaging industry has become a key path to surpass Moore's Law, addressing physical bottlenecks such as high leakage power, exponential cost increases, and signal transmission losses in processes below 7nm [1][2][3] Core Technologies and Their Applications - **CoWoS-S**: Utilizes silicon interposer and TSV for high-performance interconnection, primarily used in flagship AI chips like NVIDIA H100/A100 and AMD MI300, but at a high cost [1][6] - **CoWoS-L**: Balances performance and cost through local interconnects, currently accounting for about 60% of TSMC's 2.5D packaging for Intel, and is the direction for future large AI chips and domestic companies like Huawei and Cambricon [1][6] - **CoPoS**: Replaces circular silicon interposer with rectangular panels, potentially increasing material utilization from 70%-75% to 100%. TSMC plans to trial production in 2026 and mass production in 2027, while domestic firms are in the research and prototyping phase [1][7] - **CoWoP**: Aims to eliminate the expensive substrate step by directly mounting chips onto PCBs, but is still in conceptual research due to engineering constraints [1][7] Industry Dynamics and Constraints - The necessity for advanced packaging arises from three main constraints: 1. **Physical Limits**: Quantum tunneling effects lead to significant leakage power increases as processes advance below 7nm and 5nm, making further miniaturization less cost-effective [2][3] 2. **Cost Constraints**: Increased complexity in processes raises overall costs exponentially due to more equipment, materials, and mask layers [2][3] 3. **Performance Bottlenecks**: Longer data and current transmission paths within chips lead to higher losses, hindering effective computational power release [2][3] Global and Domestic Players - Major global players in advanced packaging include TSMC, Intel, and Samsung, with OSAT firms like ASE also advancing their capabilities. Domestic firms like Changdian Technology are also positioning themselves in this space [4] Differences Between 2.5D and 3D Packaging - **2.5D Packaging**: Focuses on horizontal integration with multiple chips placed side by side on a silicon interposer, exemplified by CoWoS [5] - **3D Packaging**: Involves vertical stacking of chips, allowing for higher interconnection density and bandwidth, typically seen in HBM stacks [5] CoWoS Variants and Their Characteristics - **CoWoS-S**: High performance but high cost, used in flagship AI chips [6] - **CoWoS-R**: Uses organic RDL for flexibility and lower costs, suitable for cost-sensitive applications [6] - **CoWoS-L**: Aims for a balance between performance, cost, and size, suitable for future large AI chips [6] Future Trends and Directions - The penetration of CoWoS-L is expected to increase as domestic AI chip manufacturers like Huawei and Cambricon transition from CoWoS-S to CoWoS-L as their production volumes rise [6]

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Core Insights - TSMC's advanced packaging capacity is severely undersupplied, prompting aggressive expansion efforts, including the unveiling of the AP7 facility in Chiayi, which will serve major clients like Apple [1][2] - The AP7 facility is set to enter its first phase of equipment installation, focusing on mass production of the SoIC technology platform, with a second phase expected to begin production this year [1] - The AP7 site has potential for at least six additional phases of expansion to meet the growing demands of clients and the AI market [1] Group 1 - AP7 is TSMC's sixth advanced packaging facility, previously undisclosed to the public, and was showcased during a media tour led by TSMC's senior vice president [1] - The first phase of AP7 is designed for SoIC technology mass production, while the second phase will support Apple's wafer-level multi-chip module (WMCM) technology [1] - AP7 is anticipated to become TSMC's largest advanced packaging facility, with future phases potentially incorporating new advanced packaging processes like CoPoS, expected to begin production by 2028-2029 [1] Group 2 - TSMC is expanding its advanced packaging capacity through both in-house production and outsourcing, with AP7 being the first facility located in Chiayi [2] - TSMC has integrated advanced packaging technology into the 3DFabric domain, including the SoIC platform, which consists of two stacking solutions: SoIC-P and SoIC-X [2] - The SoIC technology for N3-on-N4 stacking is projected to enter mass production in 2025, with a spacing of 6μm, while the next-generation SoIC A14-on-N2 is expected to be ready by 2029 [2]

Core Viewpoint - TSMC is focusing on advanced packaging as a key growth area, with plans to establish a "General Factory Manager" position to oversee all facilities, likely filled by Chen Cheng-hsien, who has extensive experience in the company [1][2]. Group 1: Advanced Packaging Business - TSMC's advanced packaging business, previously contributing about 6-7% of revenue, is expected to grow significantly due to surging AI demand, particularly for CoWoS technology, which has been in development since 2009 [1][3]. - The gross margin for TSMC's advanced packaging business has reached approximately 80%, contributing significantly to the company's overall profitability [1]. - TSMC is expanding its advanced packaging capabilities with new facilities in Taiwan and Arizona, including two new advanced packaging plants expected to be operational by the end of 2028 [3][4]. Group 2: Leadership Changes - Recent retirements of key executives, including Lin Jin-kun and Yu Zhen-hua, have led to increased attention on TSMC's succession planning and leadership transitions [2]. - Chen Cheng-hsien is anticipated to be promoted to the newly created "General Factory Manager" role, overseeing multiple advanced packaging facilities [2][3]. - TSMC is expected to announce further leadership changes by late January 2026, reflecting ongoing organizational adjustments [2]. Group 3: Technological Developments - TSMC is advancing its CoWoS technology, with new variants like CoWoS-S, CoWoS-R, and CoWoS-L being developed to meet high-performance computing (HPC) needs [4]. - The company plans to introduce a new CoWoS-L technology with a 5.5x larger mask size to address the high demand for this advanced packaging solution [4]. - TSMC is also shifting focus to CoPoS technology, integrating CoWoS with fan-out panel-level packaging (FOPLP), with plans to establish a CoPoS pilot line by 2026 [5].

Group 1 - The core viewpoint of the article emphasizes TSMC's acceleration in capacity optimization and process reconfiguration to meet the substantial demand for AI GPUs and custom ASICs as they enter mass production [1] - TSMC is implementing strategies such as optimizing existing production lines and transitioning older nodes (7nm and 5nm) to 3nm processes to enhance capital efficiency [1][4] - The 3nm process is identified as the real bottleneck for the upcoming year, with TSMC's advanced packaging solution, CoWoS, expected to remain the mainstream packaging method for AI chips [1][2] Group 2 - The semiconductor industry is witnessing a decrease in the number of effective chips per wafer due to the introduction of more computational units and I/O designs in AI GPUs and ASICs, leading to increased demand for advanced process wafers [2] - TSMC plans to establish a CoPoS RD experimental line in Q2 of next year, with mass production expected by 2028, focusing on improving the efficiency of chip packaging [2] - TSMC's 2nm process is set to begin next year, with capacity already booked until the end of 2026, driven by the GAA architecture which offers significant performance and efficiency improvements over FinFET technology [4][5] Group 3 - Major clients for TSMC's 2nm process include Qualcomm, MediaTek, Apple, and AMD, with Apple reportedly reserving over half of the initial capacity to suppress competitors [5] - TSMC aims to increase its monthly output of 2nm chips to 100,000 by the end of 2026, positioning this cutting-edge technology as a key growth driver for the company [5]

Core Viewpoint - The rapid proliferation of AI applications is driving demand for advanced packaging technologies in the semiconductor industry, with TSMC's CoWoS becoming a well-known solution. The company is also developing next-generation packaging technologies like CoPoS and CoWoP to enhance area utilization and cooling efficiency [1][10]. Group 1: Advanced Packaging Technologies - CoWoS (Chip-on-Wafer-on-Substrate) integrates multiple chips on a substrate to reduce space and improve performance, particularly for AI chips requiring high bandwidth and low latency [2][6]. - TSMC's CoWoS-L variant has seen a significant increase in demand, accounting for approximately 60% of CoWoS sales, due to its lower cost and ability to integrate passive components [6][9]. - The next-generation packaging technologies, CoPoS and CoWoP, aim to reduce costs and improve efficiency, with CoPoS utilizing a rectangular panel to enhance area utilization [10][11]. Group 2: Market Growth and Projections - The Taiwanese semiconductor packaging industry is projected to reach NT$710.4 billion by 2025, with a CAGR of 13.9%, and further growth to NT$759 billion by 2026, driven by AI and HPC infrastructure demands [1][2]. - TSMC's advanced packaging capacity is expected to grow significantly, with CoWoS capacity increasing by over 80% and SoIC capacity by more than 100% from 2022 to 2026 [2][9]. Group 3: Industry Challenges and Developments - The semiconductor industry faces challenges in meeting the increasing demand for advanced packaging, necessitating collaboration and innovation among manufacturers [10]. - TSMC is expanding its advanced packaging facilities in the U.S. and Taiwan, with plans to start testing CoPoS by 2026 and mass production by 2028 [8][9]. - The shift towards advanced packaging is shortening the time from design to mass production, reducing the development cycle from approximately 1.5 years to less than a year [9][10].

Summary of Key Points from the Conference Call Industry Overview - **Industry Focus**: Semiconductor and Semiconductor Capital Equipment (SPE) sector - **Market Forecast**: Wafer Fab Equipment (WFE) market is projected to grow by 2% YoY in CY2025, 11% in CY2026, and 8% in CY2027, driven by increased demand for generative AI and improved capital expenditure (capex) from device makers [2][6][15] Core Insights - **WFE Market Growth**: The WFE market grew approximately 9% YoY in 2024 and is expected to expand further due to rising demand for complex technologies such as DRAM interconnect etching and 3D NAND flash memory layers [6][15] - **Semiconductor Shipments**: Global semiconductor shipments increased by 28% YoY in September 2025, marking 25 consecutive months of growth, driven by advanced logic chips and HBM for generative AI [6][15] - **Advanced Packaging Technologies**: The Taiwan advanced packaging equipment sector is expected to see structural growth, with significant demand for CoWoS and CoPoS technologies, particularly in AI applications [7][24][47] Technology Developments - **CoWoS and CoPoS**: CoWoS capacity is forecasted to reach 105k and 125k wafers per minute (wfpm) by the end of 2026 and 2027, respectively. CoPoS is anticipated to succeed CoWoS by 2028, potentially increasing average selling prices (ASP) by 50-100% due to its complexity [7][24][47] - **HBM-TCB Technology**: Flux-based TCB is expected to dominate until 20-Hi HBM5, with a shift to HCB anticipated due to physical limitations. Hanmi is expected to maintain a significant market share in TCB technology [8][49] Stock Recommendations - **Preferred Stocks**: - **Japan**: Tokyo Electron (8035 JT) and Advantest (6857 JT) are favored due to their exposure to the growing WFE market and increased test times [8][49] - **Taiwan**: Grand Process Tech (3131 TT) is preferred over Scientech (3583 TT) and All Ring Tech (6187 TT) based on advanced packaging ramp-up timelines [7][47] Additional Insights - **Capex Trends**: TSMC's capex is projected to increase to $48 billion in 2026 and $52 billion in 2027, driven by generative AI demand and technology transitions [24][47] - **Memory Chip Market Dynamics**: The memory chip market is expected to experience a stronger and longer-lasting upcycle, with rising prices for DRAM and NAND chips due to supply constraints and increased demand for AI applications [24][25] - **Chinese Semiconductor Market**: Preference for SPE makers and foundries is noted, with expectations of sustained capex and domestic demand, while fabless companies may face margin pressures [25][49] Conclusion - The semiconductor industry is poised for significant growth driven by advancements in AI and technology, with specific focus on WFE and advanced packaging technologies. Stock recommendations reflect a positive outlook on companies well-positioned to benefit from these trends.

Summary of Key Points from the Conference Call Industry Overview - The conference focused on the AI computing industry, highlighting the significant role of system vendors like NVIDIA and Google in shaping market trends, while TSMC and ASML are pivotal in providing technological platforms [1][2] - Silicon photonics technology emerged as a key topic, aimed at reducing energy consumption unrelated to computation, with large-scale commercialization expected by 2027 [1][2] Company Insights TSMC - TSMC is advancing steadily in its technology, with 2nm process expected to achieve mass production by 2025 and ongoing development of 3nm technology, enhancing its pricing power and customer profitability [1][3] - Under the Foundry 2.0 concept, TSMC's advanced packaging revenue is accelerating, with six operational factories and plans for four new ones, including expansions of CoWoS, SoIC, and CoPoS platforms [1][15] - TSMC's average selling price (ASP) has nearly doubled from $3,000 in 2019 to over $7,000 currently, driven by its technological advantages [13] - Future revenue growth for TSMC is heavily reliant on high-performance computing (HPC) clients, with a 70%-80% growth rate among these customers [16] - TSMC's capital expenditures have increased, with a peak in 2021 at 50% of revenue, but the pressure is expected to ease moving forward [21] Oracle - Oracle's capital expenditures have significantly increased, potentially linked to securing a large order from OpenAI, which could drive additional computing demand [3][19] - If Oracle executes on its projected orders, it could benefit not only itself but also related companies like SoftBank and Industrial Fulian [19] Industrial Fulian - Industrial Fulian is positioned to benefit from the AI-related capital expenditure cycle, particularly in its cloud service equipment segment, which is expected to see rapid growth in 2025 and 2026 [23][24] Market Dynamics - The energy consumption associated with AI development is rising sharply, with cabinet energy consumption projected to increase from 60 kW in 2022 to 120 kW in 2025, and potentially reaching 500 kW by 2027 [10] - New AI chip architectures are emerging, such as 3D stacking and RISC-V based designs, which could significantly impact the market landscape [11] Competitive Landscape - Google and NVIDIA have different approaches in the semiconductor solutions space, with Google utilizing over 9,000 TPUs, while NVIDIA focuses on GPUs [7] - TSMC and ASML are leading the global semiconductor technology landscape, with TSMC introducing GAA technology and ASML advancing EUV lithography [8] Investment Outlook - TSMC is expected to see annual profit growth of 25%-30% in the coming years, with an attractive valuation compared to its peers [4][22] - The semiconductor industry is anticipated to continue evolving, with significant opportunities for companies like TSMC and Industrial Fulian in the AI computing supply chain [25]

Group 1 - TSMC is actively investing in advanced packaging capacity in the U.S. as part of its strategy to strengthen the domestic semiconductor supply chain, with a total investment of $100 billion planned for new facilities [2][3] - TSMC's two advanced packaging plants, AP1 and AP2, will be located in Arizona and are expected to start construction in the second half of next year, with production anticipated to begin in 2028 [2][3] - AP1 will focus on SoIC (system-on-integrated-chips) technology, which utilizes 3D stacking to enhance data transfer speed and energy efficiency, while AP2 will specialize in CoPoS (Chip-on-Panel-on-Substrate) technology, improving production efficiency and supporting larger chip sizes [3] Group 2 - The acceleration of TSMC's advanced packaging deployment is closely related to supply chain security considerations, as the U.S. government encourages semiconductor production to return domestically through subsidies and tariffs [3][4] - Samsung Electronics is investing $37 billion in a 2nm advanced wafer fab in Texas, aiming to produce AI chips for Tesla, but is cautious about investing in advanced packaging due to unclear customer demand [4][5] - Samsung's current focus on producing Tesla's 2nm chips presents significant challenges, and the company may face excessive pressure if it simultaneously invests heavily in advanced packaging [5]

Core Viewpoint - TSMC is accelerating its expansion in the United States, planning to establish two advanced packaging plants (AP1, AP2) with construction expected to start in the second half of 2026 and operational by 2028, in response to local demand for AI and HPC chip packaging [2][3]. Group 1: Expansion Plans - TSMC's second wafer fab (P2) in the U.S. is set to introduce 2nm process technology earlier than initially planned, while the advanced packaging plants are located directly across from P3, with construction now expedited to 2026 [2][3]. - The company aims to build two new advanced packaging facilities and a research center in Arizona, enhancing the AI supply chain [2][3]. Group 2: Technology and Production - AP1 will incorporate SoIC and CoW technologies, while AP2 is focused on CoPoS, which is expected to mature by 2028 [3][4]. - SoIC is currently TSMC's most advanced packaging technology, already in mass production for clients like AMD, Apple, and NVIDIA [3][4]. Group 3: Investment and Market Impact - TSMC announced a $100 billion investment in the U.S., which includes the construction of three wafer fabs, two advanced packaging facilities, and a research center, marking the largest single foreign direct investment in U.S. history [6][7]. - The establishment of advanced packaging lines in the U.S. is driven by the needs of major clients such as Apple, NVIDIA, and AMD, with a focus on CoWoS and InFO technologies [6][8]. Group 4: Supply Chain Considerations - The construction of advanced packaging facilities requires a complete supply chain, including materials and testing capabilities, which may take at least four years to establish [7][8]. - TSMC's expansion in the U.S. could impact the existing packaging and testing supply chain in Taiwan, necessitating a mature ecosystem for testing and packaging [8][9].