Summary of Key Points from the Conference Call Industry Overview - The conference focused on the AI computing industry, highlighting the significant role of system vendors like NVIDIA and Google in shaping market trends, while TSMC and ASML are pivotal in providing technological platforms [1][2] - Silicon photonics technology emerged as a key topic, aimed at reducing energy consumption unrelated to computation, with large-scale commercialization expected by 2027 [1][2] Company Insights TSMC - TSMC is advancing steadily in its technology, with 2nm process expected to achieve mass production by 2025 and ongoing development of 3nm technology, enhancing its pricing power and customer profitability [1][3] - Under the Foundry 2.0 concept, TSMC's advanced packaging revenue is accelerating, with six operational factories and plans for four new ones, including expansions of CoWoS, SoIC, and CoPoS platforms [1][15] - TSMC's average selling price (ASP) has nearly doubled from $3,000 in 2019 to over $7,000 currently, driven by its technological advantages [13] - Future revenue growth for TSMC is heavily reliant on high-performance computing (HPC) clients, with a 70%-80% growth rate among these customers [16] - TSMC's capital expenditures have increased, with a peak in 2021 at 50% of revenue, but the pressure is expected to ease moving forward [21] Oracle - Oracle's capital expenditures have significantly increased, potentially linked to securing a large order from OpenAI, which could drive additional computing demand [3][19] - If Oracle executes on its projected orders, it could benefit not only itself but also related companies like SoftBank and Industrial Fulian [19] Industrial Fulian - Industrial Fulian is positioned to benefit from the AI-related capital expenditure cycle, particularly in its cloud service equipment segment, which is expected to see rapid growth in 2025 and 2026 [23][24] Market Dynamics - The energy consumption associated with AI development is rising sharply, with cabinet energy consumption projected to increase from 60 kW in 2022 to 120 kW in 2025, and potentially reaching 500 kW by 2027 [10] - New AI chip architectures are emerging, such as 3D stacking and RISC-V based designs, which could significantly impact the market landscape [11] Competitive Landscape - Google and NVIDIA have different approaches in the semiconductor solutions space, with Google utilizing over 9,000 TPUs, while NVIDIA focuses on GPUs [7] - TSMC and ASML are leading the global semiconductor technology landscape, with TSMC introducing GAA technology and ASML advancing EUV lithography [8] Investment Outlook - TSMC is expected to see annual profit growth of 25%-30% in the coming years, with an attractive valuation compared to its peers [4][22] - The semiconductor industry is anticipated to continue evolving, with significant opportunities for companies like TSMC and Industrial Fulian in the AI computing supply chain [25]

Group 1 - TSMC is actively investing in advanced packaging capacity in the U.S. as part of its strategy to strengthen the domestic semiconductor supply chain, with a total investment of $100 billion planned for new facilities [2][3] - TSMC's two advanced packaging plants, AP1 and AP2, will be located in Arizona and are expected to start construction in the second half of next year, with production anticipated to begin in 2028 [2][3] - AP1 will focus on SoIC (system-on-integrated-chips) technology, which utilizes 3D stacking to enhance data transfer speed and energy efficiency, while AP2 will specialize in CoPoS (Chip-on-Panel-on-Substrate) technology, improving production efficiency and supporting larger chip sizes [3] Group 2 - The acceleration of TSMC's advanced packaging deployment is closely related to supply chain security considerations, as the U.S. government encourages semiconductor production to return domestically through subsidies and tariffs [3][4] - Samsung Electronics is investing $37 billion in a 2nm advanced wafer fab in Texas, aiming to produce AI chips for Tesla, but is cautious about investing in advanced packaging due to unclear customer demand [4][5] - Samsung's current focus on producing Tesla's 2nm chips presents significant challenges, and the company may face excessive pressure if it simultaneously invests heavily in advanced packaging [5]

Core Viewpoint - TSMC is accelerating its expansion in the United States, planning to establish two advanced packaging plants (AP1, AP2) with construction expected to start in the second half of 2026 and operational by 2028, in response to local demand for AI and HPC chip packaging [2][3]. Group 1: Expansion Plans - TSMC's second wafer fab (P2) in the U.S. is set to introduce 2nm process technology earlier than initially planned, while the advanced packaging plants are located directly across from P3, with construction now expedited to 2026 [2][3]. - The company aims to build two new advanced packaging facilities and a research center in Arizona, enhancing the AI supply chain [2][3]. Group 2: Technology and Production - AP1 will incorporate SoIC and CoW technologies, while AP2 is focused on CoPoS, which is expected to mature by 2028 [3][4]. - SoIC is currently TSMC's most advanced packaging technology, already in mass production for clients like AMD, Apple, and NVIDIA [3][4]. Group 3: Investment and Market Impact - TSMC announced a $100 billion investment in the U.S., which includes the construction of three wafer fabs, two advanced packaging facilities, and a research center, marking the largest single foreign direct investment in U.S. history [6][7]. - The establishment of advanced packaging lines in the U.S. is driven by the needs of major clients such as Apple, NVIDIA, and AMD, with a focus on CoWoS and InFO technologies [6][8]. Group 4: Supply Chain Considerations - The construction of advanced packaging facilities requires a complete supply chain, including materials and testing capabilities, which may take at least four years to establish [7][8]. - TSMC's expansion in the U.S. could impact the existing packaging and testing supply chain in Taiwan, necessitating a mature ecosystem for testing and packaging [8][9].

Core Viewpoint - The emergence of CoWoP technology by Nvidia is seen as a potential disruptor to TSMC's CoWoS technology, which has been dominant in advanced packaging for AI chips. The industry is debating whether CoWoP is merely a temporary trend or a significant shift in semiconductor packaging [1][3]. Summary by Sections CoWoP vs CoWoS - CoWoP (Chip on Wafer on PCB) integrates the packaging substrate with PCB, allowing for a thinner, lighter, and higher bandwidth module design compared to CoWoS (Chip-on-Wafer-on-Substrate). This integration reduces material and manufacturing costs while accelerating production timelines [2][3]. Market Impact - The introduction of CoWoP has sparked discussions about its potential to replace CoWoS and has raised questions about the future of TSMC's CoPoS (Chip-on-Panel-on-Substrate) technology, which is designed to address CoWoS's production bottlenecks [3][4]. Advantages of CoWoP - CoWoP offers several advantages, including simplified system architecture, improved thermal management, reduced substrate costs, and potentially fewer backend testing steps. It aims to solve issues like substrate warping and enhance NVLink coverage without additional substrate layers [4][5]. Challenges and Risks - Despite its potential, CoWoP faces significant challenges in commercial viability, particularly in scaling up for high-capacity GPUs. The transition from existing technologies to CoWoP involves risks, especially given TSMC's current high yield rates with CoWoS [6][7]. Industry Sentiment - PCB manufacturers express skepticism about CoWoP's ability to replace CoWoS in the short term, citing the need for substantial advancements across the entire supply chain. They believe that existing technologies remain adequate and that the transition to CoWoP will take considerable time [7][8].

Summary of TSMC's CoWoS and Advanced Packaging Outlook Company and Industry Overview - **Company**: Taiwan Semiconductor Manufacturing Company (TSMC) - **Industry**: Semiconductor, specifically focusing on advanced packaging technologies such as CoWoS (Chip on Wafer on Substrate) and CoPoS (Chip-in-Panel-on-Substrate) Key Points and Arguments CoWoS Capacity and Growth Forecast - TSMC's total CoWoS capacity is projected to reach **675k** wafers per month (wpm) by the end of **2025**, with a forecast of **1.08 million** wpm by the end of **2026**, representing a **61%** year-over-year (YoY) growth [5][62] - The company anticipates further expansion to **130k** wpm by the end of **2027** [5][13] - CoWoS capacity has seen significant growth, with a **100%** YoY increase noted in early **2024** [11] Utilization Rate and Production Adjustments - TSMC's CoWoS utilization rate (UTR) is expected to be in the low **90s** in **1H26**, with a return to full capacity anticipated in **2H26** as new projects enter mass production [5][57] - Adjustments in nVidia's orders have led to a production mismatch, impacting the UTR and causing some expansion timelines to shift [5][50] Customer Allocation and Market Dynamics - nVidia is projected to maintain a **50.1%** market share in CoWoS capacity allocation for **2026**, slightly down from **51.4%** in **2025** [6][62] - Broadcom is expected to become the second-largest customer, with an allocation of **187k** wpm, benefiting from multiple projects entering mass production [62] Advanced Packaging Technologies - TSMC is focusing on several advanced packaging technologies, including CoWoS, CoPoS, and WMCM (Wafer-level Multiple-Chip Module), with CoPoS expected to enter high-volume production by **2028** [5][21][35] - CoWoS has evolved from a niche solution to a critical component in AI and high-performance computing (HPC), driven by the demand for larger memory bandwidth [10] Strategic Partnerships and Outsourcing - TSMC is collaborating with OSAT partners like ASE and SPIL to manage the increasing demand for CoWoS, with expectations that outsourcing will accelerate in **2026** and **2027** [40][42] - The company has invested significantly in expanding its advanced packaging capabilities, including a **US$100 billion** investment in the U.S. for new fabs and R&D centers [46] Challenges and Future Outlook - The semiconductor industry faces challenges such as production bottlenecks and mismatches between upstream and downstream production, which TSMC is actively addressing [52] - The demand for AI-related products is expected to remain strong, with TSMC's management indicating improved demand compared to previous forecasts [52] Conclusion - TSMC is positioned as a leader in the advanced packaging sector, with aggressive expansion plans and a strong customer base, particularly in the AI and HPC markets. The company's strategic partnerships and investments are expected to support its growth trajectory in the coming years [7][46]

Core Viewpoint - TSMC is significantly expanding its CoWoS capacity, with projections indicating a rise from 70k wpm at the end of 2025 to 100-105k wpm by the end of 2026, and further exceeding 130k wpm by 2027, showcasing a growth rate that outpaces the industry average [1][2]. Capacity Expansion - TSMC's CoWoS capacity will reach 675k wafers in 2025, 1.08 million wafers in 2026 (a 60% year-on-year increase), and 1.43 million wafers in 2027 (a 31% year-on-year increase) [1]. - The expansion is concentrated in specific factories, with the Tainan AP8 factory expected to contribute approximately 30k wpm by the end of 2026, primarily serving high-end chips for NVIDIA and AMD [2]. Utilization Rates - Due to order matching issues with NVIDIA, CoWoS utilization is expected to drop to around 90% from Q4 2025 to Q1 2026, with some capacity expansion plans delayed from Q2 to Q3 2026. However, utilization is projected to return to full capacity in the second half of 2026 with the mass production of new projects [4]. Customer Allocation - In 2026, NVIDIA is projected to occupy 50.1% of CoWoS capacity, down from 51.4% in 2025, with an allocation of approximately 541k wafers [5][6]. - AMD's CoWoS capacity is expected to grow from 52k wafers in 2025 to 99k wafers in 2026, while Broadcom's capacity is projected to reach 187k wafers, benefiting from the production of Google TPU and Meta V3 ASIC [5][6]. Technology Developments - TSMC is focusing on advanced packaging technologies such as CoPoS and WMCM, with CoPoS expected to be commercially available by the end of 2028, while WMCM is set for mass production in Q2 2026 [11][14]. - CoPoS technology offers higher yield efficiency and lower costs compared to CoWoS, while WMCM is positioned as a cost-effective solution for mid-range markets [12][14]. Supply Chain and Global Strategy - TSMC plans to outsource CoWoS backend processes to ASE/SPIL, which is expected to generate significant revenue growth for these companies [15]. - TSMC's aggressive investment strategy in the U.S. aims to establish advanced packaging facilities, enhancing local supply chain capabilities and addressing global supply chain restructuring [15]. AI Business Contribution - AI-related revenue for TSMC is projected to increase from 6% in 2023 to 35% in 2026, with front-end wafer revenue at $45.162 billion and CoWoS backend revenue at $6.273 billion, becoming a core growth driver [16].

Core Viewpoint - TSMC's CoWoS advanced packaging technology is experiencing a supply-demand imbalance, with a capacity utilization rate of only 60%, leading to supply chain disruptions [2][3] Group 1: Capacity Expansion Plans - TSMC plans to increase its CoWoS capacity by 33% by 2026, driven by strong demand for AI computing power [4][6] - The expansion will benefit the AI ASIC supply chain and companies like NVIDIA that rely heavily on advanced semiconductor technology [5][6] - The new facilities, including the AP8 wafer fab, will support various production lines, with a focus on AI applications [2][4] Group 2: Market Dynamics and Demand - Despite strong AI demand, there are indications that procurement of CoWoS equipment may slow down after existing orders are fulfilled [3][4] - The rapid expansion of TSMC's capacity may have outpaced actual demand, leading to potential adjustments in wafer production from clients like NVIDIA and AMD [2][3] - The semiconductor industry is witnessing increased investments to meet the growing demand for AI and high-performance computing solutions [6]

Core Viewpoint - The semiconductor packaging industry is experiencing a shift from CoWoS technology to emerging alternatives like CoPoS and FOPLP due to the limitations and challenges faced by CoWoS, particularly in terms of complexity, cost, and capacity constraints [1][36]. Group 1: CoWoS Technology Challenges - CoWoS packaging technology has become a focal point in the industry but is now facing significant challenges such as high production costs, yield control issues, and electrical performance limitations [1][36]. - The increasing size of AI GPU chips and the number of HBM stacks have led to bottlenecks in CoWoS, particularly due to photomask size limitations [4][36]. - TSMC has acknowledged these challenges and is positioning CoPoS as the next-generation successor to CoWoS, aiming to gradually replace CoWoS-L through technological iterations [4][9]. Group 2: CoPoS Technology Development - CoPoS technology represents a significant evolution from CoWoS by replacing the silicon interposer with a panel-sized substrate, allowing for larger packaging sizes and improved area utilization [6][8]. - CoPoS aims to enhance overall computational performance by integrating more semiconductors within a single package, thus improving yield efficiency and reducing edge waste [6][8]. - TSMC plans to establish a pilot line for CoPoS technology by 2026, with mass production targeted for late 2028 to 2029, with NVIDIA as the first customer [9][36]. Group 3: FOPLP Technology Emergence - FOPLP is emerging as a potential major alternative to CoWoS, leveraging the advantages of fan-out wafer-level packaging while utilizing panel-level substrates for enhanced size and utilization [10][13]. - The FOPLP market is projected to grow significantly, with a compound annual growth rate of 32.5%, reaching approximately $221 million by 2028 [14][36]. - Major industry players like ASE, Samsung, and others are actively investing in FOPLP technology, with ASE planning to establish a production line in Kaohsiung and Samsung already having a foothold in the panel-level packaging sector [11][18][19]. Group 4: CoWoP Technology Introduction - NVIDIA has proposed CoWoP technology, which simplifies the traditional packaging structure by integrating the chip directly onto the PCB, potentially reducing costs and improving performance [25][30]. - CoWoP aims to enhance signal integrity and power delivery while reducing thermal issues, but it faces significant technical challenges related to PCB manufacturing capabilities [30][36]. - The transition to CoWoP is seen as a long-term project for NVIDIA, with potential benefits including reduced costs and improved performance, although short-term adoption remains uncertain due to existing dependencies on traditional packaging methods [33][35].

Core Viewpoint - The semiconductor industry is experiencing a shift from CoWoS packaging technology to emerging alternatives like CoPoS and FOPLP due to the limitations and challenges faced by CoWoS, including high production costs and capacity bottlenecks [2][39]. Group 1: CoWoS Technology Challenges - CoWoS packaging technology has become a focal point due to the rise of AI and GPU chips, but it faces significant challenges such as complex processes, high production costs, and issues with yield control and testing [2][39]. - The increasing size of AI GPU chips and the number of HBM stacks have led to limitations in CoWoS, particularly due to photomask size constraints [6][39]. Group 2: CoPoS as an Evolution - CoPoS technology is seen as the next evolution of CoWoS, with TSMC positioning it as a successor that offers greater flexibility and economic benefits [4][6]. - CoPoS replaces the silicon interposer with a panel-sized substrate, allowing for larger packaging sizes and improved area utilization, which enhances production flexibility and scalability [8][11]. Group 3: FOPLP Technology Emergence - FOPLP is gaining traction as a potential major alternative to CoWoS, with its ability to support larger chip sizes and higher I/O density, making it suitable for AI and high-performance computing applications [12][14]. - The FOPLP market is projected to grow significantly, with a compound annual growth rate of 32.5%, reaching approximately $221 million by 2028 [18][21]. Group 4: Industry Players and Developments - Major companies like ASE, Samsung, and TSMC are actively investing in FOPLP technology, with ASE planning to establish a production line in Kaohsiung and Samsung having acquired PLP technology to support its development [22][23]. - TSMC is also advancing its FOPLP technology, with plans for a dedicated production line and initial trials expected to begin in 2026 [24][25]. Group 5: CoWoP Technology Introduction - CoWoP, proposed by NVIDIA, aims to simplify the packaging structure by integrating the chip directly onto the PCB, potentially reducing costs and improving performance [29][31]. - However, CoWoP faces significant challenges, including the need for high-precision PCB manufacturing and the risk of yield issues during the transition from existing technologies [35][37]. Group 6: Future Outlook - The semiconductor industry is currently balancing mature technologies like CoWoS with emerging solutions such as CoPoS, FOPLP, and CoWoP, which are expected to reshape the landscape as they mature [39].

Core Viewpoint - The article discusses the emergence of CoWoP (Chip-on-Wafer-on-PCB) technology as a potential alternative to CoWoS (Chip-on-Wafer-on-Substrate) and CoPoS (Chip-on-Panel-on-Substrate), highlighting its advantages and disadvantages in semiconductor packaging [1][12][14]. Summary by Sections CoWoS Overview - CoWoS involves a three-stage packaging process where dies are connected to an interposer, which is then connected to a packaging substrate, followed by cutting the wafer to form chips [7]. CoPoS Technology - CoPoS replaces the wafer with a panel, allowing for a higher number of chips to be accommodated, thus improving area utilization and production capacity [11]. Introduction of CoWoP - CoWoP eliminates the packaging substrate, allowing chips to be directly soldered onto the PCB, which simplifies the design and reduces costs [12][14]. Advantages of CoWoP - CoWoP reduces packaging costs by eliminating the expensive packaging substrate, leading to lower material costs and reduced complexity [14]. - It offers shorter signal paths, enhancing bandwidth utilization and reducing latency for high-speed interfaces like PCIe 6.0 and HBM3 [15]. - The absence of a packaging cover allows for better thermal management options, which is beneficial for high-power AI chips [15]. Disadvantages of CoWoP - The direct attachment to the PCB increases the requirements for PCB reliability and precision, as the tolerance for errors is significantly reduced [16]. - The lack of protective packaging raises concerns about reliability under thermal cycling, mechanical stress, and transport vibrations [16]. - Successful implementation requires close collaboration between chip packaging and PCB manufacturing from the design stage, increasing supply chain management complexity [16]. Conclusion - CoWoP technology is considered aggressive and presents significant challenges, indicating that it may not have an immediate impact on all PCB companies in the short term [17].