Summary of Investor Presentation on Greater China Technology Hardware: AI Tech Industry Overview - The presentation focuses on the Greater China Technology Hardware sector, particularly in AI technology hardware upgrades [4][5][6] - The overall industry view is categorized as "In-Line" [1] Core Insights and Arguments - **AI GPU and ASIC Server Upgrades**: There are significant opportunities in AI GPU and ASIC server/rack design upgrades, with major design upgrades anticipated for the GB300, Vera Rubin platform, and Kyber architecture [4][5] - **Enhanced Computing Power**: AI ASIC servers are expected to enhance computing power and increase rack density, with demand growth projected for 2026-2027 [4][5] - **Power Solutions**: Upgrades to 800V HVDC power architecture and the growing adoption of liquid cooling solutions are highlighted as key trends [4][5] - **PCB/Substrate Capacity Expansion**: A wave of capacity expansion in PCB/substrate is necessary to support ongoing design upgrades [4][5] - **Data Network Improvements**: Upgrades in data and power interconnects will lead to increased data network transmission speed and capacity [4][5] - **Consumer Electronics Demand**: Demand in consumer electronics remains lukewarm, with anticipation for upcoming foldable iPhone models in the second half of 2026 [4][5] - **AI PC Proliferation**: The proliferation of AI PCs is expected to take time, indicating a gradual market adoption [4][5] - **Supply Chain Reorientation**: The status of supply chain reorientation and its potential impacts are noted as important considerations [4][5] Key Stock Ideas - **AI Server Components**: Companies such as Delta Electronics, AVC, BizLink, King Slide, Chenbro, and Gold Circuits are identified as key players in AI server components [4][5] - **AI Server ODM/OEMs**: Wistron, Hon Hai/FII, Quanta, Lenovo, and Accton are highlighted as significant ODM/OEMs in the AI server space [4][5] Valuation Comparison - A detailed valuation comparison of various companies within the sector is provided, including metrics such as EPS, P/E ratios, P/B ratios, and trading volumes [5] - Notable companies include: - **Delta Electronics**: Closing price of 942.00 with a target of 1111.0 and a P/E ratio of 21.05 for 2025 [5] - **Hon Hai**: Closing price of 226.50 with a target of 250.0 and a P/E ratio of 13.83 for 2025 [5] - **Foxconn Tech**: Closing price of 70.60 with a target of 54.00 and a P/E ratio of 2.93 for 2025 [5] Additional Important Points - The report emphasizes the potential for share price upside in the context of the discussed upgrades and market trends [4][5] - The overall sentiment reflects cautious optimism regarding the future of AI technology hardware in Greater China, with specific attention to the evolving landscape of consumer electronics and server technology [4][5]

Core Viewpoint - The article discusses the transformative impact of AI on the PCB (Printed Circuit Board) industry, highlighting the expected market growth driven by advanced packaging technologies and increasing demand for high-performance computing [3][5][9]. Group 1: AI-Driven Growth in PCB Industry - The PCB industry is experiencing rapid growth due to the exponential increase in AI computing power, which is reshaping the industry landscape [5][6]. - The global PCB market is projected to exceed $78.6 billion by 2025, with AI servers, smart electric vehicles, and high-speed communication devices as the main growth drivers [5][6]. - The compound annual growth rate (CAGR) for PCBs used in AI servers is expected to reach 32.5%, significantly higher than the industry average [5][6]. Group 2: Technological Advancements and Requirements - The emergence of AI models has led to a surge in computing power demand, necessitating higher technical specifications for PCBs, particularly in terms of layer count and material selection [6][7]. - Advanced packaging technologies like CoWoP (Chip-on-Wafer-on-PCB) are being developed to enhance signal integrity and power efficiency, which will significantly impact the future of the PCB industry [14][15]. - The shift towards high-density interconnect (HDI) PCBs is driven by the need for high-frequency and high-speed data transmission, particularly in AI applications [6][10]. Group 3: Market Dynamics and Competitive Landscape - The AI PCB market is characterized by a concentration of high-end products, while the mid-to-low-end segments face intense competition due to lower entry barriers [16]. - Domestic companies in China are leading the AI PCB sector, benefiting from high demand and limited supply, while Japanese and Korean firms dominate the upstream materials market [16][17]. - The increasing value of AI server PCBs, which can rise from $500 to over $2,500, indicates a significant shift towards high-end PCB products [9][16]. Group 4: Capital Dynamics and Investment Trends - The PCB industry is witnessing a shift from scale expansion to high-end development, driven by innovations in 5G communication, AI computing, and automotive electronics [17]. - Investment activities in the PCB sector are primarily focused on upstream materials and equipment, with significant opportunities for growth [17][18]. - Recent financing events in the PCB sector indicate a growing interest in companies that can meet the rising demand for advanced PCB technologies [18][20].

Core Viewpoint - The emergence of CoWoP technology by Nvidia is seen as a potential disruptor to TSMC's CoWoS technology, which has been dominant in advanced packaging for AI chips. The industry is debating whether CoWoP is merely a temporary trend or a significant shift in semiconductor packaging [1][3]. Summary by Sections CoWoP vs CoWoS - CoWoP (Chip on Wafer on PCB) integrates the packaging substrate with PCB, allowing for a thinner, lighter, and higher bandwidth module design compared to CoWoS (Chip-on-Wafer-on-Substrate). This integration reduces material and manufacturing costs while accelerating production timelines [2][3]. Market Impact - The introduction of CoWoP has sparked discussions about its potential to replace CoWoS and has raised questions about the future of TSMC's CoPoS (Chip-on-Panel-on-Substrate) technology, which is designed to address CoWoS's production bottlenecks [3][4]. Advantages of CoWoP - CoWoP offers several advantages, including simplified system architecture, improved thermal management, reduced substrate costs, and potentially fewer backend testing steps. It aims to solve issues like substrate warping and enhance NVLink coverage without additional substrate layers [4][5]. Challenges and Risks - Despite its potential, CoWoP faces significant challenges in commercial viability, particularly in scaling up for high-capacity GPUs. The transition from existing technologies to CoWoP involves risks, especially given TSMC's current high yield rates with CoWoS [6][7]. Industry Sentiment - PCB manufacturers express skepticism about CoWoP's ability to replace CoWoS in the short term, citing the need for substantial advancements across the entire supply chain. They believe that existing technologies remain adequate and that the transition to CoWoP will take considerable time [7][8].

Group 1 - The core viewpoint is that the semiconductor industry is expected to experience a comprehensive recovery by 2025, with an improved competitive landscape and sustained profit recovery for related companies [1] - The SW electronic index increased by 1.65% over the past week (August 4-8), outperforming the CSI 300 index by 0.42 percentage points, with sub-sectors showing varied performance [1] - Recommendations for investment focus on semiconductor design companies with low PE/PEG ratios and real performance, including Zhongke Lanyun, Juxin Technology, Meixin Sheng, and Nanchip Technology [1] Group 2 - The CoWoP technology is emerging as the next-generation chip packaging solution, evolving from the current CoWoS technology, which is expected to benefit PCB manufacturing, material supply, and equipment sectors [2][4] - CoWoS technology, led by TSMC, addresses bandwidth and energy efficiency limitations, with a projected monthly capacity increase from 35,000-40,000 wafers in 2024 to 70,000-80,000 wafers in 2025 [3] - CoWoP's design eliminates the ABF substrate, enhancing power efficiency and heat dissipation, which is expected to create opportunities for PCB manufacturers and material suppliers [4]

Core Viewpoints - The AI boom is emerging, and CoWoP is expected to become the next-generation chip packaging technology, benefiting PCB manufacturing, material supply, and equipment sectors [3][6]. Market Review - In the past week (August 4-8), the SW Electronics Index rose by 1.65%, outperforming the CSI 300 Index by 0.42 percentage points. The performance of the six sub-sectors is as follows: Consumer Electronics (4.27%), Other Electronics II (4.06%), Electronic Chemicals II (2.70%), Optical Electronics (1.51%), Semiconductors (1.45%), and Components (-1.59%) [2]. CoWoS and CoWoP Technology - CoWoS, led by TSMC, is a 2.5D advanced packaging technology that overcomes traditional packaging limitations in bandwidth and energy efficiency. CoWoS types include CoWo-S, CoWoS-L, and CoWo-R, with CoWo-S being the most mature and suitable for current AI chip demands [4]. - CoWoP technology evolves from CoWoS, focusing on eliminating the ABF packaging substrate and directly bonding the silicon interposer to high-density PCBs [5][6]. CoWoP Advantages and Beneficiaries - CoWoP offers advantages such as reduced loss, improved NVLink coverage and stability, optimized power efficiency, and enhanced heat dissipation [6]. - Beneficiaries of the CoWoP supply chain include PCB manufacturers like Shenghong Technology, Shenzhen South Circuit, and Pengding Holdings, as well as material suppliers such as Honghe Technology and Fangbang Co., Ltd. [7]. Investment Recommendations - The electronic industry maintains an "overweight" rating, with expectations of a comprehensive recovery in the semiconductor sector by 2025. Companies with real performance and low PE/PEG ratios in semiconductor design, key materials, and the silicon carbide industry are recommended for attention [8].

Core Viewpoint - The semiconductor packaging industry is experiencing a shift from CoWoS technology to emerging alternatives like CoPoS and FOPLP due to the limitations and challenges faced by CoWoS, particularly in terms of complexity, cost, and capacity constraints [1][36]. Group 1: CoWoS Technology Challenges - CoWoS packaging technology has become a focal point in the industry but is now facing significant challenges such as high production costs, yield control issues, and electrical performance limitations [1][36]. - The increasing size of AI GPU chips and the number of HBM stacks have led to bottlenecks in CoWoS, particularly due to photomask size limitations [4][36]. - TSMC has acknowledged these challenges and is positioning CoPoS as the next-generation successor to CoWoS, aiming to gradually replace CoWoS-L through technological iterations [4][9]. Group 2: CoPoS Technology Development - CoPoS technology represents a significant evolution from CoWoS by replacing the silicon interposer with a panel-sized substrate, allowing for larger packaging sizes and improved area utilization [6][8]. - CoPoS aims to enhance overall computational performance by integrating more semiconductors within a single package, thus improving yield efficiency and reducing edge waste [6][8]. - TSMC plans to establish a pilot line for CoPoS technology by 2026, with mass production targeted for late 2028 to 2029, with NVIDIA as the first customer [9][36]. Group 3: FOPLP Technology Emergence - FOPLP is emerging as a potential major alternative to CoWoS, leveraging the advantages of fan-out wafer-level packaging while utilizing panel-level substrates for enhanced size and utilization [10][13]. - The FOPLP market is projected to grow significantly, with a compound annual growth rate of 32.5%, reaching approximately $221 million by 2028 [14][36]. - Major industry players like ASE, Samsung, and others are actively investing in FOPLP technology, with ASE planning to establish a production line in Kaohsiung and Samsung already having a foothold in the panel-level packaging sector [11][18][19]. Group 4: CoWoP Technology Introduction - NVIDIA has proposed CoWoP technology, which simplifies the traditional packaging structure by integrating the chip directly onto the PCB, potentially reducing costs and improving performance [25][30]. - CoWoP aims to enhance signal integrity and power delivery while reducing thermal issues, but it faces significant technical challenges related to PCB manufacturing capabilities [30][36]. - The transition to CoWoP is seen as a long-term project for NVIDIA, with potential benefits including reduced costs and improved performance, although short-term adoption remains uncertain due to existing dependencies on traditional packaging methods [33][35].

Core Viewpoint - The semiconductor industry is experiencing a shift from CoWoS packaging technology to emerging alternatives like CoPoS and FOPLP due to the limitations and challenges faced by CoWoS, including high production costs and capacity bottlenecks [2][39]. Group 1: CoWoS Technology Challenges - CoWoS packaging technology has become a focal point due to the rise of AI and GPU chips, but it faces significant challenges such as complex processes, high production costs, and issues with yield control and testing [2][39]. - The increasing size of AI GPU chips and the number of HBM stacks have led to limitations in CoWoS, particularly due to photomask size constraints [6][39]. Group 2: CoPoS as an Evolution - CoPoS technology is seen as the next evolution of CoWoS, with TSMC positioning it as a successor that offers greater flexibility and economic benefits [4][6]. - CoPoS replaces the silicon interposer with a panel-sized substrate, allowing for larger packaging sizes and improved area utilization, which enhances production flexibility and scalability [8][11]. Group 3: FOPLP Technology Emergence - FOPLP is gaining traction as a potential major alternative to CoWoS, with its ability to support larger chip sizes and higher I/O density, making it suitable for AI and high-performance computing applications [12][14]. - The FOPLP market is projected to grow significantly, with a compound annual growth rate of 32.5%, reaching approximately $221 million by 2028 [18][21]. Group 4: Industry Players and Developments - Major companies like ASE, Samsung, and TSMC are actively investing in FOPLP technology, with ASE planning to establish a production line in Kaohsiung and Samsung having acquired PLP technology to support its development [22][23]. - TSMC is also advancing its FOPLP technology, with plans for a dedicated production line and initial trials expected to begin in 2026 [24][25]. Group 5: CoWoP Technology Introduction - CoWoP, proposed by NVIDIA, aims to simplify the packaging structure by integrating the chip directly onto the PCB, potentially reducing costs and improving performance [29][31]. - However, CoWoP faces significant challenges, including the need for high-precision PCB manufacturing and the risk of yield issues during the transition from existing technologies [35][37]. Group 6: Future Outlook - The semiconductor industry is currently balancing mature technologies like CoWoS with emerging solutions such as CoPoS, FOPLP, and CoWoP, which are expected to reshape the landscape as they mature [39].

Summary of Key Points from the Conference Call Industry Overview - The discussion centers around the semiconductor packaging industry, specifically focusing on NVIDIA Corporation (NVDA) and its proposed technology shift from CoWoS (Chip-on-Wafer-on-Substrate) to CoWoP (Chip-on-Wafer-on-PCB) packaging technology [1][2]. Core Insights and Arguments 1. **CoWoP Technology Proposal**: NVDA is considering replacing CoWoS with CoWoP, which utilizes advanced PCB technologies like mSAP and SLP to enhance performance by eliminating the ABF substrate layer [1]. 2. **Potential Benefits of CoWoP**: - Simplified system structure leading to reduced transmission losses and improved NVLink interconnect range [1]. - Enhanced thermal management and lower power consumption [1]. - Decreased substrate costs, which have been increasing with each generation [1]. - Possible reduction in backend testing steps [1]. 3. **Commercialization Challenges**: The likelihood of CoWoP being commercialized in the medium term is assessed as low due to significant technological hurdles, including the need for finer line/space dimensions and the current limitations of PCB technology [2]. 4. **Current Roadmap Conflicts**: NVDA's established roadmap, which includes CoWoS-L and CoPoS, appears contradictory to the new direction of CoWoP, indicating a potential preference for more mature technologies [2]. 5. **Supply Chain Implications**: If CoWoP is adopted, it could negatively impact ABF substrate players as the value add from substrates may diminish, while PCB makers with advanced capabilities could benefit [7][8]. 6. **Testing and Foundry Impact**: CoWoP may alter the testing landscape by reducing the number of testing steps but could increase demand for board-level testing, which may lead to a shift in testing equipment spending [11][12]. Additional Important Insights 1. **Market Participation**: There is limited participation from high-value packaging players like TSMC in the CoWoP development, which may hinder its commercialization prospects [5]. 2. **Material Considerations**: The high current and voltage requirements of PCBs may exclude certain materials, suggesting that improved versions of mSAP will likely be used for platform PCBs [9][10]. 3. **Investment Requirements**: Significant investments in clean rooms, automation, and lithography tools will be necessary for the successful implementation of CoWoP, indicating a high barrier to entry for new players [8]. 4. **NVIDIA's Leadership**: Regardless of the success of CoWoP, NVDA is positioned as a leader in datacenter AI infrastructure, continuing to innovate in packaging technologies and system-level approaches [13]. Companies Discussed - **NVIDIA Corporation (NVDA)**: Focused on advanced packaging technologies and AI infrastructure [20]. - **TSMC**: Noted for its limited engagement in the CoWoP technology development [12]. - **ABF Material Vendors**: Companies like Ajinomoto and Ibiden may face negative impacts from the shift to PCB-based technologies [7]. - **PCB Manufacturers**: Unimicron is highlighted as a strong player due to its involvement in advanced PCB technologies [8][10]. This summary encapsulates the key points discussed in the conference call, providing insights into the potential shifts in the semiconductor packaging landscape and the implications for various stakeholders.

Core Viewpoint - Morgan Stanley reports that Nvidia is exploring a revolutionary chip packaging technology called CoWoP (Chip-on-Wafer-on-PCB), which is expected to replace the existing CoWoS packaging solution [4][5]. Group 1: CoWoP Technology Overview - CoWoP utilizes advanced high-density PCB technology to eliminate the ABF substrate layer found in CoWoS packaging, directly connecting the intermediary layer to the PCB [5][9]. - The potential advantages of CoWoP include simplified system architecture, improved thermal management, lower power consumption, and reduced substrate costs [18][20]. Group 2: Supply Chain Impact - The introduction of CoWoP is seen as negative news for ABF substrate manufacturers, as the added value of substrates may significantly decrease or disappear [14]. - Conversely, PCB manufacturers are presented with significant opportunities, as the technology shift may lead to increased demand for advanced PCB capabilities [15][6]. Group 3: Commercialization Challenges - Despite the potential benefits, Morgan Stanley analysts believe that the commercialization probability of CoWoP in the medium term remains low due to multiple technical challenges [7][17]. - Current PCB technologies, even with mSAP, can only achieve line/space widths of 20-30 microns, which is still far from the desired performance levels [20]. Group 4: Nvidia's Innovation Leadership - Regardless of the success of CoWoP, Nvidia continues to lead innovations in data center AI infrastructure through a system-level approach [23][24]. - Nvidia's ongoing exploration of CoWoS-L and CoPoS technologies, along with its potential leadership in large-scale CPO applications, is expected to maintain its competitive edge in the GPU market [24].

Core Viewpoint - The recent surge in interest around the semiconductor supply chain is driven by NVIDIA's proposal to use CoWoP (Chip-on-Wafer-on-PCB) technology as a potential replacement for CoWoS packaging technology, leveraging advanced high-density PCB techniques to simplify system structure and improve efficiency [5][9]. Group 1: CoWoP Technology Overview - CoWoP is defined as a method where the chip is directly mounted onto the PCB after the intermediary layer is manufactured, eliminating the need for the ABF substrate used in CoWoS [8]. - The potential advantages of CoWoP include simplified system architecture, reduced transmission losses, improved data transfer efficiency, enhanced thermal management, and lower substrate costs [9][10]. Group 2: Commercial Viability of CoWoP - The likelihood of CoWoP achieving commercial viability in the medium term is considered low due to several technical challenges, including the need for finer line widths and pitches that current PCB technologies cannot meet [11]. - The existing technology roadmap of NVIDIA, which focuses on CoWoS-L and CoPoS, conflicts with the new direction of CoWoP, further complicating its adoption [11][12]. Group 3: Impacts on the Semiconductor Supply Chain - If CoWoP is successfully implemented, it could shift complex signal routing to the re-routing layer, potentially reducing the value of ABF substrate manufacturers while benefiting PCB manufacturers through increased revenue from advanced PCB specifications [15]. - The balance between high-speed performance and the demands for high current/voltage in platform PCBs presents significant challenges, with companies like Unimicron positioned favorably due to their experience in both PCB and substrate technologies [16]. Group 4: Effects on Testing and Manufacturing - CoWoP may reduce the number of final and system-level testing steps, shifting towards board-level testing, although achieving high yield rates is critical for this transition [18]. - The impact on wafer foundries and OSATs is expected to be minimal, as the chip-on-wafer process remains largely unchanged, but the lack of involvement from major players like TSMC raises concerns about the technology's success [19].