Group 1 - The report indicates that the external uncertainty from tariffs is expected to gradually spread, with the U.S. "reciprocal tariffs" 90-day deadline approaching, suggesting that most economies may struggle to resolve tariff issues within this timeframe [4][13][15] - The domestic policy is anticipated to remain proactive yet restrained, with the need to maintain sufficient policy space to address potential extreme risk scenarios while avoiding excessive short-term stimulus that could disrupt long-term goals [30][32][38] Group 2 - The report highlights that the improvement in domestic demand is a key driver for economic and corporate profit recovery, with expectations that consumer confidence will continue to rise due to the rebound in residents' income and wealth effects [77][78][83] - The real estate sector is showing signs of gradual recovery, with new home sales and land transaction data improving, indicating a potential positive impact on the overall economy [83][88][91] Group 3 - The report emphasizes that the capital market's liquidity remains high, with a significant number of stocks experiencing substantial gains, which has fostered a strong investment sentiment among individual investors [116][122][134] - The importance of the equity market is underscored by ongoing policy support aimed at enhancing residents' property income and maintaining market stability [136]

Core Viewpoint - Micron Technology presented its latest 3D NAND flash technology, the ninth generation (G9), at the 2025 IEEE International Memory Workshop, highlighting significant advancements in storage density and data transfer speeds while maintaining the same storage capacity per chip as the previous generation [1]. Summary by Sections G9 3D NAND Flash Technology - The G9 3D NAND flash has a storage capacity of 1 Tbit per chip, the same as the G8, but with a 40% increase in storage density of the memory cell array and a 30% increase in chip storage density [1]. - The maximum data transfer speed of G9 has improved by 1.5 times compared to G8 [1]. - The number of word line layers in G9 is 276, only a 19% increase from the 232 layers in G8, indicating that innovations beyond just increasing layer count contributed to the density improvements [1]. Storage Density Improvements - The storage density of Micron's memory cell array increased from 17 Gbit/mm² in G7 to 25 Gbit/mm² in G8, and further to 35 Gbit/mm² in G9 [3]. - Innovations include the removal of virtual pillars, which reduced block height by approximately 14%, and a decrease in the number of page buffers from 16 in G8 to 6 in G9, halving the page buffer's chip area [3]. Future Technology Challenges - The future of 3D NAND flash technology, including G10 and beyond, will face increasing technical challenges, akin to climbing an infinitely long spiral staircase [5]. - The introduction of "Confined SN" technology aims to reduce interference between adjacent cells, resulting in a 10% reduction in programming time and a 50% decrease in coupling capacitance between adjacent cells [9]. Innovations and Solutions - The G9 stack height exceeds 13 μm, with a layer height of 6.5 μm, and a high aspect ratio of over 43 due to the small diameter of storage holes [7]. - To mitigate electrical interference, Micron introduced air gaps in the insulation film and limited the nitrogen film to the gate side of the cell transistors [7][8]. - The transition from charge trapping to ferroelectric polarization is proposed as a solution to reduce the risk of dielectric breakdown, which is critical as the number of layers increases [16]. Cost and Performance Considerations - Micron is exploring wafer bonding technology to optimize the performance of peripheral circuits and memory cell arrays, despite the initial increase in costs associated with wafer bonding [12]. - The cost of wafer bonding is expected to decrease with each new technology generation, potentially becoming more cost-effective than single-chip manufacturing in the future [12][14].

Core Viewpoint - Samsung Electronics presented the evolution of next-generation DRAM and NAND flash memory at the "IMW 2025" event, highlighting advancements in memory density and architecture [1][10]. DRAM Evolution - The evolution of DRAM units has transitioned from planar n-channel MOS FETs in the 1990s to advanced structures that mitigate short-channel effects and leakage currents. The area of DRAM units has been reduced from "8F2" to "6F2," achieving a 25% reduction in unit area while maintaining the same processing dimensions [1][3]. - The current 10nm generation DRAM units maintain the "6F2" layout but are expected to shift to a "4F2" layout in the next generation, referred to as "0A" generation, due to limitations in maintaining the existing structure [3][5]. 3D DRAM Development - Samsung is exploring 3D DRAM technology, which involves vertically stacking longer DRAM units to increase memory capacity. This approach aims to enhance memory density significantly [7][9]. NAND Flash Memory Evolution - NAND flash memory has evolved from planar structures to 3D configurations, allowing for increased charge storage and reduced interference between adjacent cells. The number of stacked layers in 3D NAND has grown from 32 layers in the early 2010s to over 300 layers by the mid-2020s, significantly increasing density and capacity [11][13]. - Challenges similar to those faced by planar NAND persist, including difficulties in etching deeper holes for unit string channels and increased interference due to reduced spacing between storage holes. Innovations such as using ferroelectric films in charge trap cells are being explored to mitigate these issues [14][17]. Future Innovations - Various companies and experts shared advancements in memory technologies, including imec's pure metal gate technology for 3D NAND reliability and NEO Semiconductor's 3D X-DRAM technology, which resembles 3D NAND structures [18][19].

Group 1: DRAM Evolution - Samsung Electronics reviewed the evolution of DRAM units, highlighting the transition from planar n-channel MOS FETs in the 1990s to advanced structures in the 21st century due to short-channel effects and leakage currents [1][3] - The layout of DRAM unit arrays improved in the 2010s, reducing unit area from "8F2" to "6F2," achieving a 25% reduction in area while maintaining the same processing dimensions [1][3] - The next generation of DRAM, referred to as "0A" (below 10nm), is expected to shift from the "6F2" layout to a "4F2" layout, indicating a significant change in design [3][4] Group 2: 3D DRAM Development - Samsung is exploring 3D DRAM technology, which involves vertically stacking longer DRAM units to increase memory capacity [6][8] - The prototype of 3D DRAM, known as "VS-CAT," demonstrates the potential for increased density and reduced silicon area by stacking storage unit arrays above peripheral circuits [8][12] Group 3: NAND Flash Memory Evolution - NAND flash memory has reached the limits of density and miniaturization, prompting a shift from planar NAND to 3D NAND technology, which significantly increases charge storage capacity and reduces interference between adjacent units [10][12] - The number of stacked layers in 3D NAND has increased from 32 layers in the early 2010s to over 300 layers by the mid-2020s, enhancing memory density [12][14] - Challenges similar to those faced by planar NAND persist in 3D NAND, including difficulties in etching deeper holes for unit string channels and increased interference due to reduced spacing between storage holes [12][13] Group 4: Ferroelectric Film Applications - The introduction of ferroelectric films in NAND flash memory units aims to reduce programming voltage and suppress threshold voltage fluctuations, which can help mitigate interference between cells [14][16] - The use of ferroelectric films allows for multi-value storage capabilities, increasing the number of threshold voltage levels from two to eight or sixteen [14][16] Group 5: Future Technologies and Innovations - Various companies and experts shared advancements in DRAM and NAND technologies, including imec's pure metal gate technology and NEO Semiconductor's 3D X-DRAM technology [18][19] - Innovations in ferroelectric memory and resistive memory technologies were also discussed, showcasing ongoing efforts to enhance performance and reliability in semiconductor storage solutions [19][20]

来源：内 容 编译自 pcwatch ，谢谢。 如果您希望可以时常见面，欢迎标星收藏哦~ 自旋轨道扭矩结构和磁各向异性的设计技术。 参考链接 https://pc.watch.impress.co.jp/docs/column/semicon/2010780.html 2025年的IEEE国际存储器研讨会（IMW）是半导体存储器技术研发的国际会议即将隆重召开。届 时，将会有很多领先的存储技术发布。 据介绍，Kioxia 将报告具有 CBA（CMOS 直接键合到阵列）结构的 3D NAND 闪存的交叉位线 (CBL) 架构。相信这可以解释为什么通过晶圆键合堆叠外围电路和存储单元阵列的CBA结构在位 线布局方面具有优势。 三星则描述了具有非圆形通道孔形状的多孔 VNAND 闪存架构的阈值电压建模。美光公司模拟了 椭圆度（想象"孔形"）对 3D NAND 读取窗口边缘的影响。在最新的研究中，人们尝试通过将通 道孔的横截面形状制成椭圆形或半圆形而不是圆形来提高密度。这些声明被视为这一努力的一部 分。 旺宏电子国际公司（MXIC）开发了一种用于3D堆叠外围电路的垂直通道高压晶体管，以使1,000 层和超多层3D NAN ...

国芯网[原:中国半导体论坛] 振兴国产半导体产业！ 不拘中国、 放眼世界 ！ 关注 世界半导体论坛 ↓ ↓ ↓ 4月27日消息，近日，出品"六个核桃"的养元饮品披露一则对外投资公告，公司控制的芜湖闻名泉 泓投资管理合伙企业（有限合伙）（下称"泉泓投资"）以货币出资方式对长江存储科技控股有限责 任公司（下称"长控集团"）增资人民币16亿元！ 长江存储是一家半导体存储器研发商，是专注于3D NAND闪存设计制造一体化的IDM集成电路企 业，同时也提供完整的存储器解决方案。 河北养元智汇饮品股份有限公司（养元饮品）始建于1997年，专注植物蛋白饮料核桃乳的研发、生 产和销售业务。在 河北衡水、安徽滁州、江西鹰潭、河南漯河、四川简阳设有生产加工基地，是国 内产销规模领先的核桃乳企业。六个核桃是企业代表性产品。 根据公告，投资方出资人民币16亿元认购标的公司新增注册资本。本次投资款应用于标的公司的业务运 营和发展，包括但不限于预期业务扩展、资本支出和补充一般营运资金。 对于投资的目的，养元饮品称，本次投资能够推动公司探索股权投资的商业运营模式。在短期内对公司 经营成果不会构成重大影响，长期有利于增强公司的投资能力，更好 ...

如果您希望可以时常见面，欢迎标星收藏哦~ 今天下午，上市公司河北养元智汇饮品股份有限公司对外发布公告称，公司投资了长江存储 科技控股有限责任公司（以下简称"长控集团"或"标的公司"）。公告指出，本次投资金额为 人民币 16 亿元。本次交易完成后，公司控制的芜湖闻名泉泓投资管理合伙企业（有限合 伙）（以下简称"泉泓投资"）持有长控集团0.99%的股份。 据企查查消息透露，本次的被投标的是"长江存储科技控股有限责任公司"法人为陈南翔，旗下公 司包括长江存储科技有限责任公司、武汉新芯集成电路股份有限公司以及宏茂微等一系列子公 司。其中长江存储科技有限责任公司就是我们平时俗称的"长江存储"，也就是国内3D NAND的 唯一供应商。 至于本次被投标的是其母公司。换而言之，我们不能通过这个投资金额和在公司中的股份占比粗 暴计算"长江存储"的估值。而在引入了包括河北养元智汇饮品股份有限公司及一系列的新股东之 后，"长控集团"股东更多元化，为"长江存储"后续的发展打开了一个新局面。 官网资料显示，长江存储科技有限责任公司成立于2016年7月，总部位于"江城"武汉，是一家集 芯片设计、生产制造、封装测试及系统解决方案产品于一体 ...

Core Viewpoint - The article discusses the advancements and challenges in 3D NAND flash memory technology, particularly focusing on the innovations in etching processes that enhance storage density and production efficiency [2][19][24]. Group 1: 3D NAND Technology Overview - 3D NAND technology has become the mainstream architecture for NAND flash memory, significantly improving storage density and reducing production costs [1][5]. - The transition from 2D NAND to 3D NAND has seen a dramatic increase in the number of layers, with projections of exceeding 1000 layers in the future [11][42]. - The unit bit density of NAND technology has improved by over one million times since its inception [5][6]. Group 2: Etching Technology Developments - Recent innovations in etching technology, particularly the development of a new etching process by Lam Research and partners, have doubled the etching speed and improved precision [2][19]. - Traditional reactive ion etching (RIE) methods face challenges such as slow etching speeds and precision issues, prompting the need for more efficient etching techniques [10][12]. - The introduction of low-temperature etching technologies has shown to enhance etching speed by 2.5 times and reduce energy consumption by 40% [22][35]. Group 3: Challenges in 3D NAND Manufacturing - As the number of layers in 3D NAND increases, manufacturers face significant challenges in maintaining etching speed and consistency, particularly in achieving high aspect ratio (HAR) structures [7][40]. - The complexity of the manufacturing process increases with the number of layers, leading to higher production costs and reliability issues [12][40]. - Environmental concerns are also pressing, with the need for sustainable practices in etching technology to reduce energy consumption and emissions [17][40]. Group 4: Future Outlook - The market for semiconductor etching equipment is projected to grow significantly, with estimates reaching $28.73 billion by 2029, reflecting a compound annual growth rate (CAGR) of 5.3% [42]. - Major players in the NAND flash market, including Samsung and Kioxia, are actively pursuing the development of 1000-layer 3D NAND technology, indicating a competitive landscape [39][42]. - Continuous innovation in etching technology is essential for meeting the increasing demands for high-density storage solutions in the AI and big data era [32][24].

Core Viewpoint - The article discusses the evolution and future of alternative and persistent memory technologies, highlighting the competition among various types of memory to become mainstream in the semiconductor industry [2][3][6]. Group 1: Historical Context - For the past 40 years, semiconductor memory has evolved from SRAM, DRAM, EPROM, and EEPROM to include newer technologies like FRAM, MRAM, ReRAM, and PCM [2][3]. - NAND flash memory has been a cornerstone of non-volatile storage, but it faces limitations at the 15nm node, leading to the development of 3D NAND variants [7][8]. Group 2: Current Developments - Recent advancements in memory technologies include the emergence of microcontrollers utilizing MRAM and FRAM, with companies like NXP and Texas Instruments leading the way [6][10]. - The collaboration between NXP and TSMC aims to develop MRAM-based microcontrollers for the automotive market in 2023 [6]. Group 3: Challenges and Limitations - The transition to alternative memory technologies faces economic challenges, as the costs associated with these new technologies are currently higher than traditional NAND and DRAM [8][10]. - The integration of new memory types into existing systems is complicated by the need for additional on-chip SRAM, which increases costs and complexity [5][10]. Group 4: Future Predictions - Experts predict that it may take around ten years for alternative memory technologies to replace flash and SRAM in embedded applications due to slow development in microcontroller technology [10]. - The transition to alternative memory in external NAND flash chips and SDRAM is expected to be delayed, but once it begins, it may accelerate quickly [10].