Summary of TSMC's CoWoS and Advanced Packaging Outlook Company and Industry Overview - **Company**: Taiwan Semiconductor Manufacturing Company (TSMC) - **Industry**: Semiconductor, specifically focusing on advanced packaging technologies such as CoWoS (Chip on Wafer on Substrate) and CoPoS (Chip-in-Panel-on-Substrate) Key Points and Arguments CoWoS Capacity and Growth Forecast - TSMC's total CoWoS capacity is projected to reach **675k** wafers per month (wpm) by the end of **2025**, with a forecast of **1.08 million** wpm by the end of **2026**, representing a **61%** year-over-year (YoY) growth [5][62] - The company anticipates further expansion to **130k** wpm by the end of **2027** [5][13] - CoWoS capacity has seen significant growth, with a **100%** YoY increase noted in early **2024** [11] Utilization Rate and Production Adjustments - TSMC's CoWoS utilization rate (UTR) is expected to be in the low **90s** in **1H26**, with a return to full capacity anticipated in **2H26** as new projects enter mass production [5][57] - Adjustments in nVidia's orders have led to a production mismatch, impacting the UTR and causing some expansion timelines to shift [5][50] Customer Allocation and Market Dynamics - nVidia is projected to maintain a **50.1%** market share in CoWoS capacity allocation for **2026**, slightly down from **51.4%** in **2025** [6][62] - Broadcom is expected to become the second-largest customer, with an allocation of **187k** wpm, benefiting from multiple projects entering mass production [62] Advanced Packaging Technologies - TSMC is focusing on several advanced packaging technologies, including CoWoS, CoPoS, and WMCM (Wafer-level Multiple-Chip Module), with CoPoS expected to enter high-volume production by **2028** [5][21][35] - CoWoS has evolved from a niche solution to a critical component in AI and high-performance computing (HPC), driven by the demand for larger memory bandwidth [10] Strategic Partnerships and Outsourcing - TSMC is collaborating with OSAT partners like ASE and SPIL to manage the increasing demand for CoWoS, with expectations that outsourcing will accelerate in **2026** and **2027** [40][42] - The company has invested significantly in expanding its advanced packaging capabilities, including a **US$100 billion** investment in the U.S. for new fabs and R&D centers [46] Challenges and Future Outlook - The semiconductor industry faces challenges such as production bottlenecks and mismatches between upstream and downstream production, which TSMC is actively addressing [52] - The demand for AI-related products is expected to remain strong, with TSMC's management indicating improved demand compared to previous forecasts [52] Conclusion - TSMC is positioned as a leader in the advanced packaging sector, with aggressive expansion plans and a strong customer base, particularly in the AI and HPC markets. The company's strategic partnerships and investments are expected to support its growth trajectory in the coming years [7][46]

Core Viewpoint - TSMC is significantly expanding its CoWoS capacity, with projections indicating a rise from 70k wpm at the end of 2025 to 100-105k wpm by the end of 2026, and further exceeding 130k wpm by 2027, showcasing a growth rate that outpaces the industry average [1][2]. Capacity Expansion - TSMC's CoWoS capacity will reach 675k wafers in 2025, 1.08 million wafers in 2026 (a 60% year-on-year increase), and 1.43 million wafers in 2027 (a 31% year-on-year increase) [1]. - The expansion is concentrated in specific factories, with the Tainan AP8 factory expected to contribute approximately 30k wpm by the end of 2026, primarily serving high-end chips for NVIDIA and AMD [2]. Utilization Rates - Due to order matching issues with NVIDIA, CoWoS utilization is expected to drop to around 90% from Q4 2025 to Q1 2026, with some capacity expansion plans delayed from Q2 to Q3 2026. However, utilization is projected to return to full capacity in the second half of 2026 with the mass production of new projects [4]. Customer Allocation - In 2026, NVIDIA is projected to occupy 50.1% of CoWoS capacity, down from 51.4% in 2025, with an allocation of approximately 541k wafers [5][6]. - AMD's CoWoS capacity is expected to grow from 52k wafers in 2025 to 99k wafers in 2026, while Broadcom's capacity is projected to reach 187k wafers, benefiting from the production of Google TPU and Meta V3 ASIC [5][6]. Technology Developments - TSMC is focusing on advanced packaging technologies such as CoPoS and WMCM, with CoPoS expected to be commercially available by the end of 2028, while WMCM is set for mass production in Q2 2026 [11][14]. - CoPoS technology offers higher yield efficiency and lower costs compared to CoWoS, while WMCM is positioned as a cost-effective solution for mid-range markets [12][14]. Supply Chain and Global Strategy - TSMC plans to outsource CoWoS backend processes to ASE/SPIL, which is expected to generate significant revenue growth for these companies [15]. - TSMC's aggressive investment strategy in the U.S. aims to establish advanced packaging facilities, enhancing local supply chain capabilities and addressing global supply chain restructuring [15]. AI Business Contribution - AI-related revenue for TSMC is projected to increase from 6% in 2023 to 35% in 2026, with front-end wafer revenue at $45.162 billion and CoWoS backend revenue at $6.273 billion, becoming a core growth driver [16].

Core Viewpoint - TSMC's CoWoS advanced packaging technology is experiencing a supply-demand imbalance, with a capacity utilization rate of only 60%, leading to supply chain disruptions [2][3] Group 1: Capacity Expansion Plans - TSMC plans to increase its CoWoS capacity by 33% by 2026, driven by strong demand for AI computing power [4][6] - The expansion will benefit the AI ASIC supply chain and companies like NVIDIA that rely heavily on advanced semiconductor technology [5][6] - The new facilities, including the AP8 wafer fab, will support various production lines, with a focus on AI applications [2][4] Group 2: Market Dynamics and Demand - Despite strong AI demand, there are indications that procurement of CoWoS equipment may slow down after existing orders are fulfilled [3][4] - The rapid expansion of TSMC's capacity may have outpaced actual demand, leading to potential adjustments in wafer production from clients like NVIDIA and AMD [2][3] - The semiconductor industry is witnessing increased investments to meet the growing demand for AI and high-performance computing solutions [6]

Investment Rating - The report assigns an "Overweight" rating to TSMC with a price target of NT$1,275.0 by December 2025 [2][28]. Core Insights - TSMC is expected to maintain strong structural growth drivers due to its near-monopoly position in AI accelerators and edge AI, supported by a robust process roadmap and industry-leading packaging technology [28]. - The report anticipates a significant ramp-up in TSMC's wafer-level multichip module (WMCM) capacity, particularly for high-end iPhone models, which could lead to substantial revenue growth [5][11]. - CoWoS (Chips-on-Wafer-on-Substrate) capacity is projected to remain tight through the second half of 2025 but is expected to reach a more balanced situation by the second half of 2026 [3][4]. Summary by Sections CoWoS Capacity and Demand - TSMC's CoWoS capacity is expected to grow significantly, reaching 102,000 wafers per month (wfpm) by the end of 2027, with a growth rate of 138% in 2025 [3]. - NVIDIA's CoWoS demand is projected to grow by 25% in 2026, reaching 538,000 units, driven by the migration to the Rubin platform [4][9]. - Overall CoWoS consumption is forecasted to increase from 679,000 wafers in 2025 to 1,132,000 wafers in 2027, reflecting a year-on-year growth of 32% [9]. WMCM Capacity and Adoption - WMCM capacity is expected to reach 27,000 wfpm by the end of 2026 and ramp up to 40,000 wfpm by the end of 2027, driven by Apple’s adoption in high-end iPhone models [5][11]. - If all iPhones were to migrate to WMCM long-term, this would require approximately 90,000 wfpm of WMCM capacity, indicating a significant expansion plan [5]. Customer Demand and Projections - Broadcom is expected to see steady growth in CoWoS consumption, particularly for Google TPUs, while new customers like Meta are anticipated to ramp up in 2026 [4]. - AMD's CoWoS forecasts remain muted for 2025 and 2026, with potential growth expected in the MI450 series in late 2026 and beyond [4]. - The report highlights that the CoWoS ecosystem is maturing, with more non-AI processors beginning to adopt CoWoS packaging, indicating broader market adoption [4]. Future Outlook - TSMC's structural growth is expected to be supported by price hikes on leading-edge nodes and a strong ramp-up of N2 technology in 2026 [28]. - The report suggests that TSMC will likely raise its FY25 USD revenue guidance, alleviating concerns regarding gross margin impacts from overseas expansion and currency fluctuations [28].

Core Viewpoint - The article provides an analysis of TSMC's CoWoS and WMCM technologies, focusing on customer demand, capacity forecasts, and investment outlooks, particularly in the semiconductor industry [1]. Customer Demand Analysis - For NVIDIA, JP Morgan forecasts a 25% increase in CoWoS demand by 2026, reaching 58% market share, driven by the migration to the Rubin platform, which will increase package size by 50% [2]. - AMD's CoWoS demand is expected to be weak in 2025 and 2026 due to restrictions on the MI300 series in the Chinese market, but there is optimism for the MI400 series in late 2026 and 2027 [3]. - Broadcom is projected to see stable growth in ASIC demand, particularly from Google TPU, with Meta expected to start mass production of its CoWoS-based AI accelerator in 2025 [4][5]. Capacity and Technology Analysis - TSMC's CoWoS capacity is expected to stabilize by 2027, with a slight slowdown in expansion plans due to reduced GPU demand in China [10]. - By 2026, CoWoS-L is anticipated to account for 64% of TSMC's total CoWoS output, driven by more customers migrating to this technology [13]. - WMCM technology is simpler than CoWoS and is expected to significantly expand, with production capacity projected to reach 27,000 wafers per month by the end of 2026 and 40,000 by the end of 2027 [15]. Overall Consumption Forecast - Total CoWoS consumption is projected to grow from 134,000 wafers in 2023 to 1,132,000 wafers by 2027, reflecting a compound annual growth rate of 32% [11]. - NVIDIA's CoWoS consumption is expected to increase significantly, with projections of 705,000 wafers by 2027, while AMD's consumption will remain modest [11]. - The overall market for CoWoS is expected to see a shift towards CoWoS-L, with a majority of customers adopting this technology by 2025 [11][12].

Core Viewpoint - TSMC's CoPoS packaging technology is gaining attention in the market, with plans for its first production line set to be established by 2026 and large-scale production expected between late 2028 and 2029, with NVIDIA as the first customer [1][2] Group 1: CoPoS Technology Development - TSMC's CoPoS is a variant of the CoWoS technology, designed to optimize space and reduce costs, with dimensions of 310x310 mm [1] - The focus of CoPoS packaging will be on advanced applications such as AI, with specific processes targeting companies like Broadcom, NVIDIA, and AMD [1][2] Group 2: Production Timeline and Facilities - TSMC's AP7 facility in Chiayi is planned to have eight phases, with CoPoS expected to achieve large-scale production in phase P4 [2] - The AP7 site is strategically chosen for its larger area and advanced technology, allowing for the integration of multiple packaging technologies [2] Group 3: Future Production and Technology Integration - The timeline for CoPoS includes equipment testing starting mid-next year, with small-scale production anticipated in 2027, followed by process validation and large-scale production by the end of 2028 [2] - TSMC aims to provide optimal solutions by integrating various technologies such as SoIC, CoWoS, and CoPoS for HPC chip packaging below 2nm [2]