人工智能的发展正在重塑全球科技与产业格局，自2017年深度学习突破以来，AI从实验室走向产业 前线，并在过去几年随着大模型的崛起，迅速成为全球国家战略的核心支柱。当前的AI竞争，早已 超越了算法本身，演化为以"国家为单位"的全要素体系竞争，涵盖芯片制造、算力基础设施、人才 流动、资本投入。 中国和美国显然是这场竞争的主轴。美国依托其科技公司主导的创新体系，在大模型、AI芯片方面 持续领先全球；我国则依托强大的工业基础，和国内庞大的AI人才群体，跟美国的差距越来越小； 与此同时，欧盟、日本、韩国、印度、以色列、阿联酋等国家和地区也纷纷出台AI国家战略，试图 在全球标准制定、数据治理和行业应用中占据一席之地。 最近Google、Meta和微软都出了财报，业绩都非常炸裂，而之所以营收和净利都大幅增长，几乎都 是因为AI驱动公司的某个业务带来的增长，这也让他们会在AI上增加更多的资本开支，星球中放过 多个关于Google\Meta\微软的分析，有兴趣的朋友可以到星球查看。 这篇文章的内容我们参考的是Jefferies的一篇分析，关于全球AI的竞争格局，更多的是对美国AI政 策的解析。 美国虽然在AI人才、资本和模型创 ...

说四点关于这件事的看法。 以下文章来源于More Than Semi ，作者猫叔 More Than Semi . More Than SEMI 半导体行业研究 新闻大家应该都已经看到了： 根据"半导体综研"关老师的数据（为了不引起各方的误会，把具体型号隐去了），可以看到，国内 很多厂家的GPU算力都已经远超过H20，而在软件适配方面，虽然没有CUDA那么好用，但据笔者了 解，有几家公司的GPU/NPU产品都已经在CSP用起来了。 | 厂商 | 名称 | 发布时间 | FP32 | TF32 | BF16/FP16 | INT8 | FP8 | INT4 | FP4 | 功耗(W) | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | | NVIDIA | H20 | 2023 | 40 | 74 | 148 | 296 | 296 | | | 400 | | | | 2024 | | | 781 | | | | | | | 华为 | | 2023 | 128 | | 376 | 640 | | | | 310 | | | ...

| Spec | 说明 | | --- | --- | | 接口协议 | 支持 Ethernet 和 InfiniBand | | 网络端口 | 2 个端口，每个支持最高 200Gb/s，总带宽最高 400Gb/s | | 接口技术 | NRZ (10G, 25G)、PAM4 (50G, 100G) | | 主机接口 | PCIe Gen 5，最多支持 32 条通道（支持 x16 加扩展） | | 网卡形态 | PCIe HHHL (half-height, half-length) | | 操作系统支持 | Linux (RHEL、Ubuntu)、Windows、VMware ESXi、Kubernetes 等 | 在数据中心和AI计算场景中，英伟达的ConnectX-7网卡现在真的是一卡难求，而且也是价格不菲。 ConnectX-7网卡的核心参数如下： XPU-316 标卡具有良好的兼容性，支持 Linux、CGSL、欧拉、龙蜥等操作系统，兼容 X86 及 ARM CPU。XPU- 316 为标准 PCIe 插卡，适用于通用、智算服务器。 XPU-316 标卡可广泛用于公有云、私有云、边缘云以及智算中心的 ...

Core Viewpoint - The semiconductor industry has experienced significant growth, with global semiconductor device sales projected to reach $617.9 billion by 2024, a 162-fold increase since 1977, outpacing global GDP growth [1][3]. Summary by Sections Industry Phases - Phase 1 (1977-1994): The semiconductor industry experienced explosive growth as it filled market demand gaps [5]. - Phase 2 (1995-2009): The market reached saturation, with semiconductor sales growth aligning closely with GDP growth, stabilizing around 0.45% of GDP [5]. - Phase 3 (2010 onwards): The emergence of smartphones and mobile internet led to renewed growth, with an average annual growth rate of approximately 6% [6]. Characteristics Driving Growth - The semiconductor industry serves as the foundation for the information sector, with increasing data generation driving demand for chips [6]. - The existence of Moore's Law ensures continuous performance improvements in chips, fostering rapid technological advancements that benefit the entire semiconductor supply chain [6]. Current Market Dynamics - The semiconductor industry is currently in a phase driven by artificial intelligence (AI), marking the beginning of a fourth growth stage [10]. - The demand for high-performance computing chips has surged due to AI advancements, leading to increased average prices despite stable wafer output [10][14]. Future Outlook - The AI sector is expected to provide long-term growth opportunities for the semiconductor industry, similar to the mobile communications boom [14]. - The anticipated explosion in data generation from AI applications will significantly increase the demand for various types of chips [16].

Core Viewpoint - The article discusses the emergence of CoWoP (Chip-on-Wafer-on-PCB) technology as a potential alternative to CoWoS (Chip-on-Wafer-on-Substrate) and CoPoS (Chip-on-Panel-on-Substrate), highlighting its advantages and disadvantages in semiconductor packaging [1][12][14]. Summary by Sections CoWoS Overview - CoWoS involves a three-stage packaging process where dies are connected to an interposer, which is then connected to a packaging substrate, followed by cutting the wafer to form chips [7]. CoPoS Technology - CoPoS replaces the wafer with a panel, allowing for a higher number of chips to be accommodated, thus improving area utilization and production capacity [11]. Introduction of CoWoP - CoWoP eliminates the packaging substrate, allowing chips to be directly soldered onto the PCB, which simplifies the design and reduces costs [12][14]. Advantages of CoWoP - CoWoP reduces packaging costs by eliminating the expensive packaging substrate, leading to lower material costs and reduced complexity [14]. - It offers shorter signal paths, enhancing bandwidth utilization and reducing latency for high-speed interfaces like PCIe 6.0 and HBM3 [15]. - The absence of a packaging cover allows for better thermal management options, which is beneficial for high-power AI chips [15]. Disadvantages of CoWoP - The direct attachment to the PCB increases the requirements for PCB reliability and precision, as the tolerance for errors is significantly reduced [16]. - The lack of protective packaging raises concerns about reliability under thermal cycling, mechanical stress, and transport vibrations [16]. - Successful implementation requires close collaboration between chip packaging and PCB manufacturing from the design stage, increasing supply chain management complexity [16]. Conclusion - CoWoP technology is considered aggressive and presents significant challenges, indicating that it may not have an immediate impact on all PCB companies in the short term [17].

Core Insights - Google Gemini's daily active users (DAU) are significantly lower than ChatGPT, yet its token consumption is six times higher than that of Microsoft, primarily driven by search products rather than the Gemini chat feature [3][7][8]. User Metrics - As of March 2025, ChatGPT has over 800 million monthly active users (MAU) and 80 million DAU, while Gemini has approximately 400 million MAU and 40 million DAU [6][8]. - The DAU/MAU ratio for both ChatGPT and Gemini stands at 0.1, indicating similar user engagement levels [6]. Token Consumption - In Q1 2025, Google’s total token usage reached 634 trillion, compared to Microsoft’s 100 trillion [8]. - Google’s token consumption for Gemini in March 2025 was about 23 trillion, accounting for only 5% of its overall token usage [7][8]. - Each MAU for both ChatGPT and Gemini consumes approximately 56,000 tokens monthly, suggesting comparable user activity levels [8]. Financial Impact - Google’s cost for processing these tokens in Q1 2025 was approximately $749 million, representing 1.63% of its operating expenses, which is manageable compared to traditional search costs [8]. - Barclays predicts that Google will require around 270,000 TPU v6 chips to support current token processing demands, with quarterly chip spending expected to rise from $600 million to $1.6 billion [8].

Core Viewpoint - The article discusses the CPO (Co-Packaged Optics) industry chain participants, highlighting the differences between the traditional optical transceiver supply chain and the emerging CPO ecosystem, which integrates silicon semiconductor supply chains and requires upgrades to key components and manufacturing equipment [1][2]. Traditional Optical Transceivers - The traditional optical transceiver supply chain consists of epitaxial wafers, optical components, DSP suppliers, and module manufacturers, dominated by companies like Coherent, Lumentum, and Broadcom [2][3]. CPO Value Chain - The CPO value chain includes various components such as epitaxial wafers, fibers, optical engines, and assembly/testing services, with notable suppliers like TSMC, ASE/SPIL, and Broadcom playing critical roles [4]. Wafer Foundries - Wafer foundries are expected to be foundational for CPO development, with TSMC's COUPE platform likely becoming a key entry point for potential customers seeking CPO solutions [5][8]. - TSMC is collaborating with companies like Broadcom and Nvidia on CPO transceivers, while other foundries like Intel and GlobalFoundries are also targeting the silicon photonics market [8][9]. FAU (Fiber Array Unit) - FAUs are critical components in the CPO supply chain, with TSMC planning to integrate them directly into optical engines [10]. - FOCI is positioned to partner with TSMC due to its high-temperature resistant FAU technology, which is essential for integration into the COUPE platform [10]. Assembly, Packaging, and Testing - Companies like ASE and SPIL are expected to play significant roles in the CPO supply chain due to their expertise in packaging and assembly processes [11]. - Testing is crucial for CPO components, requiring stricter quality control compared to traditional optical transceivers [11]. Equipment Manufacturers - Equipment manufacturers like BESI and ASMPT are poised to benefit from the demand for hybrid bonding equipment driven by CPO developments [14][15]. - GPTC is expected to provide cleaning tools for EIC and PIC stacking, with unique equipment tailored for CPO production [15]. Industry Information Exchange - The article mentions the availability of industry information and analysis reports through platforms like Knowledge Planet, which aims to keep stakeholders updated on market developments [17].

Core Viewpoint - The article discusses the transition from copper cables to optical fibers in data center networks, emphasizing the advantages of optical technology, particularly CPO (Co-Packaged Optics), in supporting next-generation AI servers and addressing the challenges of mass production [2][11]. Group 1: Advantages of Optical Fiber over Copper - Optical fibers offer significantly higher bandwidth, capable of supporting 800G, 1.6T, and above, making them suitable for high-speed interconnect scenarios [3][5]. - The transmission speed of optical fibers is approximately two-thirds the speed of light, which reduces latency and enhances response times in data centers [3]. - Optical fibers can transmit data over much longer distances, with single-mode fibers reaching up to 100 kilometers, compared to copper cables, which typically support less than 10 meters for high-speed transmission [3][4]. - Optical fibers are more reliable, less affected by environmental factors and electromagnetic interference, ensuring stable data transmission in high-power environments like AI data centers [3][4]. - The space efficiency of optical fibers is superior, being thinner, lighter, and more robust, allowing for greater bandwidth in a smaller footprint [3]. Group 2: CPO Technology and Its Importance - CPO technology is identified as a key advancement for next-generation AI servers, integrating optical components directly into the packaging of ASIC/xPU chips, which enhances energy efficiency and bandwidth density [11][15]. - The CPO roadmap indicates a trend towards reducing the distance between optical engines and ASICs, with the industry currently in the commercialization phase of on-board optics [12]. - CPO significantly reduces signal loss and latency by shortening the transmission path between ASICs and optical devices from several centimeters to just a few millimeters [15]. - CPO can lower power consumption by up to 70% compared to traditional optical modules, as it minimizes the need for high-power digital signal processors [15]. Group 3: Challenges in CPO Mass Production - The complexity of packaging technology, including advanced techniques like hybrid bonding and 2.5D/3D packaging, poses challenges for ensuring system reliability and yield management [28]. - There are concerns regarding the performance of silicon-based photonic integrated circuits (PICs) compared to traditional modules using indium phosphide (InP) [28]. - Durability and thermal management are critical, as all optical components are tightly packaged within the ASIC/xPU system, requiring them to withstand high temperatures [28]. - Reliability issues arise from the close integration of optical engines with ASICs, where a single failure could jeopardize the entire high-cost system [28]. Group 4: Future Adoption and Market Trends - The adoption of CPO technology in switches is expected to occur around 2027-2028, particularly as the demand for higher bandwidth solutions increases [30]. - Major companies like Broadcom and NVIDIA are already developing their CPO solutions, indicating a competitive landscape for this technology [31][35]. - The transition of xPU systems to CPO is anticipated to be slower due to higher integration complexity and thermal management challenges, but it could lead to significant market growth in the long term [40].

Core Viewpoint - The article discusses the impact of recent restrictions on AI chip sales in China, particularly focusing on the market dynamics for Nvidia and local manufacturers, and the projected growth of the AI accelerator market in the coming years [2][3]. Group 1: Market Projections - Bernstein estimates that the Chinese AI accelerator market will reach $39.5 billion by 2025, primarily driven by Nvidia H20 ($22.9 billion), AMD MI308 ($2 billion), and local manufacturers ($14.6 billion) [2]. - Following the sales ban, Nvidia is expected to lose $1.68 billion in H20 sales, while AMD may lose $150 million, with some orders shifting to local manufacturers, potentially increasing their revenue by about 10% [2]. - Despite local manufacturers' growth, Bernstein believes they cannot fully cover the $18.3 billion gap due to production bottlenecks in 7nm wafers and CoWoS technology [2]. Group 2: Nvidia's Strategy - Nvidia plans to apply for the resumption of H20 sales and introduce a compliant NVIDIA RTX PRO GPU, with initial demand projected at $10.5 billion, although it will not meet the initial demand of $16.8 billion [2][3]. - The anticipated shipment of B30 chips to China is expected to reach 400,000 units, generating $2.8 billion in revenue, while local manufacturers may only gain an additional $1.5 billion due to new restrictions [3]. Group 3: Competitive Landscape - Major cloud service providers in China, including ByteDance, Alibaba, Tencent, and Baidu, are the primary buyers of H20, accounting for 87% of total sales [5]. - By 2027, local manufacturers are projected to capture 55% of the market share, while global competitors may face technological stagnation and lose their competitive edge [3]. Group 4: Supply and Demand Dynamics - The article highlights discrepancies between GPU shipment data from Bernstein and IDC, noting that Huawei holds a 23% market share, while Nvidia's share is overstated by IDC by 7 percentage points [16][20]. - The supply-demand relationship indicates that aside from Alibaba and Baidu, other major companies are purchasing Huawei's AI chips, raising questions about the accuracy of reported data [23]. Group 5: Local Manufacturers - The report identifies local GPU manufacturers, with Huawei leading the market, followed by Cambricon, Haiguang, and Tianshu [20][21]. - The revenue of local manufacturers is expected to increase significantly, with Moore Threads projected to boost its revenue through substantial AI computing GPU shipments in 2024 [36][38].

More Than SEMI 半导体行业研究 以下文章来源于More Than Semi ，作者猫叔 More Than Semi . 内容比较长，我们简单总结一下： NVIDIA 的 GPU 发展呈现出明显的周期，从早期图形渲染的固定流水线 DSA 架构，到为解决负载不均 衡问题发展出统一 Shader 架构和 SIMT 抽象，再到 AI 时代引入 Tensor Core 重新走向 DSA 化，期间通 过 CUDA 生态的不断优化维持了行业地位。而国内大厂 Ascend 则从系统级统一角度出发，针对异构架 构导致的生态碎片化问题，提出了同构 ISA 和混合执行模型，还设计了统一总线（UB）来打破资源孤 岛，试图实现 CPU、GPU、NPU 等的编程统一和高效互连。 最近几天关于某大厂从NPU转向GPGPU的讨论非常多，但网上充斥着太多无脑的解读，首先推荐大家 看一篇专业的解读：作者是渣总。 https://mp.weixin.qq.com/s/iqRXwdHjyMI7egMrXEIfFw SIMT 和 SIMD 两种架构各有优劣，SIMT 在编程灵活性上更具优势，适合处理稀疏数据和复杂控制 流，而 SIMD ...