Core Viewpoint - Advanced packaging has become a critical battleground for foundries and packaging companies amid the slowdown of Moore's Law and the explosive demand for AI/HPC solutions. Major players globally, including TSMC, Samsung, ASE, and domestic firms like JCET, Tongfu Microelectronics, and Huatian Technology, are accelerating capacity expansion to seize this key industry opportunity in the coming years [1]. Group 1: Market Trends and Projections - The global advanced chip packaging market is expected to grow from $50.38 billion in 2025 to $79.85 billion by 2032, with a compound annual growth rate (CAGR) of 6.8% [1]. - The demand for high-performance, low-power packaging solutions is driven by AI large models, autonomous driving, cloud computing, and edge computing [1]. Group 2: TSMC's Strategy and Expansion - TSMC's advanced packaging revenue is projected to exceed 10% in 2024, surpassing ASE to become the largest packaging supplier globally, driven by the surge in CoWoS demand [3]. - TSMC plans to invest an additional $100 billion in the U.S., including two advanced packaging plants in Arizona, expected to start construction in the second half of next year and enter mass production by 2028 [5]. - TSMC is set to launch CoWoS-L in 2026 and SoW-X in 2027, enhancing its capabilities significantly in the AI/HPC era [6]. Group 3: Samsung's Cautious Approach - Samsung has adopted a more cautious stance compared to TSMC, previously shelving a $7 billion advanced packaging facility due to uncertain customer demand [7]. - Recent contracts with Tesla and Apple highlight the necessity for Samsung to reconsider its advanced packaging investments [7][8]. - Samsung's integrated model of "memory + foundry + packaging" positions it well for future demand once customer needs become clearer [8]. Group 4: ASE's Expansion and Technological Advancements - ASE is enhancing its advanced packaging capabilities in Kaohsiung, focusing on CoWoS, SoIC, and FOPLP technologies [9]. - ASE's new K18B factory in Kaohsiung will serve AI and HPC demands, while the K28 factory will expand CoWoS testing capacity [9][10]. - ASE's technology evolution includes advancements in 3D Advanced RDL technology, which is crucial for various applications [10][11]. Group 5: Amkor's U.S. Investment - Amkor is expanding its advanced packaging facility in Peoria, Arizona, with a total investment of $2 billion, expected to create over 2,000 jobs [13]. - The new facility will primarily support TSMC's CoWoS and InFO technologies, establishing a local closed-loop for wafer manufacturing and packaging [14]. - Amkor's expansion aligns with U.S. semiconductor policies, emphasizing the need for a complete backend capability to maintain competitiveness in AI and HPC [14]. Group 6: Domestic Players' Development - JCET, Tongfu Microelectronics, and Huatian Technology are rapidly advancing in the advanced packaging sector, each developing unique strategies [15]. - JCET is focusing on various advanced packaging technologies and plans to invest 8.5 billion yuan in 2025, targeting high-performance applications [16][17]. - Tongfu Microelectronics has deepened its partnership with AMD, becoming its largest packaging supplier, and is making significant progress in large-size FCBGA technology [18][19]. - Huatian Technology is exploring CPO technology and has achieved significant growth in revenue, indicating a shift towards system integration in advanced packaging [20][21].

Summary of TSMC's SiC Strategy and Industry Insights Industry and Company Overview - The document focuses on TSMC (Taiwan Semiconductor Manufacturing Company) and its strategy regarding Silicon Carbide (SiC) in the context of advanced packaging and AI chip demands [1][2][3] - Other companies mentioned include NVIDIA, AMD, Google, and AWS, highlighting the competitive landscape in AI and HPC (High-Performance Computing) [22][60] Core Insights and Arguments 1. Challenges in AI Chip Design - The increasing complexity and power demands of AI chips have made traditional power delivery methods inadequate, leading to issues like IR drops and transient voltage droops [5][6] - Single GPUs now require over 1000A of current, pushing legacy power delivery systems to their limits [6][22] 2. Innovative Solutions - Foundries and OSAT providers are proposing solutions like Marvell's PIVR and ASE's VIPack to optimize power delivery and thermal performance [8][9] - TSMC's CoWoS-L platform integrates IVRs and eDTCs to enhance power stability and reduce voltage drop [12][13] 3. SiC's Role in Advanced Packaging - SiC is emerging as a critical material for high-voltage ICs and on-chip power delivery, supporting developments in BSPDN and IVR architectures [19][20] - Its unique properties, such as high thermal conductivity and mechanical strength, position SiC as a key enabler for thermal management and optical interconnects [21][51] 4. Market Dynamics - The demand for ultra-large-scale GPUs and ASICs is driving the need for advanced materials and packaging solutions [22][23] - TSMC is exploring SiC as an interposer material to meet the increasing bandwidth and power demands of AI/HPC packaging [61] 5. Competitive Landscape - TSMC's advancements in SiC could provide a competitive edge over Intel and Samsung, who are also investing in power delivery and packaging technologies [60][61] - The introduction of SiC substrates into TSMC's platforms could reshape the AI semiconductor supply chain [59] Additional Important Insights 1. Bottlenecks in Process and Packaging Technologies - The document identifies three critical bottlenecks: thermal challenges, power delivery bottlenecks, and electro-optical integration demands [26][33][35] - TSMC is addressing these through diversified packaging solutions and exploring next-gen silicon photonics [38][39] 2. Future Directions - The integration of SiC into TSMC's advanced packaging platforms like COUPE could redefine the industry's approach to thermal, electrical, and optical challenges [59] - The document emphasizes the importance of overcoming challenges related to defect density, process compatibility, and cost structure for SiC adoption [66][67] 3. SiC in Optical Applications - SiC is also highlighted for its potential in optical waveguides, particularly for AR glasses, due to its high refractive index and thermal conductivity [68][75] - The combination of SiC with Micro LED technology is seen as a promising pathway for future AR displays [77] 4. Research and Development - Ongoing research is focused on the feasibility of integrating SiC with TSV structures to enhance power integrity and thermal management [64][65] - TSMC's patent portfolio indicates a strong commitment to SiC integration in advanced packaging technologies [65] This comprehensive analysis underscores TSMC's strategic focus on SiC as a transformative material in the semiconductor industry, particularly in the context of AI and HPC advancements.

Core Viewpoint - Advanced packaging has become a critical battleground for wafer foundries and packaging companies, driven by the slowing of Moore's Law and the explosive demand for AI and HPC solutions. Major players globally are accelerating capacity expansion to seize this key industry opportunity [2]. Group 1: Market Trends - The global advanced chip packaging market is expected to grow from $50.38 billion in 2025 to $79.85 billion by 2032, with a compound annual growth rate (CAGR) of 6.8% [2]. - The demand for high-performance, low-power packaging solutions is being fueled by AI large models, autonomous driving, cloud computing, and edge computing [2]. Group 2: TSMC's Strategy - TSMC's advanced packaging revenue is projected to exceed 10% in 2024, surpassing ASE to become the largest packaging supplier globally [4]. - TSMC is investing $100 billion in the U.S. to build three wafer foundries and two advanced packaging plants, with plans to start construction in the second half of next year [6]. - TSMC's advanced packaging technologies include InFO for mobile/HPC chips, CoWoS for logic-HBM integration, and SoW for wafer-level AI systems [4][6]. Group 3: Samsung's Position - Samsung is taking a more cautious approach to advanced packaging, having previously shelved a $7 billion investment plan due to uncertain customer demand [7]. - Recent contracts with Tesla and Apple highlight the necessity for Samsung to reconsider its advanced packaging investments [7][8]. - Samsung's integrated model of "memory + foundry + packaging" is seen as advantageous in the AI era, positioning it to restart large-scale advanced packaging initiatives once customer demand stabilizes [8]. Group 4: ASE's Developments - ASE is enhancing its advanced packaging capabilities in Kaohsiung, focusing on high-end capacities like CoWoS and SoIC [9]. - ASE's new facilities and technology advancements aim to create a flexible multi-package platform to meet diverse customer needs in the AI/HPC wave [10]. Group 5: Amkor's Expansion - Amkor is expanding its advanced packaging facility in Arizona, increasing its land area and total investment to $2 billion, with a focus on high-performance advanced packaging [12]. - The new facility will support TSMC's CoWoS and InFO technologies, crucial for Nvidia and Apple's latest chips [13][14]. Group 6: Domestic Players - Chinese packaging companies like JCET, Tongfu Microelectronics, and Huada Semiconductor are rapidly advancing in the global advanced packaging landscape [16]. - JCET is investing in various advanced packaging technologies and has launched the XDFOI® series for high-density heterogeneous integration [17]. - Tongfu Microelectronics has deepened its partnership with AMD, becoming its largest packaging supplier and achieving significant progress in large-size FCBGA technology [18]. - Huada Semiconductor is exploring CPO packaging technology and has completed various advanced packaging techniques [20]. Group 7: Future Outlook - The focus of competition is shifting from "nano-process" to "system integration," with the U.S. aiming to establish a comprehensive capability in both front-end manufacturing and back-end packaging [22]. - Domestic OSAT companies are transitioning from a "filling" role to a "breakthrough" role, with the potential to compete with international players in specific niches [22].

Core Viewpoint - The semiconductor industry is transitioning into the "post-Moore era," where traditional scaling methods are becoming less effective due to physical limits and rising costs. Advanced packaging technologies are emerging as a key focus area, driven by the demand for AI chips requiring high performance and low latency [1]. Industry Overview - The global advanced packaging market is projected to exceed $79.4 billion by 2030, with a compound annual growth rate (CAGR) of 9.5% from 2024 to 2030, primarily fueled by AI and high-performance computing demands [1]. - Major players in the advanced packaging sector include TSMC, Intel, and Samsung, each adopting unique competitive strategies to dominate the high-end packaging market [1]. TSMC's Advanced Packaging Strategy - TSMC leads the advanced packaging market with its "3D Fabric" platform, which includes CoWoS, InFO, and SoIC technologies, covering various application scenarios [2]. - The CoWoS technology has evolved to its fifth generation, supporting high-density integration and significantly enhancing memory bandwidth for high-performance computing applications [5]. - InFO technology focuses on cost-sensitive applications, enabling low-cost, thin packaging solutions, while SoIC technology allows for true 3D chip stacking [6][10]. Intel's Advanced Packaging Approach - Intel is developing its advanced packaging capabilities through EMIB and Foveros technologies, targeting high-performance computing and AI markets [7]. - EMIB technology connects bare chips using silicon bridges, while Foveros enables vertical stacking of chips, enhancing flexibility and performance [10]. Samsung's Advanced Packaging Innovations - Samsung is advancing its packaging technologies with I-Cube and X-Cube systems, addressing both 2.5D and 3D IC packaging needs [11]. - The I-Cube technology integrates logic chips and HBM on the same interposer, while the X-Cube technology enhances system integration through vertical electrical connections [12][13]. - Samsung is also focusing on SoP (System on Panel) technology, which aims to challenge TSMC's dominance in high-end AI chip packaging by offering larger integration spaces and lower costs [14][16]. Domestic Players in Advanced Packaging - Chinese companies are making strides in the advanced packaging sector, with a projected market size of 69.8 billion yuan in 2024, driven by firms like Changjiang Electronics Technology, Tongfu Microelectronics, and Huatian Technology [17]. - Changjiang Electronics is recognized as a leader in advanced packaging, leveraging its XDFOI Chiplet platform to support high-density interconnections [18]. - Tongfu Microelectronics has established a strong position through collaborations with AMD, focusing on AI and HPC advanced packaging [20]. - Huatian Technology is expanding its capabilities in advanced packaging through significant R&D investments and partnerships [22]. Future Outlook - The global advanced packaging market is expected to reach $56.9 billion by 2025, surpassing traditional packaging for the first time, with domestic firms poised to capture more market share [32]. - The ongoing development of AI computing chips and the trend towards self-sufficiency in high-end advanced packaging present significant opportunities for domestic players to narrow the gap with international leaders [32].

Group 1 - SEMICON Taiwan 2025 will focus on AI, CoWoS advanced packaging, and testing mass production progress from September 10-12 [1] - The semiconductor industry is facing bottlenecks in process miniaturization, with heterogeneous integration and advanced packaging emerging as breakthrough directions [1] - Demand for AI, high-performance computing (HPC), and HBM is increasing, making advanced packaging technologies like 3D IC and panel-level fan-out packaging core to semiconductor innovation [1] Group 2 - TSMC's CoWoS, InFO, and SoIC advanced packaging technologies are applicable for AI and HPC chips, with CoWoS already in mass production [1] - NVIDIA and AMD have strong ongoing demand for CoWoS, while Apple requires TSMC's InFO technology for high-end processors [1] - TSMC is expanding its CoWoS and InFO advanced packaging lines in the U.S. due to strong demand and U.S. government support for domestic semiconductor manufacturing [1] Group 3 - TSMC announced a $100 billion investment in advanced semiconductor manufacturing in the U.S., totaling $165 billion, which includes two advanced packaging facilities [2] - TSMC aims to balance the supply-demand gap for CoWoS advanced packaging, with expected monthly capacity exceeding 90,000 to 95,000 pieces by the end of 2026 [2] - Non-TSMC CoWoS capacity is projected to reach 12,000 pieces monthly by the end of next year, with nearly 60% of overall annual capacity still supplied to NVIDIA [2]

Core Viewpoint - Amkor Technology is set to build a $2 billion advanced packaging and testing facility in Peoria, Arizona, expected to begin production in early 2028, marking a significant step in the U.S. semiconductor supply chain [2][3] Group 1: Facility and Investment - The new facility will occupy 104 acres and aims to address the bottleneck in semiconductor packaging, which has been a limiting factor for companies like Nvidia in producing AI chips [2] - The project received approval from the Peoria City Council on August 29, with plans modified to utilize a larger site in the city's innovation core [2] Group 2: Industry Context - The facility represents a major shift in the U.S. semiconductor landscape, as it aims to catch up with the advanced packaging capabilities predominantly held by Taiwan and South Korea [2] - Amkor's new plant will support high-performance packaging platforms, including TSMC's CoWoS and InFO technologies, which are critical for Nvidia's data center GPUs and Apple's latest chips [3] Group 3: Strategic Partnerships and Support - TSMC has signed a memorandum to transfer its packaging operations from its Phoenix fab to Amkor, reducing the turnaround time for wafers that currently takes weeks to return from Asia [3] - The expansion is partially funded by the CHIPS Act, which includes $407 million and federal tax incentives, aimed at maintaining the U.S. position in the increasingly complex chip industry [3] Group 4: Challenges Ahead - Despite the progress, the opening date in 2028 indicates that the industry may continue to face challenges, particularly in alleviating GPU shortages and AI server bottlenecks, which still rely on established Asian packaging lines [3] - Amkor faces a significant workforce challenge, with an estimated shortage of 70,000 to 90,000 workers needed for all planned U.S. fabs, highlighting the ongoing talent crisis in the semiconductor sector [3]

Core Viewpoint - TSMC is accelerating its expansion in the United States, planning to establish two advanced packaging plants (AP1, AP2) with construction expected to start in the second half of 2026 and operational by 2028, in response to local demand for AI and HPC chip packaging [2][3]. Group 1: Expansion Plans - TSMC's second wafer fab (P2) in the U.S. is set to introduce 2nm process technology earlier than initially planned, while the advanced packaging plants are located directly across from P3, with construction now expedited to 2026 [2][3]. - The company aims to build two new advanced packaging facilities and a research center in Arizona, enhancing the AI supply chain [2][3]. Group 2: Technology and Production - AP1 will incorporate SoIC and CoW technologies, while AP2 is focused on CoPoS, which is expected to mature by 2028 [3][4]. - SoIC is currently TSMC's most advanced packaging technology, already in mass production for clients like AMD, Apple, and NVIDIA [3][4]. Group 3: Investment and Market Impact - TSMC announced a $100 billion investment in the U.S., which includes the construction of three wafer fabs, two advanced packaging facilities, and a research center, marking the largest single foreign direct investment in U.S. history [6][7]. - The establishment of advanced packaging lines in the U.S. is driven by the needs of major clients such as Apple, NVIDIA, and AMD, with a focus on CoWoS and InFO technologies [6][8]. Group 4: Supply Chain Considerations - The construction of advanced packaging facilities requires a complete supply chain, including materials and testing capabilities, which may take at least four years to establish [7][8]. - TSMC's expansion in the U.S. could impact the existing packaging and testing supply chain in Taiwan, necessitating a mature ecosystem for testing and packaging [8][9].

Investment Rating - The report initiates coverage of K&S (KLIC US) with a Buy rating, and BE Semiconductor (BESI NA) with a Neutral rating, while maintaining a Buy rating on ASMPT (522 HK) [3][6][11]. Core Insights - Advanced packaging (AP) is expected to evolve significantly from 2025 onwards, with a shift from CoWoS-S to CoWoS-L/R, increased adoption of SoIC driven by HBM5, and potential upgrades in InFO technology led by Apple [3][6]. - The semiconductor cycle's recovery is a key catalyst for K&S and ASMPT, given their substantial sales exposure to conventional packaging [3][6]. CoWoS Technology - CoWoS technology is transitioning from CoWoS-S to CoWoS-L, with TSMC expected to increase its CoWoS-L capacity from approximately 20% in 2024 to nearly 60% in 2025 [7][21]. - CoWoS-S is anticipated to face oversupply due to non-TSMC supply chain expansions, while CoWoS-L is expected to be in demand for high-end GPUs [7][28]. SoIC Technology - SoIC is projected to gain importance with the adoption of high-NA EUV technology, although headwinds are expected in 2025 due to limited new adopters and potential capex constraints from Intel [8][14]. - AMD is currently the major adopter of SoIC, with potential future demand driven by Apple and HBM technologies [8][14]. InFO Technology - Apple is likely to adopt upgraded InFO technology from 2026 onwards, necessitating capacity upgrades to accommodate new application processor designs [9][20]. - The transition from InFO-PoP to InFO-M is expected as the I/O count between DRAM and application processors becomes insufficient [9][20]. Company-Specific Insights - K&S is positioned to be the primary TCB supplier for TSMC's on-wafer process starting in 2025, benefiting from the shift towards CoWoS-L technology [3][6]. - ASMPT is expected to gain market share in the HBM market from a low base, with its TCB potentially adopted by TSMC and Apple in the future [3][6]. - BE Semiconductor faces challenges due to rich valuations and potentially disappointing hybrid bonding orders in 2025 [3][6].

如果您希望可以时常见面，欢迎标星收藏哦~ 2024年，AI引发的芯片需求全面爆发，半导体产业结构性转型持续演进。在这一年，台积电 再次交出了一份亮眼答卷：不仅巩固了其技术领先地位，还在产能、营收、客户结构与全球 战略布局方面全面开花，成为当前全球最具战略纵深的半导体企业。 透过其刚刚发布的2024年年报，我们可以更清晰地看到：在这场以AI为主引擎的产业变革 中，台积电正以技术为根基、制造为核心、生态为延伸，持续构筑属于自己的"护城河"。 AI爆发年，台积电"稳稳赢麻" 2024年，尽管全球经济仍充满不确定性，传统消费电子市场复苏缓慢，但AI相关芯片的需求却持 续强劲，推动晶圆代工行业走出低谷，重回成长轨道。台积电成为最大受益者之一。 年报显示，2024年台积电全年合并营收达900亿美元，同比增长30%；税后净利达365亿美元，同 比大幅增长35.9%。毛利率达到56.1%，营业利益率达45.7%，皆创历史新高。 作为全球晶圆代工产业的龙头，台积电已经在业内建立起不可动摇的地位。台积电在IDM 2.0产业 （包括了封装、测试和光罩制造等更多环节）中 占据34%的市场份额 ，较2023年的28%显著提 升，进一步 ...

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