然而，随着芯片服务提供商加速自主研发ASIC芯片以满足更复杂的功能需求，其对封装尺寸的 要求也大幅增长。因此，一些芯片服务提供商正在考虑从台积电的CoWoS芯片转向英特尔的 EMIB芯片。 TrendForce指出，CoWoS技术通过中介层将计算逻辑、内存和I/O芯片连接起来，并将这些芯片 安 装 在 基 板 上 。 该 技 术 已 扩 展 到 包 括 CoWoS-S 、 CoWoS-R 和 CoWoS-L 。 随 着 NVIDIA 的 Blackwell平台在2025年接近量产，市场需求正迅速转向CoWoS-L，因为它将硅中介层集成到了 封装中。预计随着NVIDIA即将推出的Rubin架构的推出，这一趋势还将继续，Rubin架构将采用 更大的光罩尺寸。 人工智能/高性能计算需求的增长导致了CoWoS技术的重大瓶颈，包括产能短缺、光罩尺寸限制 和制造成本上升。TrendForce观察到，大部分CoWoS产能已被NVIDIA GPU占用，其他客户的 选择十分有限。 此外，对更大封装尺寸的需求不断增长以及美国本地化要求，促使谷歌和 Meta 等北美主要 CSP 与英特尔合作，共同采用 EMIB。 英特尔的EMIB ...

Core Insights - Advanced packaging technology is crucial for overcoming performance bottlenecks in the semiconductor industry, driven by emerging applications like AI, high-performance computing, and 5G communication [3] - The global advanced packaging market is projected to grow from approximately $45 billion in 2024 to $80 billion by 2030, with a compound annual growth rate (CAGR) of 9.4% [3][75] Technical Evolution Dimension - TSMC's CoWoS technology has evolved from supporting 1.5x to 3.3x mask sizes, with plans for a 5.5x version by 2025-2026 and a 9x version by 2027, significantly increasing integration density and reducing signal transmission latency [6][7] - Hybrid bonding technology is emerging as a core technology for next-generation advanced packaging, enabling direct wafer bonding without bumps, thus enhancing interconnect density and reducing power consumption [10][11] - AMD's MI300X AI accelerator utilizes a 3.5D packaging architecture, combining TSMC's SoIC and CoWoS technologies, achieving unprecedented integration levels with 1,530 billion transistors [14][15] - Intel employs a multi-technology strategy in advanced packaging, focusing on EMIB and Foveros technologies, with plans for further enhancements to improve performance and integration [18][19] - Glass substrate technology is gaining traction as a disruptive innovation, offering advantages in electrical performance, thermal stability, and cost-effectiveness, with a projected market penetration exceeding 50% within five years [22][23] Material System Analysis - BT resin substrates are the most widely used packaging material, accounting for over 70% of IC substrates, known for their excellent thermal and electrical properties [26][27] - ABF substrates, developed by Ajinomoto, are preferred for high-end chip packaging due to their superior processing capabilities and electrical performance, despite higher costs [28][30] - Ceramic substrates, particularly AlN and Si3N4, are ideal for high-performance applications due to their high thermal conductivity and mechanical strength [32][34] Equipment and Process Dimension - TCB equipment is critical for HBM packaging, with ASMPT holding over 80% market share, driven by the demand for AI chips and high-performance computing [45][47] - The global die bonder market is dominated by four major players, with ASMPT leading at 31% market share, followed by BESI, Ficontec, and Neways [49][51] - The back-end packaging equipment market is characterized by a diverse competitive landscape, with Disco leading in wafer thinning and cutting technologies [54] Industry Layout Analysis - TSMC is experiencing exponential growth in CoWoS capacity, projected to reach 65,000-75,000 units per month by 2025, driven by AI chip demand [63][65] - The HBM market is dominated by three players: SK Hynix, Samsung, and Micron, collectively holding over 95% market share, with SK Hynix leading at 60-70% [67][68] - China's packaging industry is rapidly advancing, with Jiangsu Changjiang Electronics Technology, Tongfu Microelectronics, and Huada Semiconductor becoming significant players globally [70][71] - The global advanced packaging market is shifting towards IDM manufacturers, who leverage integrated design and manufacturing advantages, with Taiwan companies holding a dominant position in the AI packaging market [73][74]

Core Insights - North American cloud service providers (CSPs) like Google and Meta are actively engaging with Intel regarding the EMIB solution, indicating a shift in the chip landscape with the introduction of Google's TPU v9 by 2027 [1] - EMIB, a 2.5D advanced packaging technology from Intel, is gaining attention as CSPs face challenges with TSMC's CoWoS due to capacity shortages and high costs [1][2] - The rise of ASIC solutions, particularly represented by Google's TPU, is driving the demand for EMIB technology, with expectations of explosive growth in ASIC numbers from major players by 2026-2027 [2] Group 1: EMIB Technology and Market Dynamics - EMIB is positioned as a competitive alternative to TSMC's CoWoS, primarily due to its advantages in area and cost [3] - CoWoS has a high level of technical maturity but faces significant capacity constraints, with NVIDIA alone accounting for over 60% of its production [3] - EMIB allows for highly customizable packaging layouts, which may make it the preferred choice for ASIC applications [3][4] Group 2: Cost and Performance Considerations - EMIB's design simplifies the structure by eliminating expensive intermediary layers, providing a cost-effective solution for AI clients [4] - Despite its advantages, EMIB is currently limited by its interconnect bandwidth and signal transmission distance, making it more suitable for ASIC customers [5]

Group 1 - The storage industry is currently experiencing a super cycle driven by AI, leading to an increase in storage chip prices [1] - Advanced packaging technology is positively impacting the packaging materials supply chain, resulting in both volume and price increases [1] - The overall business operations of the company are benefiting from these industry trends [1]

Core Insights - The demand for AI HPC (High-Performance Computing) is driving the need for advanced packaging solutions, particularly TSMC's CoWoS technology, but some cloud service providers (CSPs) are considering Intel's EMIB technology due to increasing chip integration requirements [1][2] Group 1: CoWoS Technology - TSMC's CoWoS solution connects different functional chips using an interposer, with various versions like CoWoS-S, CoWoS-R, and CoWoS-L developed [1] - The market demand is shifting towards CoWoS-L, especially with NVIDIA's upcoming Blackwell platform set for mass production in 2025 [1] Group 2: EMIB Technology - EMIB offers several advantages over CoWoS, including a simplified structure that eliminates the expensive interposer, leading to higher yield rates [2] - EMIB has a smaller thermal expansion coefficient issue due to its design, which reduces the risk of packaging warping and reliability challenges [2] - EMIB can achieve larger packaging sizes, with EMIB-M already supporting 6 times the mask size, and projections for 8 to 12 times by 2027 [3] Group 3: Market Dynamics - The demand for CoWoS is facing challenges such as capacity shortages and high costs, prompting CSPs like Google and Meta to explore EMIB solutions [2] - Intel's EMIB technology has been in development since 2021 and is already applied in its server CPU platforms, with Google planning to implement it in TPUv9 by 2027 [3] - NVIDIA and AMD, which require high bandwidth and low latency, are expected to continue using CoWoS as their primary packaging solution [3]

Core Insights - The semiconductor industry is increasingly seeking alternative solutions due to the ongoing tight capacity for advanced packaging at TSMC, with Marvell and MediaTek evaluating the integration of Intel's EMIB technology into their ASIC chip designs [2][4]. Group 1: Industry Challenges - TSMC faces dual challenges: the inability to rapidly expand its advanced packaging capacity in the short term and the demand from U.S. clients for localizing the entire supply chain, which TSMC's U.S. backend capacity is not yet fully equipped to meet [4]. Group 2: Technological Developments - Intel's EMIB technology, which utilizes a 2.5D packaging architecture, is gaining attention for its unique advantages in heterogeneous chip integration [4]. - Recent job postings from leading companies like Apple, Qualcomm, and Broadcom explicitly mention EMIB-related positions, indicating a proactive approach to talent acquisition in the advanced packaging sector [4]. - Intel's newly launched 3.5D packaging technology achieves higher chip interconnect density through more precise silicon vias, further enhancing its competitive edge [4]. Group 3: Market Dynamics - The embedded bridge solution used in EMIB offers advantages in cost control and yield improvement compared to traditional intermediary layer designs, making it a key focus as advanced process evolution slows down [4]. - The shift of multiple companies towards the EMIB solution not only reflects current supply chain adaptation strategies but may also reshape the competitive landscape of the semiconductor packaging industry [4].

Core Insights - The demand for AI HPC (High-Performance Computing) is driving the need for advanced packaging solutions, particularly TSMC's CoWoS technology, but some cloud service providers (CSPs) are considering Intel's EMIB technology due to increasing chip integration requirements and packaging area demands [1][2]. Group 1: Technology Comparison - TSMC's CoWoS solution connects different functional chips using an interposer, while Intel's EMIB simplifies the structure by embedding silicon bridges directly into the substrate, resulting in higher yield rates [3][7]. - EMIB technology has advantages over CoWoS in terms of thermal expansion coefficient (CTE) issues, as it has a lower silicon ratio and fewer contact areas, reducing the risk of warping and reliability challenges [3][7]. Group 2: Market Dynamics - The current market for advanced packaging is facing capacity shortages and high costs associated with CoWoS, leading companies like Google and Meta to explore Intel's EMIB solutions [2][8]. - Intel's EMIB technology is expected to support larger die sizes and provide cost-effective solutions by eliminating the expensive interposer layer, making it attractive for AI customers [7][8]. Group 3: Future Prospects - EMIB is projected to achieve significant advancements in mask size, with EMIB-M already providing 6x mask size and expected to reach up to 12x by 2027, while CoWoS technologies are limited to lower mask sizes [4][7]. - Intel's Foundry Services (IFS) has been developing EMIB technology since 2021, and with major clients like Google and Meta showing interest, this could lead to substantial growth for IFS [8].

Core Insights - The article discusses the ongoing challenges and contradictions in the U.S. semiconductor export controls against China, highlighting that despite stringent measures, China is finding ways to circumvent these restrictions and advance its semiconductor industry [1][12]. Group 1: U.S. Export Controls - The U.S. government, particularly under the Trump administration, initiated a one-year suspension of certain export controls to China, which has led to significant backlash in Congress, prompting calls for tighter regulations [4][8]. - The U.S. Department of Commerce recently approved the sale of NVIDIA's Blackwell chips to companies in Saudi Arabia and the UAE, raising questions about the effectiveness of the export controls [4][10]. - The U.S. has limited resources to enforce these controls, with only about 600 personnel managing high-tech trade worth trillions, leading to numerous loopholes [10][21]. Group 2: China's Semiconductor Industry - Contrary to U.S. expectations, China's semiconductor industry is thriving, with projections indicating a 7.4% growth in the advanced packaging equipment market by 2025, reaching approximately 173.96 billion RMB [13][15]. - China is adopting a "multi-pronged" approach to semiconductor development, focusing on innovative technologies like Chiplet heterogeneous integration and advanced packaging, which allows it to bypass traditional process limitations [15][20]. - The collaboration across the entire semiconductor supply chain in China, involving research institutions and enterprises, is creating a robust ecosystem that is difficult to disrupt [15][17]. Group 3: International Dynamics - The U.S. attempts to rally allies like the Netherlands and Japan to strengthen export controls against China are proving ineffective, as these countries have economic interests in maintaining trade with China [17][21]. - Internal conflicts within the U.S. government are evident, with Congress pushing for strict controls while the executive branch is concerned about the impact on U.S. companies like NVIDIA [21][23]. - The U.S. is considering new regulations specifically targeting AI chips, but the complexity of enforcement and compliance costs may hinder effectiveness [23].

Core Insights - The "Yifeng Zhixin" advanced packaging project was officially signed in Shenzhen, marking a strategic collaboration among Luohu Investment Control, Yidao Information, and Huafeng Technology to enhance the "AI+" strategy and drive high-quality development for enterprises [1] Group 1: Project Overview - The project aims to gather top global resources in the semiconductor field to create a leading advanced packaging production line in China [1] - It will utilize cutting-edge technologies such as 2.5D and 3D packaging and environmentally friendly processes to innovate AI hardware and smart wearable devices [1] - The project addresses core demands in miniaturization, low power consumption, and long battery life for AI terminals and applications [1] Group 2: Company Profile - Yidao Information is a research and design-focused provider of smart terminal products and solutions, with a product matrix covering consumer-grade computers, rugged smart industry terminals, XR/AI wearables, and AIoT products [2] - The company reported a 24.23% year-on-year increase in revenue for the first three quarters of 2025, indicating steady improvement in operational quality [2] - Yidao Information has built a comprehensive computing product matrix that spans edge and endpoint devices, showcasing its technological strength and efficient productization capabilities [2] Group 3: Strategic Importance - The establishment of the advanced packaging project is a significant strategic move for Yidao Information's AI ecosystem development [3] - The collaboration aims to integrate resources and achieve complementary advantages, promoting the deep integration of packaging technology with AI terminals and application scenarios [3] - The project supports the construction of the "Three Forces and Three Areas" initiative in the Luohu District, aiming to create a new engine for the gathering of emerging industries [1]

Core Insights - The semiconductor industry is rapidly shifting towards packaging technology, with advanced packaging and bonding techniques identified as key breakthroughs to overcome critical challenges, serving as the next growth engine for the industry [1] - Technologies such as hybrid bonding and non-solder bonding are maturing, facilitating advancements in 3D packaging and heterogeneous integration towards higher density and reliability [1] - New materials like nano-silver sintering are being adopted to address traditional bonding materials' thermal expansion coefficient matching issues [1] - The demand from sectors like 5G, AI, and automotive electronics is increasing the requirements for chip heat dissipation efficiency and signal transmission speed, making advanced packaging a crucial pathway to enhance computing power cost-effectiveness amid the slowing of Moore's Law [1] - Domestic companies are entering high-end markets such as HBM and power semiconductors from the mid-to-low-end market, although they still rely on international suppliers like ASM Pacific for key equipment and materials [1] - The global advanced packaging market is expected to reach $65 billion by 2027, with hybrid bonding technology projected to grow the fastest, and advanced packaging is anticipated to surpass traditional packaging as the mainstream technology by 2026 [1] - The integrated circuit ETF (159546) tracks the integrated circuit index (932087), which selects listed companies involved in semiconductor design, wafer manufacturing, packaging testing, and related materials and equipment, effectively reflecting the overall performance of core enterprises in China's integrated circuit industry [1]