Core Viewpoint - The Chinese Academy of Sciences Microelectronics Research Institute has announced procurement intentions for 10 types of instruments and equipment, with a total budget of 119 million yuan, scheduled for procurement between June and November 2025 [2][3]. Procurement Overview - The procurement includes advanced semiconductor manufacturing equipment such as: - 8-inch chemical pure gas high selectivity isotropic etching equipment - 3D integrated packaging structure function analyzer - Critical dimension measurement equipment - High-precision scanning electron microscope [3][4][5][6]. Instrument Descriptions - **Imaging-Based Overlay Measurement Tool**: A key detection device in semiconductor manufacturing for high-precision measurement of overlay errors, essential for aligning multi-layer micro-nano structures on chips. It is becoming a mainstream solution due to its high resolution and non-contact characteristics as feature sizes shrink to below 5 nm [4]. - **3D Integrated Packaging Structure Function Analyzer**: A multifunctional, high-precision, non-destructive analysis system for 3D integrated packaging structures, crucial for manufacturing, reliability testing, and failure analysis. It addresses the high demands of complex structures in advanced packaging technologies [5]. - **Diffraction-Based Overlay Measurement Tool**: An advanced technology for high-precision measurement of overlay errors in semiconductor manufacturing, utilizing diffraction patterns to achieve sub-nanometer precision [6]. Budget and Procurement Timeline - The total budget for the procurement is 119 million yuan, with specific allocations for each type of equipment. The procurement is expected to occur from June to November 2025 [2][3][8].

Core Viewpoint - The semiconductor industry is transitioning towards the "beyond Moore" era, driven by the increasing demand for efficient thermal management technologies in emerging fields such as 5G, AI, HPC, and data centers [2] Group 1: Conference Overview - The 2025 Advanced Packaging and Thermal Management Conference will focus on high-performance thermal management challenges, featuring three main forums: Advanced Packaging and Heterogeneous Integration Forum, High-Performance Thermal Management Innovation Forum, and Liquid Cooling Technology and Market Application Forum [3][4] - The conference aims to build a platform for industry-academia-research collaboration, promoting technological integration and providing innovative momentum for the semiconductor supply chain [3] Group 2: Conference Details - The conference is organized by Flink Qiming Chain and supported by the National Third Generation Semiconductor Technology Innovation Center (Suzhou) [4] - Scheduled for September 25-26, 2025, in Suzhou, Jiangsu, the conference expects around 500 participants [3] Group 3: Confirmed Speakers - Notable speakers include Professor Liang Jianbo from the National Third Generation Semiconductor Technology Innovation Center, who will discuss high thermal conductivity interface and packaging technology [7] - Other speakers represent various institutions, including the Chinese Academy of Sciences and universities, covering topics such as photothermal polyimide materials and advanced packaging applications [8][9] Group 4: Forum Topics - The forums will address key topics such as advanced packaging technology routes, cost optimization, and challenges in 2.5D/3D integration [17] - The High-Performance Thermal Management Forum will explore thermal interface materials, high-performance chip thermal management solutions, and the impact of Chiplet technology on thermal management [20][21] Group 5: Liquid Cooling Technology - The Liquid Cooling Technology Forum will discuss innovations and challenges in liquid cooling, including the standardization of cooling fluids and the application of immersion cooling in high-power density scenarios [23][24] - Topics will also cover the lifecycle cost analysis of liquid cooling systems and their integration in data centers and electric vehicles [25]

Core Viewpoint - The article discusses the evolution and significance of integrated circuit (IC) packaging in the semiconductor manufacturing process, highlighting the transition from 2D to 2.5D and 3D IC architectures as essential innovations to meet the increasing demands for performance and efficiency in modern electronic devices [2][11][29]. Summary by Sections IC Packaging Overview - IC packaging is a critical step in semiconductor manufacturing, providing protection and functionality to semiconductor chips [2][4]. - The packaging process involves placing fragile semiconductor chips into protective casings, similar to placing a cake in a sturdy box for transport [4][6]. Transition from 2D to 2.5D and 3D IC - The semiconductor industry is moving towards innovative packaging technologies like 2.5D and 3D IC to overcome limitations posed by traditional 2D packaging, especially as Moore's Law slows down [11][27]. - 2.5D IC involves placing chips side by side on an interposer, while 3D IC stacks chips vertically, enhancing integration density and performance [13][25]. Advantages and Challenges of 2.5D and 3D IC - 2.5D IC allows for moderate design complexity and easier thermal management, making it suitable for applications like GPUs and FPGAs [19][28]. - 3D IC offers very high integration density and reduced signal transmission distance, but faces challenges in cooling and design complexity [25][28]. - Both architectures aim to improve performance, reduce power consumption, and minimize space, essential for mobile and edge devices [27][29]. Market Outlook - The advanced chip packaging market is projected to grow from $3.5 billion in 2023 to over $10 billion by 2030, driven by demand in AI, 5G, high-performance computing (HPC), and automotive sectors [27][29].

Group 1 - Glass substrates are characterized by high transparency, excellent flatness, and good stability, serving as a support carrier to ensure the reliable fixation of functional materials and the overall stability and lifespan of devices [1][2] - The global advanced packaging market is projected to grow from $28.8 billion in 2019 to $42.5 billion by 2024, indicating a rising penetration rate [1][13] - The introduction of glass substrates can reduce capacitance between interconnections, leading to faster signal transmission and improved overall performance, particularly in data centers, telecommunications, and high-performance computing applications [1][15] Group 2 - The glass substrate industry chain includes key segments such as raw materials, equipment, technology, production, packaging testing, and applications, with special glass materials being crucial for semiconductor manufacturing [6] - The TGV (Through Glass Via) technology is a core technique for glass substrate packaging, enabling vertical electrical interconnections and addressing challenges associated with traditional TSV technology [19][20] - The glass substrate market is expected to reach over $400 million by 2030, with a penetration rate exceeding 2%, although organic substrates will continue to dominate the semiconductor packaging field in the near term [15][17] Group 3 - The glass substrate technology is anticipated to play a significant role in the semiconductor industry, with ongoing advancements focusing on process optimization, improving via precision and density, and expanding the functional applications of glass substrates [25] - The global semiconductor market is projected to reach $635.1 billion in 2024, reflecting a 19.8% year-on-year growth, driven by the increasing demand for high-performance semiconductor products [9]

Core Insights - Dongguan has launched its first strategic scientist team, achieving significant technological advancements in semiconductor and AI chip development, including the international first TGV 3.0 technology and the world's first low-power AI chip [1][2][4]. Group 1: Technological Innovations - The TGV 3.0 technology has overcome production bottlenecks, achieving sub-10 micron through-hole and a 10:1 aspect ratio, with a through-hole yield of 99.9%, enhancing 3D packaging solutions [4]. - The world's first "energy-aware computing" low-power AI chip operates at only 70mW with a processing power of 512 GOPS, suitable for AIoT and edge computing applications [4]. - The first PLP plasma etching equipment in the country supports large glass substrates and achieves international advanced levels in etching rate and uniformity [4]. - The first fully automated AI-AOI detection equipment offers precision detection at 0.001 microns with an accuracy exceeding 99%, filling a gap in high-end semiconductor testing equipment in China [4]. Group 2: Strategic Development - Dongguan's strategic scientist team, led by Professor Yang Xiaobo, focuses on advanced packaging and low-power AI chips, addressing critical technological challenges in the semiconductor industry [3][4]. - The city aims to transition from "Dongguan manufacturing" to "Dongguan intelligent manufacturing," leveraging its manufacturing base to enhance its technological capabilities [5]. - Dongguan has established a complete industrial chain in semiconductor and integrated circuit sectors, with 257 semiconductor companies and projected industry revenue exceeding 75 billion yuan in 2024 [6]. Group 3: Talent and Policy Support - The local government is optimizing talent policies to attract high-level scientific talent, supporting innovation and entrepreneurship through strategic scientist teams and research initiatives [8][12]. - The Dongguan Integrated Circuit Innovation Center aims to enhance technological innovation capabilities and strengthen the industrial ecosystem, focusing on the transformation of scientific achievements into industrial applications [8][12]. - The collaboration between research teams, the innovation center, and local government is noted for its efficiency and responsiveness, fostering a supportive environment for startups [11].