Core Viewpoint - The article discusses UMC's potential acquisition of a factory from Han Yu Crystal in Tainan Science Park, emphasizing the company's strategic focus on expanding advanced packaging capabilities in Taiwan and Singapore [1][3]. Group 1: Company Strategy - UMC is exploring opportunities for operational and profit enhancement, including factory acquisitions, technology collaborations, and new investments, with Taiwan remaining a key expansion option [3][5]. - The company plans to integrate wafer fabrication with advanced packaging solutions, moving beyond traditional foundry services to high-value areas [4][5]. Group 2: Technological Development - UMC has established 2.5D advanced packaging capabilities in Singapore and is leveraging wafer-to-wafer bonding technology, which is crucial for 3D IC manufacturing [4][5]. - The company is currently focused on 12nm process technology in collaboration with Intel, while also looking to diversify into compound semiconductors and specialized materials [4][5]. Group 3: Production Capacity - UMC's interposer production currently stands at approximately 6,000 units per month, with no immediate plans for capacity expansion [5]. - Future efforts will concentrate on developing integrated technologies with higher added value, providing comprehensive system-level solutions for clients [5].

Core Viewpoint - The article discusses the limitations and challenges of interposer line lengths in advanced packaging, highlighting the differences between electrical and optical interposers and the implications for signal integrity and transmission efficiency [1][11]. Group 1: Interposer Types and Challenges - There are two main types of interposers in production: organic interposers (RDL) and silicon interposers, with organic interposers being significantly cheaper to produce but having larger feature sizes [2]. - The use of silicon does not necessitate narrow lines, as wider signal lines require more signal layers, which is undesirable for manufacturers [2][3]. - The resistance of narrow lines in organic interposers leads to significant insertion loss, which is a major concern for clients [3][5]. Group 2: Signal Integrity and Grounding - Signal integrity is heavily reliant on good grounding, typically provided by ground layers, which can serve multiple functions including power delivery and impedance control [7]. - Controlled impedance is crucial for maintaining signal quality, and even short lines can suffer from interference or crosstalk [7][8]. - Designers strive to minimize loss and maintain grounding around high-speed lines, which can be challenging due to manufacturing constraints [8][10]. Group 3: Optical Interposers and Future Directions - Optical interposers face fewer limitations compared to electrical ones, as optical signals can transmit over longer distances [1][11]. - The integration of optical devices into packaging is a growing trend, with technologies like Lightmatter's Passage aiming to combine CMOS and silicon photonics within an interposer [11][12]. - While photonics offers a potential long-term solution to line length limitations, it is not yet ready for mass production [14].

公众号记得加星标⭐️，第一时间看推送不会错过。 玻璃中介层支持嵌入基板的芯粒与直接堆叠于顶部的芯粒（chiplets）之间的3D堆叠，这是硅中 介层无法实现的。在本研究中，我们通过关键系统级指标（包括面积、线长、信号完整性、电源 完整性和热完整性）论证了玻璃中介层相较于硅中介层在这种堆叠方式下的优势。我们利用芯粒 和中介层的GDS版图设计以及签核仿真实现了这一目标。 实验表明，玻璃中介层相比硅中介层可实现2.6倍的面积优化、21倍的线长缩短、全芯片功耗降 低17.72%、信号完整性提升64.7%、电源完整性改善10倍，但温度会升高15%。 引言 如今及未来，提升高复杂度系统良率的一个可行方法是将系统划分为"芯粒"。这些芯粒需集成以构成 完整系统。根据物理结构，芯粒集成有两种类型：2.5D中介层集成和3D堆叠集成。2.5D集成因允许 在中介层上集成多个现成芯粒或复用不同技术节点的知识产权 (IP)（异构集成），成为颇具吸引力的 选择。在2.5D集成中，芯粒以倒装芯片方式并排置于中介层封装顶部，如图1 (a) 所示。此外，它们 通过再分布层 (RDL) 连接，RDL是无源中介层基板上的金属层，用于提供芯粒间的横向 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 玻璃中介层支持嵌入基板的芯粒与直接堆叠于顶部的芯粒（chiplets）之间的3D堆叠，这是硅中 介层无法实现的。在本研究中，我们通过关键系统级指标（包括面积、线长、信号完整性、电源 完整性和热完整性）论证了玻璃中介层相较于硅中介层在这种堆叠方式下的优势。我们利用芯粒 和中介层的GDS版图设计以及签核仿真实现了这一目标。 实验表明，玻璃中介层相比硅中介层可实现2.6倍的面积优化、21倍的线长缩短、全芯片功耗降 低17.72%、信号完整性提升64.7%、电源完整性改善10倍，但温度会升高15%。 引言 如今及未来，提升高复杂度系统良率的一个可行方法是将系统划分为"芯粒"。这些芯粒需集成以构成 完整系统。根据物理结构，芯粒集成有两种类型：2.5D中介层集成和3D堆叠集成。2.5D集成因允许 在中介层上集成多个现成芯粒或复用不同技术节点的知识产权 (IP)（异构集成），成为颇具吸引力的 选择。在2.5D集成中，芯粒以倒装芯片方式并排置于中介层封装顶部，如图1 (a) 所示。此外，它们 通过再分布层 (RDL) 连接，RDL是无源中介层基板上的金属层，用于提供芯粒间的横向 ...

如果您希望可以时常见面，欢迎标星收藏哦~ 自半导体工业诞生以来，集成电路就一直被封装在封装件中。最初的想法主要是保护内部脆 弱的硅片不受外部环境的影响，但在过去的十年中，封装的性质和作用发生了巨大的变化。 虽然芯片保护仍然重要，但它已成为封装中最不引人关注的作用。 本文探讨了封装领域最大的变化，即通常所说的先进封装。先进的含义并没有明确的定义。相反， 该术语广泛涵盖了多种可能的封装方案，所有这些方案都比传统的单芯片封装复杂得多。先进封装 通常封装了多个元件，但组装方式却千差万别。 在这种讨论中，经常会提到 2.5D 或 3D 封装，这些描述指的是内部元件的排列方式。 本文首先讨论了从外部观察到的封装类型，然后向内讨论了高级封装所集成的基本组件。之后，将 更详细地探讨每个组件。大部分讨论将涉及高级软件包的各种组装过程。文章最后探讨了任何技术 讨论都必须涉及的四个主题--工程师如何设计先进封装、如何对其进行测试、先进封装的总体可靠 性影响以及任何安全影响。 文章还简要讨论了两个相关的广泛话题。首先是键合。虽然这是封装的一个必要组成部分，但它本 身也是一个很大的话题，在此不作详细讨论。其次是不属于集成电路但可能包含 ...