同时，硅桥接技术可在嵌入有机中介层或基板中的芯片或芯片组之间实现高密度互连。硅是目前互连 密度最高的材料，因此，硅桥接技术的设计理念在于使其体积小、成本低，这与硅中介层形成鲜明对 比。然而，组装良率问题延缓了硅桥接技术最终所承诺的成本优势的实现。 公众号记得加星标⭐️，第一时间看推送不会错过。 中介层和桥接器是先进封装中连接多个芯片和芯片组的两个关键元件，它们的构造和组装方式正在发 生根本性的变化。 中介层正变得越来越厚、越来越复杂，而桥接技术则被用来降低组装成本。这两种努力都面临着新的 挑战。 中介层实际上是一个平台，可以在其上组装多个组件，类似于微型PCB。目前主要材料是硅，即使采 用较早的工艺节点制造，其尺寸也使其价格昂贵。它们通常用于处理高密度互连，同时将I/O、电源 和接地信号传递到下方的封装基板。 图1 ：中介层与桥接层。中介层是大型硅平台，而桥接层是嵌入有机中介层或衬底中的小型硅片 中介层越来越多 人工智能正在推动中介层的复杂性。"我们现在看到更厚的中介层，金属层也更多，以适应人工智能 和高性能计算芯片所需的高密度布线和高电流路径，" YieldWerx首席执行官 Aftkhar Aslam 表 ...

Core Viewpoint - Rapidus, a Japanese semiconductor manufacturer, is developing a technology to reduce the production costs of semiconductors for artificial intelligence applications, aiming to compete more effectively with TSMC, which is preparing for full-scale production [1] Group 1: Technology Development - Rapidus has created the world's first prototype of an intermediary layer made from large glass substrates, targeting mass production by 2028 [1] - The intermediary layer serves as a platform for installing GPUs and high-bandwidth memory for AI semiconductors, providing interconnections between these components [1] - By using a square glass substrate with a side length of 600mm, Rapidus can produce ten times the number of intermediary layers compared to traditional methods that use 300mm circular silicon wafers, significantly reducing waste [1] Group 2: Competitive Landscape - Rapidus plans to mass-produce 2nm chips and aims to start forming circuits on wafers in the fiscal year 2027, with large-scale production of the backend processes expected to begin in 2028 [2] - The company is leveraging the latest materials suitable for AI semiconductors without being constrained by existing practices, positioning itself as a latecomer in the industry [2] Group 3: Financial Support and Market Position - The Japanese Ministry of Economy, Trade and Industry has committed to providing Rapidus with 1.72 trillion yen (approximately 111 billion USD) in support, with 180.5 billion yen allocated for backend processes [2] - Currently, mainland China and Taiwan account for 30% and 28% of global backend production, respectively, while Japan lags behind at only 6% [3] - Rapidus is collaborating with other Japanese companies to automate backend production processes, which are becoming increasingly complex due to the nature of AI chip assembly [3]

Core Viewpoint - The interposer has transitioned from a supporting role to a focal point in the semiconductor industry, with major companies like Resonac and NVIDIA leading initiatives to develop advanced interposer technologies [1][28]. Group 1: Definition and Importance of Interposer - Interposer serves as a critical layer between chips and packaging substrates, enabling high-density interconnections and efficient integration of various chiplets into a system-in-package (SiP) [3][5]. - The interposer is essential for achieving higher bandwidth, lower latency, and increased computational density in advanced packaging [3][5]. Group 2: Types of Interposers - Two main types of interposers are currently in production: Silicon Interposer (inorganic) and Organic Interposer (Redistribution Layer) [5][6]. - Silicon Interposer has been established since the late 2000s, with TSMC pioneering its use in high-performance computing [6]. - Organic Interposer is gaining traction due to its lower production costs and flexibility, despite challenges in wiring precision and reliability [6][23]. Group 3: JOINT3 Alliance - The JOINT3 alliance, led by Resonac, consists of 27 global companies aiming to develop next-generation semiconductor packaging, focusing on panel-level organic interposers [8][11]. - The alliance plans to establish a dedicated center in Japan for advanced organic interposer development, targeting a significant increase in production efficiency and cost reduction [11][12]. - The shift to organic interposers is driven by the limitations of silicon interposers, particularly in terms of geometric losses and production costs [11][12]. Group 4: SiC Interposer as a New Direction - NVIDIA is exploring the use of Silicon Carbide (SiC) interposers for its next-generation GPUs, indicating a potential shift in materials used for interposers [17][19]. - SiC offers superior thermal conductivity and electrical insulation, making it suitable for high-performance AI and HPC applications, although manufacturing challenges remain [19][25]. Group 5: Competitive Landscape of Interposer Materials - The competition among silicon, organic, and SiC interposers is characterized by their respective advantages and disadvantages, influencing performance, cost, and scalability [20][22][23]. - Silicon interposers are currently dominant but face challenges as chip sizes increase, while organic interposers are expected to gain market share due to cost advantages [22][26]. - SiC interposers, if successfully developed, could become the standard for cutting-edge AI and HPC packaging in the long term [26]. Group 6: Future Trends - In the short term, silicon interposers will remain the market leader, while organic interposers are anticipated to see widespread adoption in the mid-term due to their cost and scalability benefits [26]. - Long-term projections suggest that SiC interposers may emerge as the preferred choice for advanced packaging once manufacturing hurdles are overcome [26].

Core Viewpoint - Resonac has established an alliance named JOINT3, consisting of nearly 30 global companies, to develop advanced chip packaging technologies to meet the growing demand for artificial intelligence [2][3] Group 1: Alliance Formation - The JOINT3 alliance includes 27 companies, such as material manufacturers, equipment manufacturers, and chip designers, aiming to collaboratively develop materials, equipment, and design tools for chip packaging [2] - The alliance provides a practical platform for stakeholders to create and manufacture materials and technologies required for intermediary layers used in large panel manufacturing [2][3] Group 2: Importance of Intermediary Layers - Intermediary layers are critical components in chip packaging, facilitating communication between multiple chips integrated into a single module [2] - The demand for intermediary layers is expected to rise due to the increasing need for advanced packaging methods that can integrate more chips, as traditional methods of reducing transistor sizes become more challenging and costly [3] Group 3: Research and Development Initiatives - Resonac plans to establish a research and development center in Ibaraki Prefecture, northern Tokyo, which will house a prototype production line expected to be operational next year [3] - The five-year project is projected to cost 26 billion yen (approximately 174 million USD), funded and operated by participating companies [3] Group 4: Industry Trends - The rapid development of technologies such as generative artificial intelligence and autonomous driving is increasing the complexity of semiconductor technology requirements [3] - The current era is seen as a time for cross-company and cross-national collaboration to address technological challenges in the semiconductor industry [3]

Core Viewpoint - United Microelectronics Corporation (UMC) is making significant strides in advanced packaging technology, securing a major contract with Qualcomm and developing its own high-end interposer, which has been validated by Qualcomm, indicating a countdown to mass production [1][2]. Group 1: Advanced Packaging Developments - UMC's collaboration with Qualcomm focuses on advanced packaging for high-performance computing applications, particularly in AI PCs, automotive, and AI server markets, with initial production expected in Q1 2026 [1][2]. - The first batch of interposers with a capacitance of 1500nF/mm² has passed Qualcomm's electrical testing, showcasing UMC's capability in advanced packaging [1][2]. - UMC's advanced packaging technology, including 2.5D and 3D packaging, relies heavily on interposer capacitors, which are crucial for connecting stacked or side-by-side chips [2]. Group 2: Competitive Positioning - UMC's entry into advanced packaging allows it to differentiate itself from competitors in the mature process wafer foundry market, particularly against the backdrop of low-cost competition from the "red supply chain" [2]. - The partnership with Qualcomm not only involves orders but also includes Qualcomm purchasing equipment to be placed in UMC's facilities, indicating a deep and trusting collaboration [2]. Group 3: Process Technology Advancements - UMC is advancing its wafer foundry business by developing high-voltage process technologies, including a 14nm FinFET embedded high-voltage process platform, and is exploring collaboration with Intel to extend its process capabilities from 12nm to 6nm [3][4]. - UMC invested NT$15.6 billion in R&D last year, focusing on process technologies required for 5G communications, AI, IoT, and automotive electronics, with progress in special processes and 3D IC advanced packaging [3]. Group 4: Performance Enhancements - The 12nm FinFET process technology platform offers significant improvements over the 14nm technology, achieving a 10% performance increase and a 20% reduction in power consumption, while also reducing chip area by over 10% [4]. - UMC's advancements in process technology enhance its cost competitiveness and position in the semiconductor market [4].