Investment Rating - The report maintains an "Overweight" rating for the communication industry [1][7] Core Insights - The necessity for large-scale computing power continues, with a competitive landscape intensifying. The release of OpenAI's GPT-5 confirms the sustained high demand for computing resources, as evidenced by a significant cloud service agreement with Oracle valued at approximately $30 billion annually [4][11] - Progress on the "Rubin" GPU architecture by NVIDIA is on track, with notable increases in liquid cooling component prices and a projected global market size for liquid cooling exceeding 70 billion yuan by 2026 [5][12] - The domestic AI chip ecosystem is improving, with companies like Cambricon raising funds to enhance their capabilities in AI chip development, indicating a growing market space for domestic chips [6][13][14] Summary by Sections Industry Overview - The communication industry is experiencing a robust performance compared to the CSI 300 index, with a notable increase in the industry index [3] Market Trends - Liquid cooling technology is gaining traction, with its penetration rate expected to rise from under 15% in 2023 to over 50% by 2025, driven by the increasing power requirements of data centers [5][12] - The price of copper-clad laminates and fiberglass cloth used in PCBs has seen significant increases due to supply shortages, indicating a tightening supply chain [5][12] Investment Opportunities - Recommended companies to watch include those in the optical module sector such as Zhongji Xuchuang and NewEase, as well as PCB manufacturers like Shenghong Technology and Huadian Technology, and liquid cooling firms like Invec and Sihuan New Materials [6][14]

Core Viewpoint - TSMC is significantly expanding its CoWoS capacity, with projections indicating a rise from 70k wpm at the end of 2025 to 100-105k wpm by the end of 2026, and further exceeding 130k wpm by 2027, showcasing a growth rate that outpaces the industry average [1][2]. Capacity Expansion - TSMC's CoWoS capacity will reach 675k wafers in 2025, 1.08 million wafers in 2026 (a 60% year-on-year increase), and 1.43 million wafers in 2027 (a 31% year-on-year increase) [1]. - The expansion is concentrated in specific factories, with the Tainan AP8 factory expected to contribute approximately 30k wpm by the end of 2026, primarily serving high-end chips for NVIDIA and AMD [2]. Utilization Rates - Due to order matching issues with NVIDIA, CoWoS utilization is expected to drop to around 90% from Q4 2025 to Q1 2026, with some capacity expansion plans delayed from Q2 to Q3 2026. However, utilization is projected to return to full capacity in the second half of 2026 with the mass production of new projects [4]. Customer Allocation - In 2026, NVIDIA is projected to occupy 50.1% of CoWoS capacity, down from 51.4% in 2025, with an allocation of approximately 541k wafers [5][6]. - AMD's CoWoS capacity is expected to grow from 52k wafers in 2025 to 99k wafers in 2026, while Broadcom's capacity is projected to reach 187k wafers, benefiting from the production of Google TPU and Meta V3 ASIC [5][6]. Technology Developments - TSMC is focusing on advanced packaging technologies such as CoPoS and WMCM, with CoPoS expected to be commercially available by the end of 2028, while WMCM is set for mass production in Q2 2026 [11][14]. - CoPoS technology offers higher yield efficiency and lower costs compared to CoWoS, while WMCM is positioned as a cost-effective solution for mid-range markets [12][14]. Supply Chain and Global Strategy - TSMC plans to outsource CoWoS backend processes to ASE/SPIL, which is expected to generate significant revenue growth for these companies [15]. - TSMC's aggressive investment strategy in the U.S. aims to establish advanced packaging facilities, enhancing local supply chain capabilities and addressing global supply chain restructuring [15]. AI Business Contribution - AI-related revenue for TSMC is projected to increase from 6% in 2023 to 35% in 2026, with front-end wafer revenue at $45.162 billion and CoWoS backend revenue at $6.273 billion, becoming a core growth driver [16].

Core Viewpoint - NVIDIA is considering adopting CoWoP as its next packaging solution for the upcoming Rubin GPU, indicating a potential shift in its packaging strategy from the established CoWoS technology [3][7]. Group 1: CoWoP Technology Overview - CoWoP (Chip-on-Wafer-on-Platform PCB) offers several advantages, including improved signal and power integrity, reduced substrate loss, and enhanced voltage regulation proximity to the main GPU chip [4][5]. - The technology allows for direct contact between cooling solutions and the silicon chip, eliminating the need for a packaging lid, which reduces costs [4][5]. - NVIDIA has begun early testing of CoWoP technology with a sample based on the GB100 GPU, aiming to evaluate manufacturing processes and electrical functionality [4][7]. Group 2: Future Plans and Testing - NVIDIA plans to start testing a fully functional GB100 CoWoP device in August 2025, which will retain the same dimensions and focus on manufacturability and thermal design [4][7]. - The GR100 CoWoP will serve as a testing platform for the GR150 "Rubin" solution, expected to enter production by late 2026, with market availability anticipated in 2027 [7]. Group 3: Market Dynamics and Competition - Morgan Stanley predicts that NVIDIA will dominate the CoWoS wafer demand in 2026, with an estimated 595,000 wafers needed, accounting for about 60% of the global market [10][11]. - The competition for CoWoS capacity is intensifying, with TSMC expected to be the major beneficiary, as global demand for CoWoS wafers is projected to grow significantly from 370,000 in 2024 to 1 million in 2026 [9][11]. - Other tech giants like AMD and Broadcom are also expected to secure significant shares of CoWoS capacity, indicating a competitive landscape in the AI chip market [10][11].

Core Viewpoint - The HBM (High Bandwidth Memory) market is expected to experience tight supply and demand until 2027, driven by technological iterations and AI demand, with SK Hynix and Micron leading the market due to their technological and capacity advantages [1][2]. Supply and Demand Trends - HBM supply tightness is projected to persist through 2027, with a gradual easing of oversupply expected in 2026-2027. Channel inventory is anticipated to increase by 1-2 weeks, reaching a healthy level [2]. - The delay in Samsung's HBM certification and the strong demand growth from NVIDIA's Rubin GPU are the main factors contributing to the current supply-demand tension [2]. - HBM4 supply is expected to significantly increase by 2026, accounting for 30% of total bit supply, with HBM4 and HBM4E combined expected to exceed 70% by 2027 [2]. Demand Drivers - HBM bit demand is forecasted to accelerate again in 2027, primarily driven by the Vera Rubin GPU and AMD MI400 [3]. - From 2024 to 2027, the CAGR for bit demand from ASICs, NVIDIA, and AMD is projected to exceed 50%, with NVIDIA expected to dominate demand growth [3]. - Sovereign AI demand is emerging as a key structural driver, with various countries investing heavily in national AI infrastructure to ensure data sovereignty and security [3]. Pricing and Cost Structure - Recent discussions around HBM pricing are influenced by Samsung's aggressive pricing strategy to capture market share in HBM3E and HBM4 [4]. - HBM4 is expected to have a price premium of 30-40% over HBM3E12Hi to compensate for higher costs, with logic chip costs being a significant factor [4]. Market Landscape - SK Hynix is expected to lead the HBM market, while Micron is likely to gain market share due to its capacity expansion efforts in Taiwan and Singapore [5]. - Micron's HBM revenue grew by 50% quarter-over-quarter, with a revenue run rate of $1.5 billion, indicating a stronger revenue-capacity conversion trend compared to Samsung [6]. Industry Impact - HBM is driving the DRAM industry into a five-year upcycle, with HBM expected to account for 19% of DRAM revenue in 2024 and 56% by 2030 [7]. - The average selling price (ASP) of DRAM is projected to grow at a CAGR of 3% from 2025 to 2030, primarily driven by the increasing sales proportion of HBM [7]. - Capital expenditures for HBM are expected to continue growing, as memory manufacturers focus on expanding capacity to meet rising HBM demand [7].

Core Insights - The development of HBM technology is driven by the demand for AI servers, with major manufacturers actively advancing HBM4 product progress [1] - The complexity of chip design and increased wafer area due to higher I/O counts in HBM4 is expected to raise production costs significantly [1] - HBM4 is anticipated to have a premium exceeding 30%, compared to the 20% premium observed with the recent HBM3e launch [1] Industry Developments - NVIDIA showcased its latest Rubin GPU at the GTC conference, while AMD is competing with its MI400, both of which will feature HBM4 [1] - HBM4's I/O count has doubled from 1024 to 2048 compared to previous generations, maintaining a data transfer rate of over 8.0 Gbps, similar to HBM3e [1] - The increased channel count in HBM4 allows for a doubling of data transmission volume at the same transfer speed [1]

Core Insights - The development of HBM technology is driven by the demand for AI servers, with major manufacturers actively advancing HBM4 product timelines [1][5] - HBM4 is expected to have a premium exceeding 30% due to increased manufacturing complexity compared to HBM3e, which had a premium of about 20% at launch [1] Group 1: HBM Technology Overview - HBM4 is set to release in 2026, featuring a core die density of 24Gb, with layers ranging from 12 to 16 and a speed of 8-10 Gbps, doubling the I/O count from 1024 to 2048 compared to previous generations [2][5] - HBM3e, released in 2024, has a core die density of 24Gb and an I/O count of 1024, while HBM3, released in 2022, has a core die density of 16Gb [2] Group 2: Market Projections - TrendForce forecasts that the total shipment volume of the HBM market will exceed 30 billion Gb by 2026, with HBM4 expected to surpass HBM3e in market share by the second half of 2026 [6] - SK hynix is projected to maintain a leading position with over 50% market share in HBM4, while Samsung and Micron need to improve product yield and capacity to catch up [6]

如今的高端处理器，尤其是那些支持数据中心和人工智能工作负载的处理器，已经依赖多芯片设计 来满足对性能和内存带宽不断增长的需求。台积电目前的 CoWoS 解决方案可容纳面积高达 2,831 平方毫米的中介层，是标准光掩模版面积的三倍多，而受 EUV 光刻技术的限制，标准光掩模版面 积仅为 830 至 858 平方毫米。 该技术已经应用于 AMD 的 Instinct MI300X 和 Nvidia 的 B200 GPU 等产品，这些产品将大型 计算芯片组与高带宽内存堆栈结合在一起。 如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 techspot ，谢谢。 随着台积电准备扩大其芯片封装技术的物理规模，半导体行业正迈向一个重要的里程碑。在最近的 北美技术研讨会上，台积电详细介绍了新一代CoWoS（晶圆上芯片封装）技术的计划，该技术能 够组装比目前量产的芯片尺寸大得多的多芯片处理器。 然而，随着人工智能和高性能计算应用的复杂性不断增长，对更多硅的需求也日益增长。为了应对 这一挑战，台积电正在开发一种全新的 CoWoS-L 封装技术，预计最早于明年推出，该技术支持面 积高达 4,719 平方毫米（约为光 ...

Core Viewpoint - NVIDIA's next-generation Rubin AI architecture will utilize the company's first SoIC packaging, indicating a significant shift in the hardware market with the integration of advanced components like HBM4 [1][5] Group 1: SoIC Packaging Development - TSMC is rapidly constructing factories in Taiwan to shift focus from advanced packaging (CoWoS) to SoIC, with expectations for NVIDIA, AMD, and Apple to release next-generation solutions based on this design [1][2] - SoIC allows for the integration of different chips, reducing internal circuit layout space and lowering costs, with AMD being an early adopter and Apple expected to follow with its M5 chip [2][3] - TSMC's SoIC production capacity is projected to reach 15,000 to 20,000 wafers by the end of this year, with plans to double that capacity next year [2][6] Group 2: NVIDIA's Rubin Architecture - The Rubin GPU will separate the GPU and I/O die, utilizing N3P and N5B processes respectively, and will integrate these components using SoIC packaging [2][5] - The Vera Rubin NVL144 platform is expected to deliver up to 50 PFLOPS of FP4 performance with 288 GB of HBM4 memory, while the NVL576 will provide up to 100 PFLOPS and 1 TB of HBM4e capacity [5] Group 3: Workforce and Production Adjustments - TSMC plans to adjust its workforce from 8-inch fabs to support advanced packaging facilities, aiming to recruit 8,000 new employees this year to reach a target of 100,000 [3] - The company is actively preparing for the integration of SoIC technology, which is seen as crucial for future developments in semiconductor packaging [3][6]

以下文章来源于腾讯科技 ，作者苏扬 郝博阳 腾讯科技 . 腾讯新闻旗下腾讯科技官方账号，在这里读懂科技！ 将投中网设为"星标⭐"，第一时间收获最新推送 算力永不眠。 作者丨苏扬 郝博阳 编辑丨 郑可君 来源丨腾讯科技 作为AI时代的"卖铲人"，黄仁勋和他的英伟达，始终坚信算力永不眠。 今天的GTC大会上，黄仁勋拿出了全新的Blackwell Ultra GPU，以及在此基础上衍生的应用于推 理、Agent的服务器SKU，也包括基于Blackwell架构的RTX全家桶，这一切都与算力有关，但接下 来更重要的是，如何将源源不断算力，合理有效地消耗掉。 在黄仁勋眼里，通往AGI需要算力，具身智能机器人需要算力，构建Omniverse与世界模型更需要源 源不断的算力，至于最终人类构建一个虚拟的"平行宇宙"，需要多少算力，英伟达给了一个答案—— 过去的100倍。 为了支撑自己的观点，黄仁勋在GTC现场晒了一组数据——2024年美国前四云厂总计采购130万颗 Hopper架构芯片，到了2025年，这一数据飙升至360万颗Blackwell GPU。 以下是腾讯科技整理的英伟达GTC 2025大会的一些核心要点： Blac ...

Core Viewpoint - NVIDIA's recent earnings report did not meet market expectations, leading to a decline in AI stocks, with supply chain sources indicating a reduction in advanced packaging orders from TSMC [1][2]. Group 1: NVIDIA's Product and Market Dynamics - NVIDIA's CEO Jensen Huang emphasized strong market demand for the Blackwell series, with gross margins expected to remain around 70% during the ramp-up phase [1]. - The upcoming GTC event will showcase new products like Blackwell Ultra and GB300, with expectations for faster integration based on previous experiences with GB200 [2]. - The transition from the Hopper architecture to Blackwell architecture is underway, with production challenges noted due to lower yield rates of the new CoWoS-L packaging technology [4]. Group 2: TSMC's Capacity and Order Adjustments - TSMC's advanced packaging capacity remains near full utilization, but there are indications of a potential decrease in orders as the lifecycle of NVIDIA's previous GPU generation ends [1][3]. - Reports suggest that TSMC's CoWoS average monthly capacity has dropped to 62,500 wafers, below the expected 70,000 wafers, with NVIDIA's monthly orders also reduced from approximately 42,000 to 39,000 wafers [3]. - Despite rumors of order cuts, TSMC has denied these claims, stating that demand for CoWoS remains strong and that any perceived reductions may be due to process upgrades and product transitions [2][3]. Group 3: Future Prospects and Industry Trends - TSMC is ramping up production at its newly acquired facilities to meet the growing demand for advanced packaging technologies like CoWoS-L and SoIC [4]. - The industry anticipates that the new Rubin GPU and Vera CPU developments will contribute positively to market dynamics, with production expected to begin early next year [2].