在当今高速发展的半导体行业中，数据传输速度和安全性已成为关键挑战。随着人工智能、 联网车辆、5G和物联网的爆发式增长，市场对高性能计算和低功耗芯片的需求激增，而内存 带宽与数据处理安全性的瓶颈日益凸显。在这一背景下，接口IP和安全IP技术成为行业突破 的核心驱动力，它们直接决定了芯片的效能、兼容性及抗攻击能力。 成立于1990年的Rambus公司，正是这一领域的先驱者。凭借其创新的高速接口技术，Rambus重新 定义了内存与系统间的数据传输标准，其DDR内存接口、HBM3/4和PCIe 5/6 等解决方案显著提升 了数据中心、边缘计算等场景的性能上限。同时，面对日益复杂的网络安全威胁，Rambus拥有许 多安全IP解决方案，比如信任根技术、安全协议引擎、内联(inline)密码引擎、后量子密码算法加速 器核等。这些丰富的安全和接口IP解决方案帮助Rambus构建了强大的产品组合。 7月9日，针对AI和汽车两大热门方向，Rambus于北京丽亭华苑酒店举办技术探讨会。届时，除了 Rambus 之 外 ， 其 他 行 业 合 作 伙 伴 包 括 M31 、 晶 心 科 技 、 Brightsight 、 ETAS ...

茂硅明确定位走利基型应用市场，锁定需高弹性与定制化的订单，强化与车用及工控客户的粘性。 联电通过结盟英特尔，在美国携手开发12nm技术，外媒更进一步披露，面对中国大陆成熟制程产能大 战，联电评估进军进先进制程，锁定以6nm技术生产更先进的WiFi、无线射频、蓝牙元件、AI加速器， 汽车使用的核心处理芯片。联电强调，将寻求合作伙伴关係，仍持续探索更先进的制造技术。 世界开拓特殊制程应用，耕耘碳化硅（SiC）及氮化镓（GaN）多年。氮化镓已量产，世界并参与汉磊 私募案，目标2026下半年开始量产8英寸碳化硅（SiC）晶圆制造，初期锁定工控与消费用产品，未来扩 展包括电动车、AI数据中心、绿能等应用。 力积电逐步脱离低毛利制程，寻求高附加价值的产品线。力积电董事长黄崇仁先前表示，2019年起即布 局Wafer-on-Wafer（WoW）3D堆叠技术，特别适用于边缘AI、车用电子与高性能计算（HPC）领域。 中国大陆晶圆代工厂大举新建产能，但中国台湾厂不跟着拼量。龙头台积电以先进制程独霸全球，通吃 苹果、AMD、英伟达、高通等国际大厂最先进芯片代工订单；联电、世界、力积电、茂硅等成熟制程 晶圆代工厂则与国际大厂联盟或 ...

Group 1 - The core concept of hybrid bonding technology is gaining traction among major semiconductor companies like TSMC and Samsung, as it is seen as a key to advancing packaging technology for the next decade [2][4][10] - Hybrid bonding allows for high-density, high-performance interconnections between different chips, significantly improving signal transmission speed and reducing power consumption compared to traditional methods [5][11] - The technology is particularly relevant for high bandwidth memory (HBM) products, with leading manufacturers like SK Hynix, Samsung, and Micron planning to adopt hybrid bonding in their upcoming HBM5 products to meet increasing bandwidth demands [10][12] Group 2 - TSMC's SoIC technology utilizes hybrid bonding, achieving a 15-fold increase in chip connection density compared to traditional methods, which enhances performance and reduces size [14][15] - Intel has also entered the hybrid bonding space with its 3D Foveros technology, which significantly increases the number of interconnections per square millimeter, enhancing integration capabilities [19] - SK Hynix and Samsung are actively testing and planning to implement hybrid bonding in their next-generation HBM products, with Samsung emphasizing the need for this technology to meet height restrictions in memory packaging [20][22] Group 3 - The global hybrid bonding technology market is projected to grow from $123.49 million in 2023 to $618.42 million by 2030, with a compound annual growth rate (CAGR) of 24.7%, particularly strong in the Asia-Pacific region [22]

Core Viewpoint - The semiconductor industry faces critical challenges in data transmission speed and security, driven by the explosive growth of AI, connected vehicles, 5G, and IoT, leading to increased demand for high-performance computing and low-power chips [1] Group 1: Industry Challenges and Innovations - The bottlenecks in memory bandwidth and data processing security are becoming increasingly prominent [1] - Interface IP and security IP technologies are identified as core drivers for breakthroughs in the industry, directly impacting chip performance, compatibility, and attack resistance [1] - Rambus, established in 1990, is a pioneer in this field, redefining data transmission standards between memory and systems with innovative high-speed interface technologies [1] Group 2: Rambus Solutions - Rambus offers solutions such as DDR memory interfaces, HBM3/4, and PCIe 5/6, significantly enhancing performance limits in data centers and edge computing [1] - The company provides a range of security IP solutions, including root of trust technology, security protocol engines, inline cryptographic engines, and post-quantum cryptography accelerators [1] - These comprehensive security and interface IP solutions contribute to a robust product portfolio for Rambus [1] Group 3: Upcoming Event - Rambus will host a technology discussion on July 9, 2025, in Beijing, focusing on AI and automotive sectors, featuring industry partners and technical experts [2][3] - The morning session will cover the latest interface and security IP solutions for AI and advanced applications, including quantum-safe encryption and various memory technologies [6] - The afternoon session will delve into automotive safety solutions, addressing trends and challenges faced by hardware and software designers in smart connected vehicles [7]

Core Viewpoint - The semiconductor industry faces critical challenges in data transmission speed and security, driven by the explosive growth of AI, connected vehicles, 5G, and IoT, leading to increased demand for high-performance computing and low-power chips [1] Group 1: Industry Challenges and Innovations - The bottlenecks in memory bandwidth and data processing security are becoming increasingly prominent [1] - Interface IP and security IP technologies are identified as core drivers for breakthroughs in the industry, directly impacting chip performance, compatibility, and attack resistance [1] Group 2: Company Overview - Rambus, established in 1990, is a pioneer in high-speed interface technology, redefining data transmission standards between memory and systems [1] - Rambus offers a robust product portfolio, including DDR memory interfaces, HBM3/4, and PCIe 5/6 solutions, significantly enhancing performance in data centers and edge computing [1] Group 3: Upcoming Event - Rambus will host a technology discussion on July 9, 2025, in Beijing, focusing on AI and automotive sectors, featuring industry partners and technical experts [2][3] - The event will cover the latest interface and security IP solutions for advanced applications, including quantum-safe encryption and various memory technologies [6] - The afternoon session will delve into automotive security solutions, addressing trends and challenges faced by hardware and software designers in smart connected vehicles [7]

Core Viewpoint - The article discusses the emergence of supernodes in high-performance computing, emphasizing their role in enhancing the efficiency of large-scale model training and inference through optical technology [1][2][21]. Group 1: Supernode Architecture and Performance - Supernodes provide a new solution for large-scale model training and inference, significantly improving efficiency by optimizing resource allocation and data transmission [1]. - The architecture of supernodes can be categorized into single-layer and two-layer designs, with single-layer architecture being the ultimate goal due to its lower latency and higher reliability [4][6]. - The demand for GPU power has surged with the exponential growth of model sizes, necessitating thousands of GPUs to work in tandem, which supernodes can facilitate [1][2]. Group 2: Challenges in Domestic Ecosystem - Domestic GPUs face significant performance gaps compared to international counterparts, requiring hundreds of domestic GPUs to match the power of a few high-end international GPUs [6][8]. - The implementation of supernodes in the domestic market is hindered by limitations in manufacturing processes, such as the 7nm technology [6]. Group 3: Development Paths for Supernodes - Two main development paths are proposed: increasing the power capacity of individual cabinets to accommodate more GPUs or increasing the number of cabinets while ensuring efficient interconnection [8][10]. - Optical interconnect technology is crucial for multi-cabinet scenarios, offering significant advantages over traditional copper cables in terms of transmission distance and flexibility [10][12]. Group 4: Optical Technology Advancements - The transition to higher integration optical products, such as Co-Packaged Optics (CPO), enhances system performance by reducing complexity and improving reliability [14][16]. - CPO technology can save 1/3 to 2/3 of power consumption, which is significant even though communication power is a smaller fraction of total GPU power [16][17]. Group 5: Reliability and Flexibility - The use of distributed optical switching technology enhances the flexibility and reliability of supernodes, allowing for dynamic topology adjustments in case of node failures [18][19]. - Optical interconnect technology simplifies the supply chain, making it more controllable compared to advanced process-dependent components [19][21]. Group 6: Future Outlook - With advancements in domestic GPU performance and the maturation of optical interconnect technology, the supernode ecosystem is expected to achieve significant breakthroughs, supporting the rapid development of artificial intelligence [21].

Core Viewpoint - The global semiconductor foundry 2.0 market revenue is projected to grow by 13% year-on-year in Q1 2025, reaching $72.29 billion, driven by the surge in demand for AI and high-performance computing (HPC) chips [1][4]. Group 1: Market Dynamics - The traditional semiconductor foundry model (foundry 1.0) is evolving into a technology integration platform, emphasizing vertical coordination and faster innovation, influenced by AI trends and system-level optimization [1]. - TSMC leads the market with a share of 35.3% in Q1 2025, achieving approximately 30% year-on-year revenue growth, followed by Intel and Samsung [4][6]. Group 2: OSAT and Advanced Packaging - OSAT suppliers are becoming a critical segment in the foundry 2.0 supply chain, with a nearly 7% year-on-year growth in Q1 2025, benefiting from TSMC's excess demand for AI-related CoWoS [4][5]. - Advanced packaging demand is increasing, with key players like ASE, SPIL, and Amkor enhancing their capacities [4]. Group 3: Non-Memory IDM and Light Mask Suppliers - Non-memory IDMs such as NXP, Infineon, and Renesas are experiencing a decline in revenue by 3% in Q1 2025, particularly in the automotive and industrial sectors, with recovery expected to be delayed until the second half of 2025 [5]. - Light mask suppliers are benefiting from the adoption of 2nm EUV technology and the increasing complexity of AI/Chiplet designs [5]. Group 4: Future Outlook - The foundry 2.0 ecosystem is expected to transition from a linear manufacturing model to a seamlessly integrated value chain, enhancing collaboration between design, manufacturing, and advanced packaging [8].

作 者 | Livy Investment Research 编译 | 华尔街大事件 在全球人工智能军备竞赛中， AMD（ NASDAQ： AMD ）长期以来一直落后于英伟达，其估值 反映出投资者对其在下一代高性能计算（"HPC"）和生成式人工智能部署领域竞争力的持续怀 疑，但这种情况可能很快就会开始 转变。 具体来说，AMD 近期发布了其下一代 Instinct MI350 系列 加速器，预计将于 2025 年下半年量 产，同时还发布了 MI400 系列加速器及其配套的" Helios "机架式基础设施平台的预览版。加上 其 ROCm 软件堆栈的持续改进，这些进展将继续增强 AMD 日益增长的雄心，即在全栈层面与英 伟达为持续推进的 AI 转型而精心打造的同类产品展开竞争。即将到来的产品升级周期可能会显 著缩小 AMD 的技术差距，从而释放潜在的盈利拐点，支持其股价的估值追赶。 然而，不稳定因素的加剧增加了长期人工智能支出环境出现动荡的可能性。这构成了一股反作用 力，可能会推迟甚至结构性地抑制AMD即将抓住的利用人工智能相关基础设施建设的机会，使其 在需求向下游应用层转移之前获得成功。 在6月12日AMD" ...

| 投资者关系活动类别 | 特定对象调研 分析师会议 | | --- | --- | | | 媒体采访 业绩说明会 | | | 新闻发布会 路演活动 | | | 现场参观  其他（反路演活动） | | 活动参与人员 | 万家基金：汪洋 | | | 国泰基金：邓时锋、丁小丹、钱晓杰 | | | 国海富兰克林：张瑞 | | | 平安养老：袁帅 | | | 长信基金：陈言午、黄振华 | | | 华宝基金：汤祺、张坤、袁银泉 | | | 沣谊投资：窦金虎 | | | 公司董事、副总经理：金逸中 | | | 公司董事会秘书、副总经理：张江山 | | | 公司证券事务代表：王英 | | 时间 | 2025 年 6 月 25 日-6 月 26 日 | | 地点 | 上海 | | 形式 | 反路演活动 一、公司的基本情况 | | | 公司成立于 1999 年，并于 2009 年上市，总部位于 浙江省台州市，是一家全球领先的含氟精细化学品制造 | | | 商，是行业内少数几家横跨无机及有机氟化工行业的企 | | 交流内容及具体问答记 | 业。以含氟技术为核心，公司已经覆盖的业务包括新型 | | 录 | 材料（新 ...

2024 年，公司海外业务增长较快，境外收入较 2023 年 增长了 32.03%，境外收入占比为 19.10%。其中，欧美地区 收入保持稳定增长，东南亚、拉美等地区收入增速较快。2025 年，公司将继续加大海外市场发展力度，增加国际市场的工 作人员，积极参加海外展会等推广活动，海外经销体系进一 步拓宽和下沉，进一步提升公司在全球范围内的影响力。 | | ☑特定对象调研 □分析师会议 | | | --- | --- | --- | | 投资者关系 | □媒体采访 □业绩说明会 | | | 活动类别 | □新闻发布会 □路演活动 | | | | □现场参观 | | | | □其他 (请文字说明其他活动内容) | | | 参与单位名称 | 平安资管顾皓卿、张旭欣、龚彦恺、童飞、王晶 | | | 及人员姓名 | 广发证券王钰翔、王娅婕、孟祥杰 | | | 时间 | 年 月 日 2025 6 26 | | | 地点 | 公司会议室 | | | 上市公司 | 财务总监、董事会秘书：张争 | | | 接待人员姓名 | | | | | 本次投资者关系活动以现场调研的方式进行，以会谈的 | | | | 形式进行了充分的沟通和 ...