Core Viewpoint - The article discusses the competitive landscape in semiconductor manufacturing, focusing on advancements by TSMC and Intel in their respective processes and technologies, particularly in the context of the A14 process node and High NA EUV lithography. TSMC Developments - TSMC is transitioning from FinFET to Nanosheet technology, with a focus on CFET (Complementary FET) devices for further miniaturization and power reduction [1][3] - TSMC showcased its first CFET transistor with a gate pitch of 48nm at the 2023 IEDM, marking a significant milestone in CFET technology [3] - The company is also exploring new interconnect technologies to enhance performance, including new via schemes and materials like graphene to reduce resistance and coupling capacitance [7] Intel Innovations - Intel's upcoming 14A process node, set for risk production in 2027, aims to reduce power consumption by up to 35% and improve performance per watt by 15% to 20% compared to the 18A node [8][9] - The introduction of Turbo Cell technology is designed to optimize critical paths in CPU and GPU designs, enhancing overall performance without compromising power efficiency [10][12] - Intel plans to utilize High NA EUV lithography for its 14A process, despite concerns over cost and complexity, while also maintaining a Low NA EUV alternative to mitigate risks [13][19] High NA EUV Strategy - TSMC has decided not to use High NA EUV for its A14 process due to cost concerns, opting for traditional 0.33 NA EUV technology instead [13][14] - Intel has installed a High NA EUV lithography machine and is committed to exploring its use in the 14A process, while ensuring compatibility with existing design rules to alleviate customer concerns [15][17] - The article highlights the ongoing debate over the cost-effectiveness of High NA EUV versus Low NA EUV, with Intel asserting that both processes can achieve similar yields [17][18]

Core Viewpoint - EUV technology is overcoming challenges such as high costs and complex optical systems, showing significant advantages in processes of 10nm and below, with recent advancements from major companies indicating a new phase of commercial application and development [1]. Group 1: High NA EUV Developments - Intel is the first chip manufacturer to purchase High NA EUV lithography machines, with each machine valued at €350 million, currently used for R&D purposes [3]. - Intel's early results show that High NA machines can complete tasks with fewer exposures and processing steps compared to earlier machines, indicating a strong commitment to leading in the High NA EUV era [3][4]. - imec demonstrated a 90% yield in electrical testing of 20nm spaced metal lines using High NA EUV lithography, confirming the technology's capability at such small dimensions [6][10]. Group 2: Competitive Landscape in DRAM - Micron has introduced its first EUV-based 1γ (1-gamma) 16Gb DDR5 devices, achieving a 20% reduction in power consumption and a 30% increase in bit density compared to previous generations [11][15]. - Micron's transition to EUV is expected to improve economic efficiency for new nodes, combining EUV with multiple patterning DUV technology [15][16]. - The competition among major memory manufacturers is intensifying as Micron adopts EUV, with Samsung and SK Hynix also investing in High NA EUV machines to enhance their competitive edge [17]. Group 3: EUV Mask Technology - Samsung has decided to procure EUV pellicles from Mitsui Chemicals to improve production efficiency, following challenges in yield for its 3nm process [22][23]. - The development of EUV pellicles is crucial for reducing pattern defects in chip manufacturing, with ongoing efforts to enhance the performance and lifespan of these films [21][25]. Group 4: Future of EUV Technology - The ongoing innovation in EUV technology is expected to lead to more efficient, precise, and cost-effective chip manufacturing processes, supporting the semiconductor industry's growth and competitiveness [29].