Core Viewpoint - Intel's EMIB interconnect solution demonstrates advantages over traditional 2.5D technology in advanced chip packaging design, showcasing its application in various products and its potential for next-generation chip production [1][17]. Group 1: EMIB Technology and Comparison - Intel's EMIB technology has been applied in several products, including Ponte Vecchio, Sapphire Rapids, Granite Rapids, Sierra Forest, and the upcoming Clearwater Forest series [1]. - Competitors like TSMC utilize 2.5D and 3D packaging technologies, which involve silicon interposers and TSV (Through-Silicon Vias) for interconnections, contrasting with Intel's smaller interconnect bridges [3]. - 2.5D packaging has drawbacks, such as additional costs for silicon interposers and increased complexity and reduced yield with larger chip sizes [8]. Group 2: Advantages of EMIB - EMIB technology eliminates the need for silicon interposers between chips and packages, allowing for flexible chip placement and integration [11]. - The key advantages of EMIB include improved layout flexibility, support for 2D and 3D scaling, cost-saving opportunities, and simplified design processes [14][16]. - Intel's EMIB-T technology enhances bandwidth and chip integration by incorporating TSVs, making it suitable for high-performance applications [13][20]. Group 3: Future Developments and Market Position - Intel is increasing investments in wafer fabrication and aims to establish a new era of advanced chip production in the U.S. with its 14A technology [17][31]. - The company showcased its scalable packaging capabilities with multi-chip products using 18A/14A nodes, Foveros 3D, and EMIB-T technology, setting standards for high-performance computing and AI [18][20]. - Intel's advanced packaging solutions are expected to intensify competition with TSMC's CoWoS solutions, which also integrate multiple HBM chips [18]. Group 4: Industry Collaboration and Customer Focus - Intel is developing a diverse ecosystem participation plan to accelerate product launch and enhance supply chain resilience [29]. - The recent advanced packaging chip demonstration targets external customers, particularly highlighting the advantages of the 14A process node designed for third-party clients [31]. - The success of Intel's advanced packaging technology will depend on securing orders from third parties, which is crucial for the adoption of its 14A technology [33].

Core Viewpoint - The article emphasizes the transformative potential of Laser-Induced Deep Etching (LIDE) technology in the semiconductor packaging industry, particularly in utilizing glass as a substrate for advanced packaging solutions. This technology addresses the increasing demands for high-density interconnections, efficient thermal management, and mechanical stability in semiconductor devices [2][19][22]. Group 1: Market Demand and Technological Advancements - The semiconductor industry's shift towards high-end chips like AI and HPC is driving the need for advanced packaging technologies that require higher bandwidth, lower power consumption, and smaller sizes [2]. - Glass is gaining attention as a promising material for semiconductor packaging due to its excellent thermal stability, electrical insulation, and optical transparency [3][19]. - There is a pressing demand for glass microstructures, including through-glass vias (TGV), blind vias, and microchannels, which are crucial for thermal management and high-density interconnections [2][3][19]. Group 2: Limitations of Traditional Glass Processing Techniques - Traditional glass processing methods, such as mechanical drilling and wet etching, have significant limitations, including the generation of defects, limited aspect ratios, and scalability issues [4][6]. - Mechanical drilling can induce high mechanical stress, leading to micro-cracks and compromised structural integrity [4]. - Wet etching methods struggle with aspect ratio control and are not suitable for mass production due to their complexity and cost [4][6]. Group 3: Advantages of LIDE Technology - LIDE technology combines laser modification and chemical etching to achieve high-precision glass microstructure fabrication, allowing for the creation of deep, narrow structures without defects [11][16]. - The two-step process of LIDE involves laser modification followed by wet etching, enabling the formation of complex microstructures with high aspect ratios and mechanical strength [10][11][16]. - LIDE technology supports the integration of various microstructures, such as TGVs, microchannels, and blind vias, on a single glass substrate, enhancing the functionality of semiconductor packages [13][19][22]. Group 4: Implications for Semiconductor Packaging - The integration of multiple microstructures using LIDE technology addresses the challenges of thermal management and sensor integration in high-power semiconductor devices [19][22]. - The formation of microstructures in glass substrates necessitates new requirements for the semiconductor supply chain and process integration, particularly in adapting back-end assembly and bonding technologies [20][22]. - Collaboration among material suppliers, equipment manufacturers, and semiconductor companies will be crucial for developing reliable and efficient processing systems as the industry transitions to complex glass substrate packaging [20][22]. Group 5: Future Outlook - LIDE technology is positioned to become a core driver of next-generation packaging technologies, solidifying glass materials' status as a mainstream substrate in high-end packaging applications [22].

Core Viewpoint - Morgan Stanley has raised its forecast for Google's TPU chip shipments for 2026 and 2027, expecting shipments to reach 3.7 million and 5 million units respectively, driven by TSMC's expanding CoWoS packaging capacity and strong market demand [1][3]. Group 1: Capacity Forecast Adjustments - Morgan Stanley has increased its CoWoS capacity forecasts for 2026 and 2027 by 8% and 13% respectively, reflecting TSMC's new capacity construction in the second half of 2026 and 2027 [1][3]. - TSMC's CoWoS capacity is expected to reach 115,000 wafers per month by the end of 2026, with external suppliers providing an additional 12,000 to 15,000 wafers per month [1][3]. Group 2: Demand Drivers - The increase in capacity is primarily driven by rising demand from the ASIC supply chain [1][3]. - The main shipments for 2026-2027 will come from TPU v7 (Ironwood) and v8 series (Broadcom's AX version and MediaTek's X version) [3]. Group 3: Company-Specific Insights - NVIDIA's CoWoS allocation for 2026 remains at 700,000 wafers, with slight adjustments in product mix due to HBM4 readiness issues [4]. - AMD's CoWoS forecast remains unchanged at 90,000 and 120,000 wafers for 2026 and 2027, respectively, with potential delays in the MI450 project [4]. - AWS's Trainium project has seen a slight reduction in expected shipments for 2026, now projected at 2.1 million units [5]. Group 4: Outsourcing Trends - The outsourcing ratio for packaging has increased, benefiting equipment suppliers [6][7]. - TSMC will focus on key GPU and AI ASIC projects, leaving smaller projects to packaging houses like ASE and Amkor [7]. - Equipment suppliers are expected to see a year-on-year increase in demand for CoWoS, with new capacity projected to grow by 40,000 to 50,000 wafers per month [7].

Core Viewpoint - TSMC's transition to 2nm GAA technology marks a significant advancement in semiconductor manufacturing, with expectations of increased production capacity and efficiency, while the real bottleneck lies in advanced packaging technologies like CoWoS, rather than transistor density [1][40]. Group 1: 2nm Technology and Production - TSMC's 2nm technology is set to begin mass production in Q4 2025, utilizing nanosheet transistors that enhance performance and power efficiency across all process nodes [1]. - Compared to the 3nm N3E process, the 2nm technology offers a 10% to 15% speed increase at the same power level, and a 25% to 30% reduction in power consumption while increasing chip density by over 15% [2]. - TSMC plans to establish five 2nm fabs in Kaohsiung, with a total investment exceeding NT$1.5 trillion, creating 7,000 high-tech jobs [2]. Group 2: Advanced Packaging Challenges - The CoWoS (Chip-on-Wafer-on-Substrate) technology is critical for integrating advanced chips with HBM memory; without it, even the most advanced chips could become excess inventory [3][40]. - Advanced packaging capabilities are becoming the key limiting factor in the AI semiconductor sector, overshadowing the importance of transistor density [40]. - TSMC's CEO confirmed that supply constraints are expected to persist until 2025, despite plans to double production capacity in 2024 and 2025 [21]. Group 3: Market Dynamics and Competitors - NVIDIA is projected to secure over 70% of the CoWoS-L capacity, creating a structural advantage, while companies like Broadcom are also vying for a share of the remaining capacity [23][40]. - The AI chip market is evolving, with companies like Broadcom capturing approximately 70% of the custom AI accelerator market, and their AI revenue expected to reach $12.2 billion in FY2024, a 220% year-over-year increase [32]. - The competition in the AI chip market is intensifying, with major players like AMD and Intel also making significant strides in developing their own AI hardware solutions [35][37]. Group 4: Future Developments and Innovations - TSMC is diversifying its advanced packaging technologies, including the development of CoPoS (Chip-on-Package-on-Substrate) technology, expected to be introduced after 2027 [24]. - The transition from FinFET to GAA technology introduces new manufacturing complexities, requiring specialized equipment and processes, which could extend production timelines [11][40]. - The demand for advanced packaging is expected to grow significantly, with OSAT (Outsourced Semiconductor Assembly and Test) companies also ramping up their capabilities to meet the increasing needs of AI chip production [43].

Summary of Semiconductor Industry Conference Call Industry Overview - The semiconductor industry is recovering from a down cycle that began in 2021 and is entering a new up cycle driven primarily by AI computing demand rather than traditional consumer electronics demand [1][5] - AI computing demand remains strong, with high GPU rental prices and utilization rates, contrasting with the low utilization rates seen during the internet bubble, indicating that AI development is not a bubble and will continue to drive demand for semiconductor equipment and materials for an extended period [1][7] Key Insights - Significant price increases for DRAM and NAND storage chips are expected in Q3 2025, with a further rise anticipated in Q1 2026 due to overseas cloud providers' aggressive purchasing and slow upstream capacity increases, presenting market share opportunities for domestic storage manufacturers [1][8] - China's domestic production rates for mobile chips, computer chips, and advanced GPU computing chips are currently low, but increasing domestic production rates will create substantial market expansion opportunities, especially in processes of 14nm and below [1][10] - New technology applications, such as advanced packaging, are expected to bring incremental opportunities for semiconductor equipment and materials, with TSMC's capital expenditures indicating significant demand for related equipment [1][11] Market Dynamics - The semiconductor industry typically experiences cycles approximately every five years, with the current phase indicating an expansion stage as evidenced by the performance and sales data of many listed companies [4][5] - AI computing demand is driving the semiconductor equipment market, with core companies like NVIDIA playing a crucial role in this process. The demand for advanced GPUs and storage is filling up wafer fab capacities, leading to a substantial increase in equipment orders [6][12] Future Projections - The AI computing demand is expected to remain in a state of supply shortage, with GPU rental prices high and utilization rates robust, suggesting that this demand will continue to drive the market for a considerable time [7][12] - The expansion of the storage cycle and advancements in autonomous control in advanced processes are anticipated to create significant investment opportunities in the equipment sector for 2026 [2][14] Investment Opportunities - The listing of domestic storage giants is accelerating, primarily aimed at financing for capacity expansion, which will drive the development of the entire equipment sector [15] - The increasing complexity of processes is expected to significantly increase the demand for equipment, potentially doubling or tripling in some areas, thereby supporting revenue and performance growth for related equipment manufacturers [16] Policy and Domestic Production - Government support for domestic equipment replacement is evident, with incentives for purchasing domestic equipment and strategic focus on self-sufficiency in the semiconductor industry [17][18] - Domestic equipment manufacturers have reached mainstream standards in mature processes and are making strides in advanced processes, indicating a significant shift towards domestic production capabilities [13][18] Valuation and Investment Strategy - The current valuation of semiconductor equipment is relatively high compared to traditional industries, but the growth momentum is clear, supported by commercial validation and government policies [19] - Historical data shows that from 2019 to 2021, company performance grew significantly, and future growth is expected to continue, suggesting that current price-to-earnings and price-to-book ratios are below historical medians, presenting investment opportunities [20] Direct Investment Products - The CSI Semiconductor Materials and Equipment Theme Index is a highly focused tool for investors looking to capitalize on the semiconductor industry's upstream, with over 80% concentrated in equipment and materials, making it an ideal choice for direct investment in the semiconductor sector [21]

SEMICON Japan 走访见闻 20251222 2026 年半导体行业迎来存储超级周期，DRAM 资本开支迅速增长超 20%，NAND 主要集中于升级投资，利好东京电子、Kokusai Electric 等企业。 先进工艺升级驱动后道设备需求，Advantest、Teradyne 等受益。3 纳米和 2 纳米工艺光刻强度提升，ASML 和 LaserTech 等公司有望受益。 日本企业预测 2026 年中国市场持平或微增，长存和长兴表现突出，未 来资本开支仍有上行空间。光纤光缆供应紧张，藤仓、住友电工和古河 电气产能全满。 英特尔 CEO 更换后股价上涨，可能通过先进封装技术或代工业务实现复 苏，现有产品竞争力或回升，投资者对此高度关注。 软银押注 OpenAI 存在争议，出售英伟达股票并承担高杠杆风险，投资 收益具有不确定性。WSTS 预测 2026 年全球半导体行业加速增长，总 规模接近 1 万亿美元。 中国企业市场份额不断提升，预计到 2026 年底市占率可能从 23%- 24%提高到 30%左右，显著高于东京电子等海外厂商的预期。 台积电 CoWoS 产能受限仍是全球 AI 发展的瓶颈之一，预 ...

AI 与汽车浪潮驱动先进封装腾飞 安靠技术（AMKOR） 股票研究 /[Table_Date] 2025.12.18 (AMKR.O) [Table_Industry] 海外信息科技 | | |  | 安靠技术（Amkor）首次覆盖报告 | | [Table_Industry] 海外信息科技 | | --- | --- | --- | --- | --- | --- | | [姓名table_Authors] | 电话 | 邮箱 | 登记编号 | [Table_Invest] | | | 秦和平(分析师) | 0755-23976666 | qinheping@gtht.com | S0880523110003 | 评级： | 增持 | | 李潇(分析师) | 021-23183060 | lixiao4@gtht.com | S0880525070003 | | | | 龚浩(研究助理) | 021-23183306 | gonghao2@gtht.com | S0880125090016 | [当前价格 Table_CurPrice] (美元)： | 38.87 | 本报告导读： 完备先进封装完整产品谱 ...

Core Insights - The strategic partnership between Chenxian Optoelectronics and Xinyi Chang focuses on overcoming technical bottlenecks in glass-based Micro-LED technology, particularly in mass transfer processes, with applications in commercial displays, smart meetings, transparent displays, and automotive displays [1][2] - Glass-based Micro-LED technology has transitioned from laboratory validation to accelerated industrialization, showcasing advantages such as high reliability, structural simplicity, ultra-high pixel density, high light transmittance, and micron-level stitching precision [1] - The demand for AI chip computing power is driving the trend of glass substrates replacing traditional organic substrates, with major semiconductor and technology companies like AMD, Apple, NVIDIA, Intel, TSMC, and Microsoft investing in glass-based solutions [1] Company Developments - Chenxian Optoelectronics has invested over 4 billion yuan in building the first large-size TFT glass-based Micro-LED production line in Chengdu, which is expected to generate over 100 billion yuan in output value for the upstream and downstream industry chain upon full production [2] - The collaboration between Chenxian Optoelectronics and Xinyi Chang represents a significant milestone in transitioning from "single-point technological breakthroughs" to "full industry chain collaborative innovation" in the glass-based Micro-LED sector [2] - The deepening cooperation is anticipated to accelerate the localization of core equipment and process iterations, contributing to the establishment of a self-controlled industrial ecosystem in China's high-end display field [2]

Core Viewpoint - The rapid proliferation of AI applications is driving demand for advanced packaging technologies in the semiconductor industry, with TSMC's CoWoS becoming a well-known solution. The company is also developing next-generation packaging technologies like CoPoS and CoWoP to enhance area utilization and cooling efficiency [1][10]. Group 1: Advanced Packaging Technologies - CoWoS (Chip-on-Wafer-on-Substrate) integrates multiple chips on a substrate to reduce space and improve performance, particularly for AI chips requiring high bandwidth and low latency [2][6]. - TSMC's CoWoS-L variant has seen a significant increase in demand, accounting for approximately 60% of CoWoS sales, due to its lower cost and ability to integrate passive components [6][9]. - The next-generation packaging technologies, CoPoS and CoWoP, aim to reduce costs and improve efficiency, with CoPoS utilizing a rectangular panel to enhance area utilization [10][11]. Group 2: Market Growth and Projections - The Taiwanese semiconductor packaging industry is projected to reach NT$710.4 billion by 2025, with a CAGR of 13.9%, and further growth to NT$759 billion by 2026, driven by AI and HPC infrastructure demands [1][2]. - TSMC's advanced packaging capacity is expected to grow significantly, with CoWoS capacity increasing by over 80% and SoIC capacity by more than 100% from 2022 to 2026 [2][9]. Group 3: Industry Challenges and Developments - The semiconductor industry faces challenges in meeting the increasing demand for advanced packaging, necessitating collaboration and innovation among manufacturers [10]. - TSMC is expanding its advanced packaging facilities in the U.S. and Taiwan, with plans to start testing CoPoS by 2026 and mass production by 2028 [8][9]. - The shift towards advanced packaging is shortening the time from design to mass production, reducing the development cycle from approximately 1.5 years to less than a year [9][10].

Core Insights - Intel's optimism regarding its wafer foundry division is highlighted, particularly with the upcoming 18A process technology and advanced packaging products [1][2] - The company is currently mass-producing Panther Lake chips, set to launch on January 5, with yield rates improving but not yet at optimal levels [1] - Intel's internal facilities are engaging with external customers to assess interest in the 18A-P and 18A-PT process nodes, which are showing promising early progress [2] Group 1 - Intel's 18A process technology is maturing, and the company is looking to reconnect with external clients to gauge their interest [2] - Advanced packaging technologies are seen as a significant opportunity for Intel's wafer foundry, with some clients achieving good results, indicating a shift towards Intel's solutions as alternatives to TSMC's products [2][3] - The company acknowledges a potential underestimation of the advanced packaging business's potential, driven by external demand due to capacity constraints at TSMC [2] Group 2 - Intel's wafer foundry division has not seen a significant drop in optimism compared to previous months, with ongoing discussions about improving the division's offerings [3] - External customers are considering Intel's chip and packaging solutions, contributing to management's confidence in the foundry division's ability to enhance its performance [3]