公众号记得加星标⭐️，第一时间看推送不会错过。 在人工智能与大数据技术驱动存储需求指数级增长的产业变革期，新存科技于近日重磅推出新一 代内存级存储芯片NM111。这款采用全自主知识产权三维集成技术的突破性产品，凭借64Gb超 大容量、低延迟及高耐久性等核心指标，达到国际领先水平，为我国构建自主可控的存储产业生 态注入强劲动能。 作为国内首款具备内存级性能的新型存储芯片，NM111通过先进的三维垂直堆叠架构与纳米级互联 技术，实现64Gb超大容量，存储密度较传统DRAM提升数倍。该芯片支持内存语义访问，支持随机 读写操作，读取延时低至百纳秒，带宽高达3.2Gbps，可广泛应用于服务器内存扩展、数据库缓存等 场景。其突破性的非易失特性更可实现断电数据保护，在元数据存储等关键领域将系统性能提升至全 新维度。 推荐阅读 新存科技于2024年9月和2025年初分别发布首款64Gb国内最大容量三维新型存储级芯片NM101，和1 28Gb的升级产品NM102。此次发布的NM111属于全新持久内存芯片系列，在性能和可靠性方面实现 全面提升。基于公司在设计、材料、工艺、器件、测试等多方面的持续创新，NM111耐久度较前作 提升 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 来源：内容编译自techspot。 随着 Nvidia 持续加速发布驱动程序更新，即使是老牌游戏硬件最终也会难以跟上。即将发布的更新 将终止对三种 GPU 架构的官方支持，但受影响的显卡不会立即停止工作。 Nvidia 刚刚确认，即将发布的 580 系列显示驱动程序将是最后一款支持基于 Maxwell、Pascal 和 Volta 微架构 GPU 的驱动程序。580 版本发布后，大量老款 GeForce 显卡将不再获得错误修复或潜 在的（尽管可能性不大）代码优化。 我的电脑搭载了 GeForce RTX 4080 Super，运行着 566.36 Game Ready 驱动，运行流畅，我近期 不打算更新。毕竟，这配置"足够好"地运行《毁灭战士：黑暗时代》，帧率稳定在 100+ FPS，支持 DLSS 画质，而且无需依赖 AI 帧生成。 参考链接 https://www.techspot.com/news/108523-nvidia-drop-driver-support-maxwell-pascal-volta-gpus.html *免责声明：本文由作者原创。文 ...

Core Viewpoint - Samsung is facing challenges in its semiconductor business due to setbacks in HBM and lagging wafer foundry capabilities, leading to performance issues and loss of market leadership in DRAM to SK Hynix and TSMC [1][2] Group 1: Semiconductor Production Adjustments - Samsung has officially postponed the mass production of 1.4nm semiconductors to 2029, two years later than previously planned, in an effort to enhance the profitability of its 2nm and higher processes [4] - The decision to delay 1.4nm production is seen as a response to a decline in operational rates that resulted in a loss of 4 trillion KRW for Samsung's foundry division last year [4] - Samsung plans to focus on stabilizing its 2nm process and improving the operational rates of its 4, 5, and 8nm processes to ensure profitability [5] Group 2: HBM Supply and Partnerships - Samsung is negotiating with Nvidia for the supply of HBM3E 12-layer chips, emphasizing that its quality is competitive with rivals [7] - The company has also secured supply agreements with AMD for its AI accelerator MI350X series, which has boosted confidence in Samsung's HBM3E 12-layer memory quality [7] - Nvidia is expected to begin shipping its Blackwell Ultra AI accelerator by the end of this year, with initial supply contracts already established with SK Hynix and Micron [8] Group 3: Market Dynamics and Competitive Position - The demand for Blackwell Ultra is anticipated to grow not only next year but also in the following year, as the initial production of the next-generation Vera Rubin is likely to be limited [10] - Samsung's entry as a third major supplier of HBM3E 12-layer memory could provide Nvidia with leverage in price negotiations with existing suppliers [10] - The average selling price (ASP) of HBM3E provided by SK Hynix is reportedly about 60% higher than that of the 8-layer version, indicating a competitive pricing environment [10]

公众号记得加星标⭐️，第一时间看推送不会错过。 来源：内容来自 彭博社 。 这项半导体制造条款被纳入一份近900页的法案，该法案代表了美国总统唐纳德·特朗普经济议程的核 心。众议院议员目前已准备好审议该法案，目标是在7月4日之前将其提交给特朗普签署。 增加税收抵免额度将增强《2022年芯片与科学法案》规定的一项关键激励措施。该法案是美国总统乔 ·拜登签署的一项跨党派法案。该计划还包括390亿美元的拨款和高达750亿美元的制造业项目贷款， 旨在在数十年来生产转移到亚洲之后，提振美国半导体产业。 这项税收抵免没有上限，其成本很可能已经高于其他形式的补贴——这取决于《芯片法案》刺激的投 资规模。几乎在所有情况下，这项税收抵免都将占到任何一家公司（包括那些未获得拨款的公司）获 得激励的最大份额。该拨款计划的主要受益者包括英特尔、台积电、美光科技和三星电子。 特朗普今年早些时候呼吁废除《芯片法案》，但两党议员都不愿取消这些补贴，因为这些补贴为各自 选区提供了高薪工作，而芯片行业被视为对国家安全至关重要。与此同时，美国商务部继续实施这项 拨款计划，同时敦促加大投资力度，并修改了耗时数月谈判的奖励条款。 到目前为止，特朗普 ...

除了新建晶圆厂外，美光公司还将扩建其位于弗吉尼亚州马纳萨斯的工厂。目前，该工厂生产用于汽 车、航空航天、国防和工业应用的内存芯片。升级后，该工厂将获得产能以及先进的封装能力，可在 美国组装HBM内存堆栈。不过，美光公司只有在其位于爱达荷州博伊西的晶圆厂提高DRAM晶圆产 量 后 ， 才 会 在 其 弗 吉 尼 亚 工 厂 增 加 HBM 产 能 。 尽 管 如 此 ， 预 计 美 光 公 司 将 在 美 国 生 产 HBM5 或 HBM6。 公众号记得加星标⭐️，第一时间看推送不会错过。 来源：内容编译自tomshardware。 美光公司本月宣布了新的美国扩张战略， 将投资计划扩大至 1.5 亿美元，计划在弗吉尼亚州建造一 座 HBM 封装工厂，并投资约 500 亿美元用于研发。美光公司本月透露，该公司多年来在美国的首 座新晶圆厂将于 2027 年下半年投入运营。 继2022年8月《芯片与科学法案》颁布后，美光科技公布了重大计划，将在爱达荷州和纽约州投资超 过1150亿美元建设新晶圆厂，目标是未来十年在美国生产40%的DRAM产品。根据新计划，美光科技 计划在美国政府的支持下，在未来20多年内投资2000亿 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 来源：内容 编译自 pcgamesn 。 据最新传闻，新款AMD Ryzen CPU 的主频可能达到甚至超过 7GHz，这代表着其较 Zen 4 和 Zen 5 架构有了巨大的飞跃。此前有传闻称，下一代 AMD 处理器的主频只有在"非常"保守的估计下才会超 过 6GHz。 据报道，英特尔正在研发一款新的52 核 CPU ，这给AMD带来了压力，迫使其推出重大产品。此前 已有传言称，AMD 将无法满足英特尔的高核心数量，Zen 6 架构最多只能支持 24 个核心，而Zen 7 架构则可能支持 32 个核心。然而，尽管 AMD 的下一代 CPU 核心数量似乎不如英特尔，但 AMD 似乎正在用更快的核心数量来弥补这一不足。 YouTube 技 术 泄 密 者 " 摩 尔 定 律 已 死 " （ MLID ） 此 前 声 称 曾 与 AMD 工 程 师 讨 论 过 AMD Zen 6 CPU，并声称当时关于6GHz 以上频率的传闻"非常保守"。此后，MLID 的主持人继续与 Alderon Games 的一位客座游戏开发者讨论 AMD 的 Zen 6 架构，并暗示 AM ...

Core Insights - The article discusses the exponential growth of AI models, reaching trillions of parameters, highlighting the limitations of traditional single-chip GPU architectures in scalability, energy efficiency, and computational throughput [1][7][8] - Wafer-scale computing has emerged as a transformative paradigm, integrating multiple small chips onto a single wafer to provide unprecedented performance and efficiency [1][8] - The Cerebras Wafer Scale Engine (WSE-3) and Tesla's Dojo represent significant advancements in wafer-scale AI accelerators, showcasing their potential to meet the demands of large-scale AI workloads [1][9][10] Wafer-Scale AI Accelerators vs. Single-Chip GPUs - A comprehensive comparison of wafer-scale AI accelerators and single-chip GPUs focuses on their relative performance, energy efficiency, and cost-effectiveness in high-performance AI applications [1][2] - The WSE-3 features 4 trillion transistors and 900,000 cores, while Tesla's Dojo chip has 1.25 trillion transistors and 8,850 cores, demonstrating the capabilities of wafer-scale systems [1][9][10] - Emerging technologies like TSMC's CoWoS packaging are expected to enhance computing density by up to 40 times, further advancing wafer-scale computing [1][12] Key Challenges and Emerging Trends - The article discusses critical challenges such as fault tolerance, software optimization, and economic feasibility in the context of wafer-scale computing [2] - Emerging trends include 3D integration, photonic chips, and advanced semiconductor materials, which are expected to shape the future of AI hardware [2] - The future outlook anticipates significant advancements in the next 5 to 10 years that will influence the development of next-generation AI hardware [2] Evolution of AI Hardware Platforms - The article outlines the chronological evolution of major AI hardware platforms, highlighting key releases from leading companies like Cerebras, NVIDIA, Google, and Tesla [3][5] - Notable milestones include the introduction of Cerebras' WSE-1, WSE-2, and WSE-3, as well as NVIDIA's GeForce and H100 GPUs, showcasing the rapid innovation in high-performance AI accelerators [3][5] Performance Metrics and Comparisons - The performance of AI training hardware is evaluated through key metrics such as FLOPS, memory bandwidth, latency, and power efficiency, which are crucial for handling large-scale AI workloads [23][24] - The WSE-3 achieves peak performance of 125 PFLOPS and supports training models with up to 24 trillion parameters, significantly outperforming traditional GPU systems in specific applications [25][29] - NVIDIA's H100 GPU, while powerful, introduces communication overhead due to its distributed architecture, which can slow down training speeds for large models [27][28] Conclusion - The article emphasizes the complementary nature of wafer-scale systems like WSE-3 and traditional GPU clusters, with each offering unique advantages for different AI applications [29][31] - The ongoing advancements in AI hardware are expected to drive further innovation and collaboration in the pursuit of scalable, energy-efficient, and high-performance computing solutions [13]

Core Viewpoint - The article discusses the recovery of the semiconductor market as manufacturers clear inventory, leading to rising prices and delivery times for analog chips [2][3]. Group 1: Market Dynamics - Analog chip prices and delivery times are increasing as manufacturers address inventory backlogs [2]. - Texas Instruments (TI) is raising the production process of various analog components by 30%, with some data converter component prices doubling [2]. - TI is increasing the output of 300mm wafer analog components at its Richardson, Texas facility and plans to invest $60 billion to build three new fabs [2]. Group 2: Future Market Outlook - The German distribution trade group FBDi anticipates market improvement in the second half of 2025 due to reduced inventory [3]. - Supply chain resilience has become a priority for companies post-COVID, emphasizing the need for robust risk management strategies [3]. - Generative AI is increasingly applied in supply chain management, enabling continuous analysis of large datasets to identify potential risks and generate insights [3]. Group 3: Distributor Insights - UK distributor Anglia's marketing director indicates that market conditions are improving, with suppliers concerned about potential order backlogs due to expected longer delivery times later in the year [4].

Core Viewpoint - The next significant leap in semiconductor packaging will require a series of new technologies, processes, and materials that will collectively achieve an order-of-magnitude performance improvement, which is crucial for the AI era [1]. Group 1: Advances in Cooling Technologies - Liquid cooling technology at the chip level is emerging as forced air cooling reaches its limits, with up to 40% of power used for current delivery and heat dissipation [4]. - TSMC's silicon integrated micro-cooler (IMEC-Si) is being tested for reliability, designed to handle over 3,000 watts of uniform power dissipation under specific conditions [6]. - The demand for direct liquid cooling is increasing, with innovative concepts like using chips as coolants being proposed [7]. Group 2: Hybrid Bonding and Interconnects - Hybrid bonding with fine-pitch multilayer redistribution layers (RDL) is gaining attention as a cost-effective solution for high-speed interconnects [14]. - Intel's hybrid bonding can achieve spacing as small as 1µm, which is critical for advanced applications [5][17]. - The transition from traditional dielectric materials to polymer/copper hybrid bonding is being explored to enhance performance [16]. Group 3: Backside Power Delivery - Backside power delivery significantly reduces voltage drop related to transistor power supply, but it also exacerbates heat issues [19]. - IBM has developed an anisotropic model for precise heat transfer calculations in backend stacks, emphasizing the importance of thermal considerations in design [21]. - The implementation of backside power delivery is expected to lead to a 10% to 30% reduction in thermal losses [23]. Group 4: Co-Packaged Optical Devices - The demand for faster data networks is driving the integration of optical engines with GPUs and HBM in a single package, significantly increasing data transmission speeds [26]. - Co-packaged optical devices (CPO) are expected to achieve a 32-fold increase in bandwidth by bringing optical engines closer to processors [26]. - However, challenges remain regarding thermal management and warpage sensitivity in CPO implementations [28].

Core Viewpoint - Nanchip Technology (stock code: 688484) has launched a new high-integration multi-port mobile power supply solution, which includes discrete protocol chips SC2006A & SC2007A, as well as a three-in-one SoC solution SC2016A & SC2017A, covering a full power range of 22.5W-140W, supporting various application scenarios [1][3]. Market Overview - The mobile power supply market is expanding due to the increasing popularity and intelligence of mobile electronic devices, with the market size in China expected to reach $1.046 billion in 2024, accounting for over 30% of the global market [3]. - The demand for integrated charging solutions is rising, leading to the introduction of products that support multi-port charging, wired and wireless compatibility, and higher power supply for laptops [3]. Product Features - The SC2006A and SC2007A chips are designed for complex scenarios requiring customized logic, supporting various fast charging protocols and ensuring system stability through multiple protection mechanisms [4][9]. - The SC2016A and SC2017A SoC solutions integrate PD, MCU, and Charger, simplifying system design for applications below 100W [7][11]. Safety and Compliance - Starting from August 2024, China will implement mandatory 3C certification management for mobile power supplies to ensure safety and reliability standards are met [3]. - Nanchip Technology's products are designed to help clients achieve 3C certification while enhancing product integration and safety features [3][11]. Cost Efficiency - The SC2006A and SC2007A chips utilize an ARM Cortex M0 core, providing ample MCU resources at minimal cost, and support low standby current of 10μA in shipping mode [4][9]. - These chips are optimized for cost-effectiveness while maintaining high performance and safety standards [4][11].