公众号记得加星标⭐️，第一时间看推送不会错过。 英特尔的季度财报让公司及其股价在经历了数月的乐观情绪后回归理性。尽管英特尔的营收和利润超 出预期，令投资者感到惊喜，但令人失望的季度业绩预测却导致股价大幅下跌。周五，英特尔股价收 于45.07美元，当日下跌17%，创下自2024年8月2日以来的最大单日跌幅，当日股价暴跌26%。 该报告提醒人们，尽管有政府支持并与英伟达建立了备受瞩目的合作伙伴关系，英特尔仍然深陷危机 之中，复苏之路依然漫长。 过去六个月对英特尔股东来说简直是美梦成真。在经历了多年业绩未达标、战略失误和市场份额下滑 之后，英特尔股价在9月中旬开始反弹，涨幅超过118%，并在1月22日创下近五年来的新高。 投资者乐观情绪源于多方面因素。首先是去年四月英特尔领导层的重组，以及陈立步(Lip-Bu Tan)被 任命为首席执行官。作为半导体行业最具影响力的人物之一，陈立步上任时传递了一个明确的信息： 重塑英特尔的工程文化，并将公司重心从短期财务业绩转向卓越的产品和长期战略。伴随他上任而来 的裁员——约2.2万名员工，占英特尔员工总数的20%左右——也让投资者相信，英特尔正在变得更 加精简高效、纪律严明。 ...

Core Viewpoint - The article discusses the process of generating a Process Design Kit (PDK) for digital standard cell libraries, emphasizing the importance of accurate modeling and design rules in semiconductor manufacturing [1][9]. Group 1: PDK Generation Process - The first step in PDK generation is defining the Back End of Line (BEOL) stacking structure, which includes the number of metal and via layers, conductor and dielectric materials, and the geometries suitable for the technology node [1]. - After defining the BEOL structure, electrical characteristics for each layer are simulated, and results are recorded in BEOL parasitic parameter files [1]. - The next critical step in PDK development involves designing and developing N-channel and P-channel FET device models, which form the foundation of the standard cell library [1]. Group 2: Design Rules and Layout - Design rules for minimum metal lengths, spacing between metal/via, and end-to-end spacing are documented in technology files (.tf) or Layout Exchange Format (LEF) files [2][3]. - The layout design of standard cells is compact, limiting internal wiring to lower BEOL layers (typically M1-M3) and middle interconnect layers (MOL) [7]. - A layout versus schematic (LVS) check is performed after layout completion to ensure the layout matches the schematic and adheres to design rules [7]. Group 3: Device Simulation and Characterization - Device characteristics are simulated using TCAD tools, with DC and AC characteristics characterized through various models, including BSIM [5]. - As technology nodes shrink, transistor architectures have evolved, with FinFET and GAAFET structures requiring specific BSIM-CMG templates for accurate modeling [5]. - The final step involves developing a standard cell library that includes circuit schematics for each cell, which is essential for layout and simulation [5]. Group 4: Parasitic Parameter Extraction - Parasitic parameter extraction captures MOL and lower BEOL layers, represented as RC SPICE netlists, which are crucial for performance evaluation during layout simulations [8]. - The information generated from these netlists is stored in Liberty (.lib) files, aiding EDA tools in assessing design performance during module layout and routing simulations [8]. - Accurate parasitic modeling and standard cell characterization are vital for reliable timing and power analysis in digital integrated circuit design [9].

Core Viewpoint - The choice of TSMC as a foundry partner by Nvidia and AMD has proven to be a significant investment, especially in the context of the current AI industry where chip supply is a major bottleneck [1][2][3]. Group 1: Importance of TSMC - TSMC is recognized as the largest foundry in the AI supply chain, playing a crucial role alongside manufacturers like Nvidia and AMD [4]. - The strong relationships TSMC maintains with its partners are a key reason why companies prefer TSMC over alternatives, even when faced with attractive options from competitors like Intel [4]. Group 2: Nvidia's Commitment - Nvidia's CEO Jensen Huang expressed confidence in becoming TSMC's largest customer, a promise he made despite initial setbacks in technology [2]. - Nvidia's success, with a market valuation of $5 trillion, is attributed to its close relationship with TSMC, which has granted Nvidia exclusive access to certain technologies and a steady supply of chips [2]. Group 3: AMD's Strategic Decision - AMD's CEO Lisa Su highlighted the decision to trust TSMC as a major strategic move, which has led to significant gains in market share in both client and server segments [3]. - AMD's shift from GlobalFoundries to TSMC as its primary manufacturing partner has been pivotal in its success, contrasting with Intel's struggles in its internal foundry operations [3].

以下文章来源于西门子EDA ，作者SIEMENS 西门子EDA . 面对复杂交织的系统级难题，任何单点工具的优化都显得杯水车薪。西门子EDA的整个设计流程 基于系统技术协同优化（STCO）的理念，贯穿整个3D IC的设计、验证和制造全流程，追求系 统层面的整体优化。 西门子EDA IC 封装产品客户技术经理 电子领域的创新步伐正在不断加快。为了让我们的客户能够加快推出改变生活的创新产品，并成为市场 的领导者，我们致力于提供世界上最全面的电子设计自动化 (EDA) 软件、硬件和服务组合。 全球半导体产业正从旷日持久的竞速赛，转向以创新为核心的全新范式。在这场革命中， Chiplet（小芯片）技术来到了聚光灯下，它主张将复杂系统分解为模块化的小芯片，通过先进 封装技术进行异构集成，从而开辟了一条通往更高性能密度的路径。 随着设计复杂度指数级增长，Chiplet技术要求EDA软件、IP供应商、晶圆厂和封装厂之间达成 深度协同。因此，Chiplet技术的兴起，本质上是一场围绕"系统级最优化"的生态革新。在此背 景下，作为芯片设计的基石，EDA软件的角色与能力亟需进化。产业界需要的不仅仅只是单点 工具创新，而是能够应对 ...

Core Viewpoint - Marvell Technology's stock performance has lagged behind the broader semiconductor market during the AI boom, but this may change as the focus shifts towards inference and energy efficiency, areas where Marvell excels [1][2]. Group 1: AI Transition - The AI industry is expected to transition from "brute-force training" to Agentic AI and inference by 2026, which requires lower latency and significantly higher energy efficiency compared to training [1]. - Marvell's custom XPU (AI accelerator) is designed for these specific workloads, optimizing for "tokens per watt," making it crucial for cloud giants aiming to scale services to billions of users [2]. Group 2: Interconnect Innovations - A critical infrastructure change by 2026 is the limitation of copper interconnects, which face challenges in heat, power consumption, and signal degradation as AI data centers expand [2]. - Marvell is investing heavily in Co-Packaged Optics (CPO) and has acquired Celestial AI for $3.25 billion to integrate optical interconnects directly into chip packaging, addressing data transfer bottlenecks without excessive power and heat [2][3]. Group 3: Customer Diversification - Marvell has historically been criticized for its reliance on Amazon Web Services (AWS), which increased earnings volatility and limited market recognition of its AI potential [3]. - The company is diversifying its customer base, having secured custom chip design orders from three of the four major U.S. cloud providers, with new projects expected to accelerate in 2026 [3][4]. Group 4: Financial Outlook - Marvell's trading valuation is significantly lower than peers, with an expected revenue growth of 42% in 2026 and 22% in 2027, despite a current operating margin of about 15% [4]. - The rationale for a re-rating lies in improving this margin structure, as increasing data center revenue and customer diversification could transform Marvell from a cyclical component supplier to a structural AI infrastructure platform [4].

公众号记得加星标⭐️，第一时间看推送不会错过。 研调机构Counterpoint发布报告指出，台积电预计在2028年前将晶圆14厂12英寸成熟制程产能削减 15%至20%。主要目的是解决传统工艺节点产能利用率低下的问题，同时释放资源以支持先进封装技 术的拓展。 根据目前的形势，台积电预计到 2028 年将逐步淘汰 Fab14 工厂约 50KWPM 的产能，通过多元化的 制造渠道提高运营灵活性和盈利能力，同时维持客户供应。 台积电表示，经与客户讨论，让资源运用更具弹性，也就是优化资源以支持客户。台积电会一如既往 地支持客户，即使是在8英寸晶圆业务方面，只要客户有好的业务发展，台积电都会持续提供支援。 参考链接 htt ps://mone y.udn. c om/mone y/st or y/ 5612/ 92847 84 htt ps:// c ount e r poi ntr e s e a r c h. c om/ e n/i nsi ghts/TSMC-t o-Cut-Fa b1 4-Ma t ur e -Node -Ca pa c it y-t o-Re fl e c t-Cha ngi ng- Dem ...

Core Insights - The article discusses significant developments in the AI chip sector, highlighting Tesla's revival of the Dojo 3 supercomputer project and Cerebras Systems' multi-billion dollar agreement with OpenAI for AI computing power [1][10]. Group 1: AI Chip Developments - Tesla's Dojo 3 project aims to position the company as a leading AI chip manufacturer, with a focus on "space artificial intelligence computing" rather than traditional training models [6][8]. - Cerebras Systems has secured a contract with OpenAI worth over $10 billion, promising to deliver 750 megawatts of computing power by 2028, emphasizing the growing demand for low-latency inference capabilities [10][11]. Group 2: Chip Architecture and Performance - The distinction between two types of large chips is made: Cerebras' wafer-scale integration and Tesla's wafer-scale system, each addressing the "memory wall" and "interconnect bottleneck" challenges differently [2][4]. - Cerebras' WSE-3 chip boasts 40 trillion transistors and 900,000 AI cores, achieving a memory bandwidth of 21 PB/s, significantly outperforming NVIDIA's H100 [3][11]. Group 3: Strategic Shifts - Tesla's shift in strategy reflects a recalibration of resources, moving away from competing directly with NVIDIA's GPU clusters to focusing on specialized applications in space computing [7][8]. - Cerebras' approach to positioning itself as a provider of dedicated inference machines allows it to capitalize on the emerging demand for low-latency processing, differentiating itself from traditional training platforms [15][19]. Group 4: Market Dynamics and Competition - The AI chip market is becoming increasingly crowded, with competitors like AMD and NVIDIA rapidly advancing their offerings, which poses challenges for alternative architectures like those from Cerebras and Tesla [15][19]. - The collaboration between OpenAI and Cerebras is seen as a strategic move to secure a foothold in the burgeoning inference market, which is expected to dominate AI computing needs in the future [10][19]. Group 5: Future Outlook - The advancements in packaging technology, such as TSMC's CoWoS, are expected to blur the lines between large and small chip architectures, potentially reshaping the competitive landscape [16][19]. - The article concludes that both Tesla and Cerebras are not merely trying to replicate NVIDIA's success but are instead seeking to find value in niches overlooked by general solutions, indicating a long-term battle for survival and innovation in the AI chip market [20].

Core Viewpoint - The demand for AI is driving a potential price increase in global wafer foundries, affecting even non-mainstream 8-inch wafers [1][2]. Supply Side Summary - TSMC and Samsung are gradually reducing 8-inch wafer production, with TSMC aiming for partial plant shutdowns by 2027. This reduction is expected to lead to a 0.3% decline in global 8-inch wafer capacity in 2025, entering negative growth. In 2026, despite some Chinese manufacturers planning slight capacity expansions, the overall capacity is projected to decrease by 2.4% due to the larger reductions from TSMC and Samsung [1][2]. Demand Side Summary - The increase in power IC orders for AI servers and the trend of IC localization in China are boosting demand for local wafer foundries, leading to a significant rise in capacity utilization rates for some Chinese manufacturers starting mid-2025. This has prompted these manufacturers to initiate price increases for foundry services, effective in the second half of 2025. The overall average capacity utilization for global 8-inch wafers is expected to rise to 85-90% in 2026, up from 75-80% in 2025, with some foundries planning to raise prices by 5-20% across all customers and process platforms [2][3]. Price Increase Considerations - Despite the anticipated price increases, actual price hikes for 8-inch wafers may be moderated due to concerns in consumer electronics and rising costs from memory and advanced processes impacting surrounding IC costs [3].

公众号记得加星标⭐️，第一时间看推送不会错过。 预计 NAND 价格在第二季度将继续上涨。据悉，三星电子目前正为了调高第二季度的供应价格与客 户进行协商。 三星电子已将第一季度 NAND 闪存价格提高了两倍以上。由于人工智能（AI）的普及，基于 NAND 的存储设备需求暴增，但供应端并未显著增加。预计内存短缺现象和价格上涨趋势在短期内仍将持 续。 25 日据业界消息，三星电子今年第一季度的 NAND 闪存供应价格涨幅已超过 100%。据了解，三星 已于去年年底与主要客户完成了供应合同的签署，并从 1 月起开始执行调价后的价格。继 DRAM 合 同价格上涨近 70% 之后，NAND 闪存的涨势也大幅增强。 三星电子第九代NAND闪存 NAND 价格的上涨并非近两日才开始。自去年年底内存供应短缺正式凸显以来，NAND 领域也受到 了 波 及 。 根 据 市 场 调 研 机 构 TrendForce 的 数 据 ， 去 年 第 四 季 度 NAND 价 格 环 比 上 涨 了 约 33~38%。虽然该机构此前预测今年第一季度的涨幅会维持在类似水平，但实际供应价格已远超预 期。 NAND 价格翻倍的情况不仅限于三星电 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 在英特尔第四季度财报会议上，首席执行官陈立武（Lip-Bu Tan）和首席财务官大卫·辛斯纳（David Zinsner）发表了多项言论，表明其代工业务（Foundry）正以稳健的势头推进。 英特尔预计芯片及先进封装订单将带来"数十亿美元收入" 虽然在消费级和数据中心/人工智能（DCAI）领域，英特尔在平衡这两项业务方面进展缓慢，但在英 特尔代工业务的演进方面，首席执行官陈立武详细介绍了制程节点的进展和客户送样情况。在谈到 18A 及其衍生版本时，陈立武透露，随着代工厂在良率方面取得积极进展，公司目前正致力于向潜在 客户提供 18A-P 工艺的 PDK 1.0（工艺设计套件）。 "我们现在正在出货首批基于 Intel 18A 构建的产品，这是在美国本土开发和制造的最先进半导体工 艺。如前所述，随着我们努力扩大产能以满足强劲的客户需求，良率正在稳步提升。此外，Intel 18AP 进 展 顺 利 ， 我 们 正 与 内 部 及 外 部 客 户 就 此 进 行 沟 通 ， 并 已 在 去 年 年 底 交 付 了 1.0 版 本 PDK。"—— 英特尔首席执行官 陈立 ...