Core Viewpoint - Intel has made significant advancements in chip packaging technology under the leadership of new CEO Chen Liwu, particularly with the introduction of the EMIB-T technology, which enhances chip packaging size and power delivery capabilities to support new technologies like HBM4/4e [1][9]. Group 1: EMIB-T Technology Advancements - EMIB-T integrates TSV (Through-Silicon Via) for vertical signal transmission between chips, reducing power transmission resistance by over 30%, which minimizes voltage drop and signal noise [2][6]. - The technology incorporates high-density MIM (Metal-Insulator-Metal) capacitors to suppress power noise, ensuring signal integrity, especially in high-performance applications like AI accelerators and data center processors [2][7]. - EMIB-T supports a maximum package size of 120x180 mm, allowing integration of over 38 bridges and 12 dies, with plans to reduce bump pitch from 45 microns to as low as 25 microns in the future [2][7]. Group 2: Strategic Importance and Market Position - Intel's foundry aims to leverage cutting-edge process node technologies to manufacture chips for both internal and external clients, enhancing performance, cost, and energy efficiency through complex heterogeneous designs [4][5]. - The EMIB-T technology is crucial for supporting HBM4 memory and UCIe interconnect requirements, making it an ideal packaging solution for AI accelerators, data center processors, and supercomputing chips [7][8]. - Intel plans to achieve mass production of EMIB-T packaging by the second half of 2025, with a vision to integrate over 24 HBM chips in a single package by 2028, significantly impacting global semiconductor packaging technology [9].

Core Insights - The rigid copper-clad laminate (CCL) industry in China experienced rapid growth from 2019 to 2021 due to accelerated 5G base station construction, surging demand for electronic components in electric vehicles, and increased consumer electronics demand driven by the pandemic. However, starting in 2022, the industry entered an adjustment phase due to global economic recession, weak consumer electronics demand, and semiconductor supply chain disruptions. In 2023, the industry continued to contract, with sales volume slightly decreasing to 524.9 million square meters and sales revenue shrinking to 9.334 billion yuan, representing a year-on-year decline of 16.3% [2]. Industry Overview - Rigid copper-clad laminates, also known as copper foil laminated boards, play a crucial role in electronic circuit manufacturing, providing conductivity, insulation, and support. They significantly impact signal transmission speed, energy loss, and characteristic impedance. Rigid copper-clad laminates are characterized by their hardness and toughness, making them suitable for applications in communication devices, household appliances, electronic toys, and computer peripherals [3]. Policy Background - China's policy support for the rigid copper-clad laminate industry is characterized by multi-level and multi-dimensional collaborative promotion, focusing on technological upgrades, intelligent equipment transformation, and green transition. Key policy areas include supporting the R&D breakthroughs of high-frequency and high-speed copper-clad laminates and high-performance substrates, optimizing production processes, and establishing standardized testing systems to enhance product reliability. Additionally, policies encourage enterprises to strengthen pilot testing capabilities through advanced equipment updates and promote sustainable development through the adoption of environmentally friendly materials and clean production processes [5][6]. Industry Chain - The rigid copper-clad laminate industry chain in China consists of upstream suppliers of key raw materials such as electronic-grade glass fiber cloth, copper foil, resin, and wood pulp paper, which provide the foundational materials for laminate manufacturing. The midstream focuses on the production and manufacturing of rigid copper-clad laminates through processes like lamination and coating. The downstream applications cover communication devices, household appliances, electronic toys, and computer peripherals, directly serving the demands of consumer electronics, communication technology, and home appliance industries [7]. Current Industry Status - In 2023, the global rigid copper-clad laminate market faced a decline due to macroeconomic fluctuations, with total sales revenue dropping by 16.3% to 12.734 billion USD and sales volume slightly decreasing by 1.1% to 656.8 million square meters. Among the product categories, conventional FR-4 maintained the largest sales revenue share at 33.38%, while special resin-based and dedicated CCL (including high-speed, high-frequency, and IC carrier boards) increased their share to 32.88%, driven by resilient high-end demand from AI servers, 5G communication, and advanced packaging technologies. The demand for halogen-free FR-4 and high Tg FR-4 has contracted due to weakened consumer electronics and automotive electronics demand, while composite and paper-based CCL accounted for less than 10% of the market, leading to a rapid exit of traditional low-end products. Notably, high-speed CCL (including halogen-free types) showed outstanding performance among the three special laminates, with sales revenue increasing by 5.5% despite market challenges, driven by rising technical barriers [9].

Group 1 - Glass substrates are characterized by high transparency, excellent flatness, and good stability, serving as a support carrier to ensure the reliable fixation of functional materials and the overall stability and lifespan of devices [1][2] - The global advanced packaging market is projected to grow from $28.8 billion in 2019 to $42.5 billion by 2024, indicating a rising penetration rate [1][13] - The introduction of glass substrates can reduce capacitance between interconnections, leading to faster signal transmission and improved overall performance, particularly in data centers, telecommunications, and high-performance computing applications [1][15] Group 2 - The glass substrate industry chain includes key segments such as raw materials, equipment, technology, production, packaging testing, and applications, with special glass materials being crucial for semiconductor manufacturing [6] - The TGV (Through Glass Via) technology is a core technique for glass substrate packaging, enabling vertical electrical interconnections and addressing challenges associated with traditional TSV technology [19][20] - The glass substrate market is expected to reach over $400 million by 2030, with a penetration rate exceeding 2%, although organic substrates will continue to dominate the semiconductor packaging field in the near term [15][17] Group 3 - The glass substrate technology is anticipated to play a significant role in the semiconductor industry, with ongoing advancements focusing on process optimization, improving via precision and density, and expanding the functional applications of glass substrates [25] - The global semiconductor market is projected to reach $635.1 billion in 2024, reflecting a 19.8% year-on-year growth, driven by the increasing demand for high-performance semiconductor products [9]

Investment Rating - The report does not explicitly provide an investment rating for the advanced packaging equipment industry. Core Insights - The advanced packaging technology aims to enhance chip performance, increase functional integration, reduce product size, and improve thermal management capabilities, driven by the demand for high-performance electronic products. The key to achieving these advanced packaging technologies lies in advanced packaging equipment [2]. Summary by Sections Semiconductor Packaging Equipment Industry Overview - Traditional packaging focuses on low cost and simple structures, while advanced packaging utilizes high-density interconnects, heterogeneous integration, and 3D stacking technologies to meet the demands of high-performance computing, 5G, and AI [16]. - The global semiconductor manufacturing equipment sales are projected to grow from $106.3 billion in 2023 to $117.1 billion in 2024, with advanced packaging driving an increase in the share of packaging equipment sales [21][22]. Required Semiconductor Equipment for Packaging Processes - Advanced packaging introduces new applications such as wafer thinning, RDL (Redistribution Layer) production, bump production, and TSV (Through-Silicon Via) production, necessitating both existing backend packaging equipment and new front-end equipment [9][27]. - The traditional backend packaging equipment must undergo technological upgrades to accommodate smaller sizes, higher integration, and more complex structures, focusing on precision, material compatibility, process control, and automation [32]. Advanced Packaging Equipment Analysis - The report highlights the need for various semiconductor equipment types, including thinning machines, dicing machines, and bonding machines, to support advanced packaging processes [35][45]. - The global thinning machine market is dominated by Japanese companies, with a concentration ratio of approximately 85%, while domestic companies like Huahai Qingke and Jing Sheng Machinery are emerging players [40][44]. Traditional Backend Equipment Upgrades and Manufacturers - Traditional backend packaging equipment requires upgrades to meet the demands of advanced packaging, focusing on precision enhancement, material compatibility, process control, and automation [32]. - Key domestic suppliers for thinning machines include Huahai Qingke, Jing Sheng Machinery, and China Electronics Technology Group [32].

Core Viewpoint - The article discusses the advancements and importance of 3D integrated circuits (3D IC) and the role of EDA tools like 3Sheng Stratify™ in ensuring the accuracy and integrity of stacked chip designs, which are crucial for high-performance applications in various industries [3][30]. Group 1: 3D IC and Advanced Packaging - 3D IC technology provides significant flexibility and reusability in product design, particularly for AI computing and high-end mixed-signal integration [3]. - Stacked chips utilize advanced packaging techniques that are essential for performance, functionality, cost, and iteration methods [3]. - The demand for high-density interconnect advanced packaging is growing across various applications, including military, aerospace, and consumer electronics [4]. Group 2: EDA Tools and Verification - 3Sheng Stratify™ EDA tool offers rapid and accurate assembly-level verification for interconnections between dies and intermediary layers in stacked chip designs [10]. - The tool supports design rule checks (DRC) and layout versus schematic (LVS) checks to ensure consistency and compliance with design specifications [10][12]. - The verification process includes checks for signal integrity and functionality across complex interconnect structures [9]. Group 3: Key Performance Indicators - The EDA tool provides various functionalities, including high-density interconnect verification, static timing analysis, and design rule compliance checks [12][13]. - It also features automated detection of anomalies and supports multi-file collaborative checks to enhance design efficiency [13][14]. - The tool aims to improve manufacturability and reliability of 2.5D designs by ensuring that physical layouts meet manufacturing process specifications [23]. Group 4: Design Rule Checks and Automation - The 3Sheng DRC tool supports a wide range of design rule checks, including geometric rules and special process checks, to ensure compliance with foundry specifications [25][28]. - The tool incorporates machine learning algorithms for anomaly detection in 2.5D designs, enhancing the accuracy of network connection checks [18][20]. - Automated repair features are included to address design rule violations, thereby reducing manual intervention and speeding up the design iteration process [28][29]. Group 5: Future Directions - The company aims to enhance the automation design capabilities for 2.5D/3D/3.5D systems, providing comprehensive design and verification solutions to the industry [31]. - The integration of various design engines within the 3Sheng Integration Platform facilitates rapid design and verification processes, ensuring a balance between performance, power consumption, area, and cost [30].

Core Viewpoint - Asahi Kasei's supply adjustments of PSPI materials have significant implications for the global semiconductor industry, highlighting the tension between surging AI computing demands and limited production capacity [1][2]. Group 1: PSPI Material Overview - PSPI (Photosensitive Polyimide) is a high-performance polymer material that combines excellent dielectric properties, mechanical strength, and heat resistance with photosensitivity, playing a crucial role in semiconductor packaging and advanced packaging processes [3][5]. - The global market for PSPI materials is projected to reach USD 402 million in 2024 and USD 802 million by 2030, with major suppliers dominating approximately 95% of the market share [5][9]. Group 2: Domestic Market and Companies - The domestic PSPI market in China is expected to reach RMB 820 million in 2024, driven by the increasing demand for AI computing chips and advanced packaging technologies [9]. - Key domestic players in the PSPI market include Bomi Technology, Dinglong Holdings, Aisen Semiconductor, and Shengquan Group, with various companies actively developing and producing PSPI materials [10][11][12][13]. Group 3: Company Highlights - Bomi Technology has achieved mass production of PSPI materials and is involved in a national key research project for 2.5D/3D packaging technology [10]. - Dinglong Holdings has developed multiple semiconductor packaging materials and is set to begin mass production in 2024 [11]. - Aisen Semiconductor is launching its first domestic positive PSPI product in 2024 and is also working on various other PSPI types [12]. - Shengquan Group has established a pilot line for PSPI and plans to expand production significantly by 2025 [12].

Core Viewpoint - SpaceX, led by Elon Musk, is betting on Fan-Out Panel Level Packaging (FOPLP) to meet the production demands of its low Earth orbit satellites, requiring suppliers to expand their FOPLP production lines [1][2]. Group 1: SpaceX and FOPLP Development - SpaceX has signed a Non-Recurring Engineering (NRE) contract with Innolux, which is expected to secure significant orders for power management chips and aims for FOPLP mass production this year [1]. - SpaceX is also establishing its own FOPLP production line in Malaysia, with a substrate size of 700mm x 700mm, the largest in the industry, to enhance vertical integration capabilities in satellite systems [1][2]. Group 2: Innolux's Position and Strategy - Innolux, a supplier for Tesla, is extending its collaboration with SpaceX into semiconductors, aiming to develop analog chips for mass production this year [2]. - The company is utilizing its existing 3.5-generation glass substrate for FOPLP, which, while not competitive for panel production, offers significant advantages in mass production efficiency due to its large size [2]. Group 3: Technical Development and Clarifications - Innolux is developing three main process technologies for FOPLP: chip first, RDL first, and TGV, with chip first and RDL first progressing as planned, while TGV is still in the development phase [4]. - The company emphasizes that the display technology and advanced packaging processes share about 60% of their procedures, indicating a strong potential for entering the packaging field [4][5]. Group 4: Market Perception and Misunderstandings - Innolux has clarified misunderstandings arising from reports suggesting that the display industry's precision standards are insufficient for advanced chip packaging, asserting that such claims could mislead the market and affect its reputation [3][4]. - The company has the capability to produce the largest substrate size currently applicable in advanced packaging, and it can adjust processes for smaller substrate sizes without technical challenges [4][5].

【DT新材料】 获悉，近日，日本 旭化成 向部分客户发出供应调整通知， 拟收 紧其PIMEL系列感光材料供应，此次供应限制主要系AI算力需求快速 增长，导致该公司产能无法及时匹配市场需求所致。 市场更有最新消息称公司 将断供其 液态感光性聚酰亚胺（PSPI）材料（商品名PIMEL）。 鼎龙股份 ，具有 200吨/年显示面板用PSPI，另外 仙桃产业园1000吨PSPI产线投产，PFAS Free PSPI、BPDL产品已完成性能优化、实验线验证阶段，并 送样国内主流面板厂客户G6代线验证。 万润股份 ， OLED用光敏聚酰亚胺（PSPI）已经在下游面板厂实现供应。去年10月， 公司宣布将与京东方材料、德邦科技、业达经发共同出资设立烟台 京东方材料科技有限公司。 八亿时空 表示其 聚酰亚胺（PSPI） 在客户端验证顺利。近日，公司子公司浙江时光新能源有限公司项目环评文件的公示，涉及年产50吨高端光刻胶树脂 (PHS)，200吨光敏聚酰亚胺(PSPI)的生产能力。 PSPI是一种具有光敏性和耐热性双重功能的聚酰亚胺溶液，属于高端聚酰亚胺，是一种在高分子链上兼有亚胺环以及光敏基因的有机材料，在暴露于 光或紫外线时会 ...

Core Insights - Dongguan has launched its first strategic scientist team, achieving significant technological advancements in semiconductor and AI chip development, including the international first TGV 3.0 technology and the world's first low-power AI chip [1][2][4]. Group 1: Technological Innovations - The TGV 3.0 technology has overcome production bottlenecks, achieving sub-10 micron through-hole and a 10:1 aspect ratio, with a through-hole yield of 99.9%, enhancing 3D packaging solutions [4]. - The world's first "energy-aware computing" low-power AI chip operates at only 70mW with a processing power of 512 GOPS, suitable for AIoT and edge computing applications [4]. - The first PLP plasma etching equipment in the country supports large glass substrates and achieves international advanced levels in etching rate and uniformity [4]. - The first fully automated AI-AOI detection equipment offers precision detection at 0.001 microns with an accuracy exceeding 99%, filling a gap in high-end semiconductor testing equipment in China [4]. Group 2: Strategic Development - Dongguan's strategic scientist team, led by Professor Yang Xiaobo, focuses on advanced packaging and low-power AI chips, addressing critical technological challenges in the semiconductor industry [3][4]. - The city aims to transition from "Dongguan manufacturing" to "Dongguan intelligent manufacturing," leveraging its manufacturing base to enhance its technological capabilities [5]. - Dongguan has established a complete industrial chain in semiconductor and integrated circuit sectors, with 257 semiconductor companies and projected industry revenue exceeding 75 billion yuan in 2024 [6]. Group 3: Talent and Policy Support - The local government is optimizing talent policies to attract high-level scientific talent, supporting innovation and entrepreneurship through strategic scientist teams and research initiatives [8][12]. - The Dongguan Integrated Circuit Innovation Center aims to enhance technological innovation capabilities and strengthen the industrial ecosystem, focusing on the transformation of scientific achievements into industrial applications [8][12]. - The collaboration between research teams, the innovation center, and local government is noted for its efficiency and responsiveness, fostering a supportive environment for startups [11].

Core Insights - Global semiconductor capital expenditure (CapEx) is projected to decrease by 7% quarter-on-quarter in Q1 2025 but increase by 27% year-on-year, driven by investments in advanced logic, high-bandwidth memory (HBM), and advanced packaging technologies supporting AI applications [1] - Memory-related capital expenditure has surged by 57% year-on-year, while non-memory spending has grown by 15% during the same period [1] - Wafer fab equipment (WFE) spending is expected to rise by 19% year-on-year in Q1 2025, with a further 12% increase anticipated in Q2, fueled by significant investments in advanced logic and memory production to meet growing AI demands [1] - Test equipment spending has increased by 56% year-on-year in Q1, with a forecasted growth of 53% in Q2, driven by demand for AI and HBM chips [1] - Global wafer fab capacity is expected to exceed 42.5 million 300mm equivalent wafers per quarter in Q1 2025, reflecting a 2% quarter-on-quarter and 7% year-on-year growth [1] China Wafer Capacity Growth - China remains the leading region for wafer capacity expansion, although growth momentum is expected to slow in the coming quarters [2] - Japan and Taiwan are experiencing the fastest quarterly capacity growth, driven by significant investments in power semiconductors and the expansion of advanced foundries [2] Major Chip Manufacturers Increasing CapEx - TSMC has reaffirmed its annual capital expenditure target for 2025 at $38 billion to $42 billion, which aligns with market expectations and represents a historical high, with a midpoint of $40 billion [3] - TSMC's Q1 2025 capital expenditure was $10.06 billion, slightly lower than the previous quarter's $11.23 billion [3] - Approximately 70% of TSMC's 2025 capital expenditure will be allocated to advanced process technologies, with 10% to 20% for special technologies, and another 10% to 20% for advanced packaging, testing, and photomask production [3] - SMIC plans to invest $7 billion in capital expenditure in 2025, reflecting domestic demand growth and efforts to advance chip manufacturing technology following U.S. sanctions against TSMC supplying chips to Huawei [3]