公众号记得加星标⭐️，第一时间看推送不会错过。 昨日，有媒体引述第三方购物平台获悉，海力士和三星的256G DDR5服务器内存一根超过4万 元，有的甚至高达49999元/根。如果按照1盒100根来计算，其价格将近500万元，这已经超过 上海不少房产。这也正是昨天热文"一盒内存条价格堪比上海一套房"的核心观点。 昨天，半导体行业观察也报道了闪迪从去年四月到现在，股价已经上升十倍。具体参考文章 《闪迪股价，飙升 1080% 》 。 从三星今天发布的数据看来，存储巨头也的确已经数钱数到手软。 该盈利远超市场普遍预期（约 18 万亿韩元），分析师表示，全球人工智能 (AI) 基础设施投资的扩 大推动了存储半导体周期的反弹，这一结果证实了这一点。 根据三星电子1月8日发布的数据，2025年第四季度销售额环比增长8.06%，同比增长22.71%。营业 利润环比增长64.34%，同比增长208.17%。按季度计算，这是自2018年以来的最高水平。 报道进一步指出，存储半导体业务是此次盈利改善的核心。尽管各业务部门的官方业绩尚未公布，但 业内人士和证券界普遍预期，半导体（DS）部门第四季度的销售额约为40万亿韩元，营业利润为 ...

Core Insights - The semiconductor industry is experiencing a significant push towards localization, with numerous companies planning to build factories by 2025 to meet the rising demand for advanced technologies such as AI chips and advanced memory [1] - Investment sources include both industry and government, focusing on addressing current technological challenges and expanding capabilities in various sectors [1] Regional Developments Asia - TSMC is constructing six new fabs and advanced packaging plants in Taiwan, while ASE is investing $578.6 million in Kaohsiung for an advanced packaging facility [2] - SK Hynix's total investment in the Yongin industrial cluster may reach 600 trillion KRW (approximately $407 billion) [2] - Micron is building an advanced memory manufacturing plant in Japan with government support, and Rapidus has completed a prototype of a 2nm GAA process [2] - India has approved four new fabs, including SicSem's facility in Odisha [2] Europe - The EU launched five pilot production lines under the Chips Act, targeting 2nm, advanced packaging, and photonics [3] - The Czech semiconductor center received €450 million in funding for ON Semiconductor's SiC power device factory [3] - Germany is providing significant financial support for Infineon's and GlobalFoundries' factory expansions in Dresden [3] - imec has opened an automotive chip center in Heilbronn, Germany, and launched an advanced chip design accelerator project [3] Americas - TSMC has increased its investment in the U.S. to $100 billion, while Apple is investing $500 billion and GlobalFoundries $16 billion [4] - Micron plans to invest an additional $30 billion in U.S. fabs, including new facilities in Idaho and Virginia [4] - Texas Instruments has opened a new advanced 300mm fab in Sherman, Texas, as part of a $60 billion investment plan [4] Challenges and Uncertainties - Several companies, including NXP and Intel, are facing challenges with factory closures and project cancellations due to market volatility [5] - The uncertainty surrounding the U.S. Chips Act and its implications for funding and investment strategies is causing concern among industry leaders [6][7] Material and Energy Concerns - The semiconductor industry is facing strategic challenges related to the supply of rare earth materials, emphasizing the need for diversification and domestic resource development [10] - The energy consumption of AI server clusters is rising, with projections indicating that it could account for 7% of global electricity demand by 2025 [11] Future Outlook - The semiconductor industry is poised for growth driven by advancements in AI, quantum technology, and robotics, with significant potential in healthcare and elder care applications [15] - The industry is expected to see substantial investments in new facilities and fabs, reflecting ongoing adjustments to previously announced plans [16]

Core Viewpoint - Through-Silicon Vias (TSVs) are essential for modern 3D Integrated Circuit (3D-IC) technology, providing vertical interconnections that enable short and low-latency signal paths between stacked chips [1] Group 1: TSV Structure and Manufacturing - TSVs are vertical metal plugs, typically made of copper, embedded in the thickness of silicon chips. The classic manufacturing process includes deep reactive ion etching (DRIE), deposition of liner and barrier layers, copper electrochemical deposition, and back thinning to expose the vias [3] - TSVs can be categorized into three types based on their introduction in the manufacturing process: front-side, middle, and back-side vias, with middle vias being most common in high-density logic memory stacking [3] Group 2: TSV Spacing and Electrical Characteristics - TSV spacing is a critical parameter affecting system design choices. Smaller spacing allows for more vertical interconnections per unit area, supporting higher bandwidth between stacked chips, but also presents challenges [5] - Parasitic parameters of TSVs, including resistance, capacitance, and inductance, must be accurately modeled early in the process. These parameters impact signal integrity, timing convergence, power transmission, and inter-layer communication [7] - The capacitance of TSVs acts like a metal-insulator-semiconductor capacitor, where higher capacitance increases delay and reduces noise tolerance, introducing crosstalk to nearby networks [7] - Resistance from copper filling is significant for high-frequency signals, directly affecting insertion loss and power efficiency for wideband memory and high-speed SerDes paths [7] - The vertical geometry of TSVs can introduce inductive behavior that affects impedance matching and eye diagram margins for fast edges and GHz-range components [7] Group 3: Design Constraints and Reliability - The choice of TSV spacing must optimize electrical performance, mechanical reliability, and physical design constraints due to increased mechanical stress and larger KOZ (Keep Out Zone) areas [8] - Each TSV requires a KOZ, preventing the placement of active devices or sensitive interconnections within that area to avoid performance degradation due to stress and leakage current [12] - The thermal expansion coefficient (CTE) of copper is higher than that of silicon, leading to local stress during temperature cycling, which can alter transistor characteristics and affect long-term reliability [12] - To mitigate stress impacts, TSVs can be compared with micro-bumps, with TSVs offering shorter vertical path lengths, typically in the range of tens of micrometers, compared to hundreds of micrometers for micro-bumps [12] Group 4: Applications and Performance - TSVs significantly enhance vertical bandwidth density, supporting more parallel connections in a smaller space, crucial for high bandwidth memory (HBM) stacks achieving terabits per second [15] - TSVs provide lower interconnect latency due to shorter path lengths and reduced RC delay compared to micro-bump interconnections, which introduce longer paths and additional parasitic layers [15] - TSVs can also serve as thermal conduits, aiding in vertical heat dissipation, a feature not available with micro-bumps, although TSVs introduce thermal stress that requires balanced layout strategies [15] - Engineering teams must establish a TSV budget early in the 3D IC design phase, influencing chip size, partitioning strategies, bandwidth targets, and overall packaging economics [15] Group 5: Verification and Reliability Considerations - Electrical, physical, and reliability verification are essential for TSVs, addressing long-term reliability concerns such as hybrid bonding and TSV integration [20] - Specific scenarios for hybrid bonding include precise extraction of TSV array parasitics, timing analysis of inter-layer paths, and SI/PI analysis of vertical power networks [21]

Core Viewpoint - Ultra-Wideband (UWB) technology has been increasingly applied in various commercial fields requiring secure and precise distance measurement capabilities since the early 2000s, with applications in contactless access systems, asset tracking, and navigation support in large venues [1][4]. Group 1: UWB Technology Characteristics - UWB technology utilizes extremely short pulses in wireless signal transmission, allowing for a bandwidth significantly greater than narrowband technologies like Wi-Fi and Bluetooth [1]. - The operational frequency range of UWB typically spans from 6 to 10 GHz, with channel bandwidths around 500 MHz or higher, enabling centimeter to millimeter-level positioning accuracy [1]. - Enhanced physical layer features of UWB, as part of the IEEE 802.15.4z standard, play a crucial role in achieving secure distance measurement capabilities [1]. Group 2: Advancements by imec - imec has made significant contributions to UWB technology by reducing power consumption, increasing bit rates, and enhancing distance measurement accuracy while ensuring resistance to interference from other wireless technologies [3]. - The development of multiple generations of UWB radio chips compliant with the IEEE 802.15.4z standard has been achieved, featuring innovative pulse shaping and modulation techniques [3]. Group 3: Applications and Future Potential - Experts believe UWB's potential extends beyond precise distance measurement to radar-like applications, detecting passive objects through the analysis of reflected signals [4]. - UWB technology can enhance safety in automotive applications by detecting the presence of occupants and monitoring gestures and vital signs [4]. - The upcoming IEEE 802.15.4ab standard, expected to be released in early 2026, will facilitate the realization of such UWB applications by introducing radar capabilities [4]. Group 4: Performance Metrics - imec's fourth-generation UWB transceiver, showcased at VLSI 2025, supports enhanced modulation and high data rates, achieving up to 124.8 Mb/s, integrated within a system-on-chip (SoC) [5]. - The UWB radar sensing technology demonstrates unique capabilities, such as extended detection ranges and high data rates, which are approximately 20 times higher than current applications [14]. Group 5: MIMO Architecture - imec's infrared UWB radar sensing system features a 2x2 MIMO architecture, allowing simultaneous operation in both transmission and reception modes without the need for RF switches [7]. - This configuration significantly reduces the effective working distance limitations previously imposed by mode-switching times, enabling operation within a range of 30 cm to 3 m [8]. Group 6: Market Opportunities - The high data rate and low power consumption of UWB technology open new application areas, including audio and video data streaming for next-generation smart glasses or VR/AR devices [14][16]. - The advanced ranging capabilities introduced by the fifth-generation UWB technology can enhance user experiences in automotive and smart building applications, potentially increasing effective working distances and improving performance in complex environments [15][16].

Core Viewpoint - The global semiconductor industry is undergoing a transformative change with the rise of the open-source instruction set architecture (ISA) RISC-V, which has captured 25% of the global processor market as of January 2026, marking the end of the long-standing x86 and Arm duopoly and ushering in an era of shared resources in chip design [1] Group 1: Technological Evolution - RISC-V's rise is attributed to its modular architecture, allowing designers to customize chips for specific workloads without the legacy bloat of x86 or the strict licensing constraints of Arm [2] - The introduction of the RISC-V vector extension RVV 1.0 is crucial for high-throughput mathematical operations required in modern AI applications, enabling companies like Tenstorrent to develop competitive cores [2][3] - The deployment of out-of-order execution RISC-V cores has achieved single-thread performance comparable to high-end laptop processors, with the ESWIN EIC7702X SoC demonstrating neural processing capabilities of up to 50 TOPS [3] Group 2: Strategic Shifts - Qualcomm's acquisition of Ventana Micro Systems for $2.4 billion signifies a strategic move to independence from Arm, allowing Qualcomm to develop its own high-performance RISC-V cores without royalty payments [4] - Meta Platforms is restructuring its chip strategy towards open ISA, optimizing its Meta Training and Inference Accelerator (MTIA) based on RISC-V, achieving a 30% improvement in performance per watt compared to previous proprietary designs [4] Group 3: Competitive Landscape - RISC-V offers a cost-effective path for large AI labs and cloud service providers to vertically integrate, enabling startups to license high-quality open-source cores and create custom chips at significantly lower costs than traditional licensing [5] - The proliferation of high-performance chips based on RISC-V is disrupting the market positions of Intel and Nvidia, compelling these giants to integrate their own neural network processors (NPU) more aggressively [5] Group 4: Geopolitical Sovereignty - RISC-V has become a core tool for nations pursuing technological sovereignty, particularly in China, where it is seen as a strategic necessity amid strict U.S. export controls on advanced architectures [6] - The EU is similarly leveraging RISC-V through initiatives like the DARE project to reduce dependence on U.S. and U.K. technologies, with companies like Axelera AI delivering RISC-V-based AI units [6] Group 5: Future Outlook - The trend towards "AI PCs" is expected to drive RISC-V's growth, with second-generation RISC-V laptops anticipated to launch by mid-2026, promising superior battery life and dedicated NPU performance [8] - Challenges remain in traditional enterprise environments, as legacy software heavily relies on x86 optimization, but advancements in binary translation technology could facilitate RISC-V's adoption [8] - Successful integration of RISC-V systems could pave the way for achieving 40% to 50% market share by the end of the decade [8] Group 6: New Computing Era - RISC-V's market share reaching 25% signifies a pivotal moment in technology history, transitioning from a "black box" chip era to a transparent, customizable, and globally accessible architecture [9] - The emergence of "pure RISC-V" data centers and flagship devices based on open ISA is anticipated, marking the reality of RISC-V as a third pillar in computing [9]

Core Viewpoint - The article emphasizes the transition in consumer AI from a focus on extreme computing power to a balanced approach that prioritizes cost-effectiveness, energy efficiency, and scenario adaptability, with customized ASIC chips becoming essential for inference tasks [1][3]. Group 1: Market Demand and Technological Advancements - The demand for consumer-grade AI has shifted towards integrated capabilities that offer better cost-performance ratios and energy consumption metrics [1]. - New基讯科技有限公司 leverages its self-developed 5G communication chips with edge AI capabilities to address interaction pain points, aiming to provide AI solutions that are cheaper, more reliable, and easily deployable [1][3]. - The company is positioned as a leader in the consumer AI market by integrating cloud and edge AI ecosystems, moving from cloud dependency to native terminal solutions [3]. Group 2: Application Scenarios - The focus is on high-frequency consumer scenarios such as home, office, and mobile travel, utilizing 5G chip connectivity to achieve seamless integration across various applications, including AIOT, wearable health monitoring, and smart home systems [5]. - The explosion of large model applications is expected to significantly increase the demand for inference chips, making AI a practical tool for widespread use [5]. Group 3: Technical Innovations - New基讯's 5G chips provide low-latency, wide-coverage connectivity, combined with local inference frameworks and cloud model access, utilizing model distillation and tiered storage technologies to enhance efficiency [7]. - Customized chips can significantly improve energy efficiency through hardware-level optimizations, addressing consumer demands for size, power consumption, and security [8]. Group 4: Ecosystem Development - The synergy between AI and 5G is highlighted as a means to accelerate the implementation of inference technologies, with a focus on creating a "China technology + global service" model for international markets [10]. - The first product featuring New基讯's AI solutions, an AI guardian terminal, is set to launch globally this year [10].

公众号记得加星标⭐️，第一时间看推送不会错过。 随着人工智能（AI）半导体需求强度远超市场预期，全球封测龙头日月光投控正迎接前所未有的成长 契机。大摩(摩根士丹利，Morgan Stanley）在最新的研究报告中，将日月光投控的投资评等重申为 「买进」，并将目标价从新台币228 元大幅上调至308 元。此一调整，反映了分析师对其2026 年至 2027 年获利成长的强劲信心，特别是看好其在先进封装领域的领先地位及定价权的提升。 报告指出，由于AI 半导体需求极为强劲，加上日月光的产能已趋近极限，预计该公司将在2026 年调 涨后段晶圆代工服务价格，涨幅预期落在5% 至20% 之间，高于原先预期的5-10%。这波涨价主要导 因于半导体通膨压力，日月光已决定将包含基板、贵金属及电费在内的增加成本转嫁给客户。同时， 公司将优先向毛利率较高的AI 客户供货，以优化产品组合。 报告表示，大中华区外包封测（OSAT）的产能利用率（UTR）在2025 年已持续复苏，预计2026 年 将进一步成长。日月光2025 年第三季的产能利用率已达90%，在实务上什至已接近满载，这使其在 2026 年的价格谈判中拥有极强的议价筹码。 ...

全球领先的低功耗无线连接解决方案提供商 Nordic Semiconductor 正在将人工智能智能和功能引入 最小的电池供电型物联网设备。凭借业界领先的超低功耗边缘人工智能解决方案，Nordic 加速了集 成边缘人工智能智能的新一代设备的到来，将能源效率与开发者无与伦比的易用性完美结合。 nRF54LM20B – 全新超低功耗、大内存无线SoC，搭载Axon NPU 定制 Neuton 模型——业界领先的超小型边缘 AI 模型 Nordic Edge AI Lab – 开发工具，简化并加速边缘人工智能开发 "人工智能工厂负责训练智能，而 Nordic 负责部署智能——在设备端、在边缘端，在世界运转的地 方，" Nordic Semiconductor 首席执行官 Vegard Wollan 表示。"边缘人工智能已不再是可选项，而 是大规模实现安全、隐私和可持续性的唯一途径。Nordic 的边缘人工智能解决方案能够实现毫秒级 决策，无需往返云端的延迟，通过本地处理确保合规性，并为数十亿台联网设备带来显著提升的电池 续航能力。这是超低功耗边缘人工智能的新标准，而 Nordic 正在定义它。" 公众号记得加星标⭐ ...

挑战在于，为相对较小的市场开发基于更小晶体管尺寸的更先进芯片成本巨大。诺基亚是Marvell的 另一大RAN客户，在5G初期，该公司与英特尔签订合同，由后者提供基于10纳米制程的网络芯片。 几年后，诺基亚最新5G产品中使用的Marvell芯片的晶体管尺寸似乎只有原来的一半。专家表示，尺 寸缩小会带来高昂的成本，尤其是在大规模MIMO等前沿领域，而大规模MIMO是一种先进的RAN技 术。 公众号记得加星标⭐️，第一时间看推送不会错过。 自 5G 时代到来以来，三星销售的网络产品大致分为两大类。对于不愿受云化及相关趋势影响的传统 用户，三星提供基于 Marvell Technology 定制芯片的专用无线接入网 (RAN)。另一种选择是三星的 虚拟 RAN 产品线，该产品线采用英特尔的通用处理器。 然而，这家韩国供应商对虚拟无线接入网（Virtual RAN）的优先发展引发了人们对其专用产品组合 长期前景的质疑。据知情人士透露，在Marvell内部，为三星未来的5G和6G网络需求开发芯片已开始 显得经济上不可行。Marvell在无线接入网产品市场上的整个地位都岌岌可危。 三星官方的说法是，与Marvell的合作一 ...

Core Insights - The rapid development of generative artificial intelligence has accelerated the deployment of large-scale AI clusters globally, leading to a significant energy crisis due to increased energy consumption associated with data processing and transmission [1][3] - Photonics technology, particularly silicon photonics, has the potential to address energy consumption issues by enabling high-density interconnects and low-energy optical switching, which are essential for sustainable AI infrastructure [3][4] Group 1: Energy Consumption and Photonics - The energy supply required for data processing is expected to grow exponentially alongside data volume, necessitating the development of technologies that decouple energy growth from data growth [1] - Silicon photonics has evolved over the past two decades to provide an ideal platform for efficient optical interconnects, enabling high bandwidth and long-distance links while maintaining low energy consumption [3][4] Group 2: Optical Switches and ASICs - The energy efficiency of optical transceivers has matched the pace of Moore's Law, achieving over 5 pJ/bit, while the scalability of ASIC switches has lagged behind, indicating a bottleneck in the switch rather than the transceiver [4][6] - Optical switches maintain low power consumption even as throughput increases, contrasting with ASIC switches, which exceed 1000W at 100Tbps throughput [6] Group 3: System Applications and Development - Optical switches cannot directly replace ASIC switches due to their inability to process data packets, necessitating a complete system redesign and optimization for optical circuit switches (OCS) [8] - Google has pioneered the large-scale implementation of OCS in its data centers, leading to increased interest and development in optical switching technology [8][9] Group 4: Photonic Neural Networks (PNN) - Photonic neural networks leverage the high uniformity and yield of silicon photonic devices to perform matrix-vector multiplications at high speed and low energy, potentially alleviating the computational burden on high-energy digital processors [13][15] - New AI models based on electro-optic nonlinearity have been proposed to enhance the capabilities of PNNs, allowing for efficient computation without intermediate digital processing [15][21] Group 5: Future Directions - Significant advancements in silicon photonics have demonstrated its potential to enhance the sustainability of AI infrastructure through high-density I/O and optical AI accelerators [23] - Integrating photonic functional devices into traditional digital infrastructure presents challenges that require further research into overall system design and implementation [23]