公众号记得加星标⭐️，第一时间看推送不会错过。 SK集团董事长崔泰元于20日（当地时间）表示，"SK海力士今年的营业利润预期可能超过1000亿美 元（约合145万亿韩元）。" 在当天于华盛顿特区萨拉曼德酒店举行的由切伊高级研究院主办的"跨太平洋对话（TPD）2026"欢迎 致辞中，切伊表示，"人工智能（AI）的普及正在从根本上改变半导体行业的结构"。 关于SK海力士的盈利前景，他表示："去年12月，我们预计今年的营业利润将超过500亿美元；今年1 月，我们认为可能会超过700亿美元；而现在新的估计是，可能会超过1000亿美元。" 他补充道："这听起来确实是个好消息，但同时也可能造成 1000 亿美元的损失。"他还说："市场波 动性非常高，新技术可能是一种解决方案，但也可能使一切付诸东流。" Chey补充道："我们正站在不可避免的变革的黎明，在这个变革过程中，人工智能正在吞噬一切。" SK海力士去年创下历史新高，销售额达98万亿韩元，营业利润达47万亿韩元。这一营业利润首次超 过三星电子的43.6万亿韩元，主要得益于高密度聚乙烯（HBM）需求的激增。 Chey评估认为，人工智能需求的爆炸式增长正在从根本上重塑内 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 三星电子时隔一年从SK海力士手中夺回了全球动态随机存取存储器（DRAM）市场的头把交椅。该 公司在高带宽内存（HBM）领域重获竞争力，而通用DRAM价格的上涨也显著提振了相关收入。业 内人士预计，鉴于通用DRAM价格持续高企，三星电子将继续保持领先地位。 据市场研究公司Omdia 22日发布的数据显示，去年第四季度全球DRAM市场总收入达到524.7亿美元 （约合76万亿韩元），较上一季度增长120亿美元（约合17万亿韩元）。DRAM价格的大幅上涨极大 地扩大了整体市场规模。 其中，三星电子的DRAM营收环比增长40.6%，达到191.56亿美元（约合27.7万亿韩元）。其市场份 额上升2.9个百分点至36.6%，重回第一。 同期，SK海力士DRAM营收增长25.2%至172.26亿美元（约合25万亿韩元），但市场份额从34.1%下 滑至32.9%，跌至第二位。SK海力士去年第一季度曾凭借HBM销售额的激增登上榜首，但一年后排 名再次发生变化。 不过，就目前而言，DRAM 比 HBM 更有利可图，因为 DRAM 价格飙升，使得三星电子缺乏降价以 获取更多市场份额 ...

Core Viewpoint - Nvidia is making a significant move into the CPU market, expanding its offerings beyond GPUs, particularly through a partnership with Meta to provide servers equipped with Nvidia Grace CPUs [2][4][5]. Group 1: Nvidia's CPU Strategy - Nvidia has signed a multi-year data center agreement with Meta, which includes the deployment of Nvidia Grace CPUs alongside Blackwell GPUs in Meta's data centers [2]. - The introduction of the Grace CPU marks Nvidia's first large-scale deployment in the server CPU market, indicating a strategic shift towards CPU offerings [4]. - Despite the focus on CPUs, Nvidia's commitment to GPUs remains strong, as the demand for powerful GPUs for large AI models continues to grow [5]. Group 2: Market Dynamics and Competition - Nvidia's entry into the CPU market poses a challenge to established players like Intel and AMD, especially as Intel faces production capacity constraints [6]. - The CPU market is experiencing a resurgence in demand, particularly for AI applications, which Nvidia aims to capitalize on with its new CPU offerings [5][6]. - Nvidia's strategy includes not only data center CPUs but also consumer-grade CPUs for laptops, aiming to leverage the success of ARM architecture in the PC market [8][11]. Group 3: Future Developments and Innovations - Nvidia is set to launch new PC processors, including the N1X and N1, which will utilize TSMC's 3nm process technology, targeting high-performance gaming laptops and compact desktops [9][10]. - The integration of CPU and GPU in a system-on-chip (SoC) design is a key focus, aiming to provide energy efficiency and performance similar to mobile devices [8][11]. - Nvidia's collaboration with MediaTek and Intel indicates a strategic approach to penetrate the PC market while addressing compatibility challenges with existing applications [10][12]. Group 4: Market Sentiment and Financial Outlook - Despite Nvidia's strong position in the AI GPU market, there are concerns about market sentiment and potential impacts on stock performance, as the company has seen limited stock price growth recently [14]. - Analysts express that while Nvidia's fundamentals remain strong, rising anxiety in the industry could affect investor confidence [14].

Core Viewpoint - The forum highlighted the importance of collaborative innovation in the semiconductor industry, showcasing Shanghai Xizhi Technology's achievements in optical-electrical integration and its flagship product, the Guangyue OP32 optical interconnect supernode solution, which addresses critical challenges in computing power interconnection [1][10]. Summary by Sections Event Overview - The "Collaborative Innovation Forum from Devices to Networks" was held on March 18, 2026, at the Shanghai New International Expo Center, organized by Semiconductor Industry Observation and Munich Shanghai Optical Expo, gathering over 200 industry elites [1]. Key Presentations - The agenda included various expert presentations on topics such as optical-electrical integrated chips, silicon photonics for high-speed AI connections, and advanced packaging innovations, emphasizing the collaborative nature of the semiconductor industry [3][4][5]. Shanghai Xizhi Technology's Innovations - Shanghai Xizhi Technology introduced its Guangyue OP32 solution, based on the world's first distributed optical switching dOCS chip, which allows flexible configuration and topology switching for GPU interconnections, significantly enhancing network efficiency and reducing deployment costs [5][6]. - The dOCS chip's design does not rely on advanced semiconductor process nodes, providing a secure supply chain defense and ensuring long-term stability for enterprises in a complex industrial environment [6] . Industry Collaboration - The forum emphasized the synergy between various companies, including Zhuhai Silicon Chip Technology and Shanghai BoPu Semiconductor, in advancing semiconductor innovations, collectively shaping a comprehensive innovation landscape from devices to networks [8]. - A roundtable discussion featured insights from industry representatives on key topics such as collaborative paths for the entire industry chain and the implementation of domestic technologies, highlighting the necessity of continuous breakthroughs in core technologies for high-quality development in the semiconductor sector [8][10].

Core Insights - The article discusses the increasing difficulty in chip design due to technological advancements, particularly focusing on the challenges posed by AI workloads and the transition to heterogeneous multi-chip designs. It highlights that the return on investment for advanced node scaling is being compressed in ways that many teams have yet to quantify [2]. Group 1: Challenges in 3nm Process - The clock margin in the 3nm process has expanded to 25% to 35% of the total clock cycle, driven by abstract sign-off methods leading to structural consequences [3]. - A 2.5x over-design trap exists where applying 28nm acceptance assumptions to 3nm designs forces designers to over-engineer clock networks, resulting in unnecessary costs for buffers, area, and wiring complexity [3]. - Near-threshold voltage effects can lead to an 8% to 12% increase in uncertainty, while power supply-induced jitter (PSIJ) and simultaneous switching can consume an additional 5% to 10% of margin [4]. Group 2: Economic Consequences - A 10% reduction in recoverable clock margin can lead to an 18% to 20% decrease in dynamic clock power, significantly impacting a design's competitiveness in its market segment [7]. - Recovering 10% of margin at a target frequency of 3 GHz could yield a frequency increase of 300 MHz, translating to hundreds of millions in additional revenue if production is shifted to higher performance product tiers [7]. - The forced increase in unit sizes due to abstract-driven margins can inflate chip sizes by 10% to 15%, raising unit costs for millions of chips [8]. Group 3: Solutions and Future Directions - The crisis stems from the fact that models have not kept pace with physical advancements, and the most direct solution to address structural pessimism is to replace timing abstractions with electrical resolution through detailed SPICE analysis [9]. - The competitive edge in advanced nodes increasingly relies on the ability to safely eliminate unnecessary margins rather than simply increasing them [9]. - Teams that directly address physical issues rather than approximating them will regain performance, energy efficiency, and yield lost due to uncertainty [9].

公众号记得加星标⭐️，第一时间看推送不会错过。 美国最高法院裁定美国总统川普根据"国际紧急经济权力法（IEEPA）"征收对等关税违法，川普宣布 改采"一九七四年贸易法"第122条对全球加征10%关税。学者坦言，现况变得更加复杂，因为川普不 仅强调232条款关税措施继续，还重提台湾偷走美国芯片产业。 台新新光金控首席经济学家李镇宇指出，IEEPA被否决不是削弱贸易战，而是让贸易战「合法化」， 从紧急命令变成产业调查，从总统裁量变成跨部门程序，这种制度型关税比川普的情绪式关税更持 久。他认为，政府和朝野不要误判可因此对美国食言或对既有承诺打折，这样的风险反而更大，因为 当行政弹性工具被限缩，美国会更倾向启动232或301等程序，谈判空间会更小，政治成本会更高。 川普在记者会中指出，厂商可以把产品外包到国外生产，让美国人民失业，甚至把所有人都推上失业 名单；但如果要在其他国家生产汽车，就必须支付15%、20%或30%的关税。他说，那些事情本来就 不该发生，美国不会因此失去自己的产业。 他接着表示："同样的事情也发生在台湾。台湾进来，他们偷走了我们的芯片产业，长期大量生产芯 片，把我们的公司挤下去，英特尔本来会是最大 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 为了应对生成式人工智能和基础模型计算需求的快速增长，IBM 研究院采用了全栈式方法，将人工 智能计算能力构建并集成到我们的系统产品中。IBM Spyre 加速器正是基于这种方法而诞生的。 企业工作负载由复杂的执行流程构成，其中会使用各种类型的模型来自动化决策。将人工智能集成到 企业工作负载中意味着在工作负载执行的不同阶段可能会使用多种不同的人工智能模型。因此，人工 智能加速器必须具备无缝的软件集成、灵活的硬件集成以及企业级的稳健性和可管理性。从人工智能 生命周期的角度来看，Spyre 的首要任务是加速推理。除此之外，我们还需要一种能够集成到多个 IBM 平台（尤其是 IBM Z 和 Power 系统）的解决方案。Spyre 的设计选择充分体现了这些考虑因 素。 Spyre AI 内 核 专 为 混 合 精 度 AI 数 学 运 算 而 设 计 。 每 个 Spyre AI 内 核 分 为 两 个 " 核 心 单 元"（corelet）。每个核心单元包含一个二维 8x8 SIMD 脉动阵列，用于矩阵乘法和卷积等运算；以 及两个一维向量阵列，用于激活/归一化函数和量 ...

Core Viewpoint - The semiconductor industry is transitioning from focusing on smaller chip sizes to integrating multiple smaller units (Chiplets) to overcome physical limitations in chip size and yield issues [2][5][10]. Group 1: Chip Size Limitations - The maximum area for a chip's photolithography mask is approximately 858 square millimeters, with NVIDIA's GH100 chip reaching 814 square millimeters, indicating a limit to chip size [2]. - As chip sizes increase, the yield issues become more pronounced, similar to painting on a larger canvas where defects affect more area [3]. Group 2: Chiplet Architecture - Chiplets allow for the division of large chips into smaller components, which can be manufactured separately and then assembled, improving yield and reducing costs [5][6]. - Each Chiplet can utilize different manufacturing processes, optimizing performance and cost [5]. Group 3: CoWoS Technology - CoWoS (Chip-on-Wafer-on-Substrate) architecture integrates multiple chips and requires a high-speed interconnect layer, which is critical for performance [7][9]. - The choice of materials for the interconnect layer significantly impacts performance, cost, and production capacity [9][10]. Group 4: Material Challenges - Organic substrates have dominated for 25 years but face limitations in high-performance applications, particularly with AI chips [10][14]. - Silicon interconnect layers provide better performance but are costly and resource-intensive, creating a bottleneck in production [18][19]. Group 5: Glass Substrate Potential - Glass substrates present a promising alternative, potentially matching silicon's thermal expansion properties and significantly reducing signal loss [25][27]. - Two approaches for glass use include replacing the interconnect layer or the substrate itself, each addressing different performance challenges [20][21]. Group 6: Industry Competition - Major players like Intel and Samsung are investing heavily in glass technology, with Intel showcasing prototypes and Samsung developing a vertical integration strategy [35][37]. - The competition is fierce, with companies like Absolics and SKC also exploring innovative solutions to meet the growing demand for AI chips [38][44]. Group 7: Future Outlook - The semiconductor industry is at a crossroads, with multiple technologies vying for dominance, including organic substrates, silicon interconnects, and emerging glass technologies [63]. - The future will depend on overcoming production challenges and achieving economic viability in new materials and methods [48][51].

Core Viewpoint - SK Hynix anticipates a continued upward trend in memory prices throughout the year due to strong demand driven by AI services and limited supply [4][5] Group 1: Memory Price Trends - The current upward trend in memory prices is expected to persist throughout the year, primarily driven by strong demand from AI customers [4] - Despite potential "despeccing" from PC and mobile users, limited supply growth is likely to keep prices rising [5] - A shortage of cleanroom space across the industry is contributing to supply constraints and a favorable pricing environment [5] Group 2: Inventory and Supplier Negotiation - Healthy inventory levels and enhanced supplier bargaining power are leading to increased discussions around long-term contracts [5] - SK Hynix notes that no customer can fully meet their memory needs this year, resulting in low demand fulfillment rates across all end markets [5] - The company is engaging in discussions for multi-year contracts with major clients, aiming to maximize future demand stability [6] Group 3: HBM Business Outlook - Current supply-demand tightness in traditional DRAM may lead to more favorable terms for the HBM business in 2027 [6] - Although there is potential for demand growth, significant changes to production plans for HBM and traditional DRAM in 2026 are deemed challenging [6] Group 4: Production Capacity and Technology Upgrades - SK Hynix will focus on increasing 1b nm DRAM capacity this year, primarily to support HBM3E and HBM4 supply [7] - The company plans to utilize 1c nm technology for HBM starting in 2027, with a significant portion of traditional DRAM expected to adopt this node by year-end [7] Group 5: Capital Expenditure Guidance - SK Hynix expects an increase in capital expenditures this year compared to last year, while maintaining capital expenditure discipline [8] - The company anticipates that the composition of wafer fab equipment (WFE) spending will remain similar to last year, with a focus on HBM and traditional DRAM [8]

Group 1 - The core issue in the semiconductor industry has shifted from visible contamination to atomic-scale contamination, where even trace materials can significantly alter surface behavior and device performance [4][10][29] - As technology nodes advance, the acceptable levels of contamination have drastically decreased, requiring precision at the atomic layer deposition level [7][8] - Modern contamination mechanisms are often hidden and accumulate over time, making them difficult to detect and manage, leading to reliability risks rather than immediate yield losses [19][22][30] Group 2 - Traditional pollution control methods focused on preventing harmful substances from entering the manufacturing environment, but at atomic scales, the focus must also include residual materials [4][10] - The impact of contamination is often indirect, manifesting as variability in device performance rather than discrete defects, complicating detection and classification [14][15] - Effective contamination management now requires a holistic approach that integrates material selection, tool design, process flow, and data analysis, rather than relying solely on cleaning [27][30]