Core Viewpoint - Apple's upcoming M5 chip for high-end MacBook Pro will feature a new Liquid Molded Plastic (LMC) supplied exclusively by Taiwan's Changxin Materials, which is expected to enhance performance and efficiency in the coming years [2][3]. Group 1: Chip Technology and Performance - The M5 chip will not fully utilize CoWoS technology initially, but the adoption of compatible materials is a strategic move for future iterations [3]. - LMC will provide advantages such as structural integrity, better heat dissipation, and higher manufacturing efficiency, contributing to stable performance and increased efficiency [3]. - Future M6 or M7 chips may fully adopt CoWoS or even CoPoS packaging technologies, allowing for larger and more complex processors capable of handling demanding workloads [3][4]. Group 2: Supply Chain and Procurement Strategy - Changxin Materials has outperformed Japanese suppliers Namics and Nagase to secure the contract, indicating a shift in Apple's procurement strategy towards greater reliance on Taiwanese suppliers [3]. - This change grants Apple more flexibility in control and R&D collaboration within advanced chip materials [3]. Group 3: Future Developments and Cost Considerations - Apple is exploring other packaging technologies to enhance chip performance and reduce costs, with the A20 series chips expected to transition from InFO to multi-chip module packaging (WMCM) by 2026 [6][7]. - WMCM will utilize Molding Underfill (MUF) technology, which integrates bottom filling and molding processes to reduce material consumption and improve yield and efficiency [7]. - Apple is also considering System on Integrated Chips (SoIC) technology for the M5 series, allowing for high-density connections between stacked chips to reduce latency and enhance performance [8].

最近市场炒得火热的芯片晶圆板封装（CoWoP）技术，与现有的CoWoS封装有什么区别？对供应 链有何影响？商业化前景如何？ 8月5日，据追风交易台消息，摩根大通在最新研报中称，英伟达正在探索一项革命性的芯片封装 技术CoWoP（Chip-on-Wafer-on-PCB），该技术有望替代现有的CoWoS封装方案。 摩根大通指出，这一技术变革将利用先进的高密度PCB（印刷电路板）技术，去除CoWoS封装中 的ABF基板层，直接将中介层与PCB连接。 如果您希望可以时常见面，欢迎标星收藏哦~ 来源 ：内容来自 钜亨网 。 摩根大通称，英伟达正在探索的芯片封装技术CoWoP，将利用先进的高密度PCB（印刷电路板） 技术，去除CoWoS封装中的ABF基板层，直接将中介层与PCB连接，具有简化系统结构，更好的 热管理性能和更低功耗等优势。该技术有望替代现有的CoWoS封装方案。 该行还在研报中详细分析了"CoWoP"技术对于供应链的影响，认为对ABF基板厂商显然是负面消 息，却是PCB制造商的重大机遇。 虽然，摩根大通分析师认为该技术在中期内商业化机率较低，主要受制于多重技术挑战，但是该行 在研报中强调：无论CoWoP是 ...

Core Viewpoint - Morgan Stanley reports that Nvidia is exploring a revolutionary chip packaging technology called CoWoP (Chip-on-Wafer-on-PCB), which is expected to replace the existing CoWoS packaging solution [4][5]. Group 1: CoWoP Technology Overview - CoWoP utilizes advanced high-density PCB technology to eliminate the ABF substrate layer found in CoWoS packaging, directly connecting the intermediary layer to the PCB [5][9]. - The potential advantages of CoWoP include simplified system architecture, improved thermal management, lower power consumption, and reduced substrate costs [18][20]. Group 2: Supply Chain Impact - The introduction of CoWoP is seen as negative news for ABF substrate manufacturers, as the added value of substrates may significantly decrease or disappear [14]. - Conversely, PCB manufacturers are presented with significant opportunities, as the technology shift may lead to increased demand for advanced PCB capabilities [15][6]. Group 3: Commercialization Challenges - Despite the potential benefits, Morgan Stanley analysts believe that the commercialization probability of CoWoP in the medium term remains low due to multiple technical challenges [7][17]. - Current PCB technologies, even with mSAP, can only achieve line/space widths of 20-30 microns, which is still far from the desired performance levels [20]. Group 4: Nvidia's Innovation Leadership - Regardless of the success of CoWoP, Nvidia continues to lead innovations in data center AI infrastructure through a system-level approach [23][24]. - Nvidia's ongoing exploration of CoWoS-L and CoPoS technologies, along with its potential leadership in large-scale CPO applications, is expected to maintain its competitive edge in the GPU market [24].

Core Viewpoint - The article discusses the emergence of CoWoP (Chip-on-Wafer-on-PCB) technology as a potential alternative to CoWoS (Chip-on-Wafer-on-Substrate) and CoPoS (Chip-on-Panel-on-Substrate), highlighting its advantages and disadvantages in semiconductor packaging [1][12][14]. Summary by Sections CoWoS Overview - CoWoS involves a three-stage packaging process where dies are connected to an interposer, which is then connected to a packaging substrate, followed by cutting the wafer to form chips [7]. CoPoS Technology - CoPoS replaces the wafer with a panel, allowing for a higher number of chips to be accommodated, thus improving area utilization and production capacity [11]. Introduction of CoWoP - CoWoP eliminates the packaging substrate, allowing chips to be directly soldered onto the PCB, which simplifies the design and reduces costs [12][14]. Advantages of CoWoP - CoWoP reduces packaging costs by eliminating the expensive packaging substrate, leading to lower material costs and reduced complexity [14]. - It offers shorter signal paths, enhancing bandwidth utilization and reducing latency for high-speed interfaces like PCIe 6.0 and HBM3 [15]. - The absence of a packaging cover allows for better thermal management options, which is beneficial for high-power AI chips [15]. Disadvantages of CoWoP - The direct attachment to the PCB increases the requirements for PCB reliability and precision, as the tolerance for errors is significantly reduced [16]. - The lack of protective packaging raises concerns about reliability under thermal cycling, mechanical stress, and transport vibrations [16]. - Successful implementation requires close collaboration between chip packaging and PCB manufacturing from the design stage, increasing supply chain management complexity [16]. Conclusion - CoWoP technology is considered aggressive and presents significant challenges, indicating that it may not have an immediate impact on all PCB companies in the short term [17].

Core Viewpoint - Intel has unveiled several breakthroughs in chip packaging technology at the Electronic Components Technology Conference (ECTC), focusing on the new EMIB-T technology, which enhances power delivery and communication efficiency for advanced chip designs, particularly for HBM4 integration [5][14][32]. Group 1: EMIB-T Technology - EMIB-T integrates Through-Silicon Vias (TSVs) into the existing EMIB technology, improving power delivery efficiency and enabling ultra-high-speed communications between dies [12][14]. - The technology supports larger package sizes exceeding 120 mm x 180 mm and allows for more than 38 bridges, with die-to-die interconnection pitch scaling below 45 micrometers [12][15]. - EMIB-T is designed to be a cost-effective and scalable solution for heterogeneous integration, facilitating the mix and match of different die types on a single package [12][14]. Group 2: Thermal Management Innovations - Intel has introduced a novel disaggregated heat spreader design that improves thermal interface material (TIM) coupling, reducing voids by 25% and effectively cooling processors with a thermal design power (TDP) of up to 1000W [19]. - A new thermo-compression bonding process has been developed to minimize warping during the bonding process, enhancing yield and reliability for large package substrates [23]. Group 3: Strategic Importance of Packaging Technology - Advanced packaging technology is crucial for Intel Foundry as it aims to provide comprehensive chip manufacturing options, allowing integration of various chip types from multiple suppliers [32]. - Intel's packaging services have become a leading offering for external customers, including major industry players like AWS and Cisco, as well as government projects, contributing significantly to revenue generation [32].