芯片封装技术

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三星或将投资入股英特尔!
国芯网· 2025-08-28 12:12
国芯网[原:中国半导体论坛] 振兴国产半导体产业! 不拘中国、 放眼世界 ! 关注 世界半导体论坛 ↓ ↓ ↓ 8月28日消息,韩国科技巨头三星电子董事长李在镕正在美国访问,有业内人士猜测,此行可能将促成 三星对美国半导体公司英特尔的投资。 消息称,由于台积电为人工智能芯片在封装业务上投入了大笔资金,三星可能将通过与英特尔的合作以 增强自己的竞争力,因为英特尔和台积电是全球仅有两家能够进行先进后段(BEOL)芯片制造的高端 芯片制造商。 消息人士指出,三星的兴趣还建立在另一个基础上,即如果将后端和前端芯片制造的市场份额合并,三 星在全球芯片制造市场上的地位不及英特尔。然而,一旦两家公司合作,它们将共享资源以追赶台积 电。 三星希望通过对英特尔的投资,一方面兑现投资美国半导体制造业的承诺,扩大在当地的业务,另一方 面与英特尔建立更紧密的合作关系。加上提供封装业务的Amkor也在考虑范围内,外界猜测三星的投资 与封装业务有关。 由于英特尔具备先进的混合键合封装能力,让三星产生了合作的兴趣。值得注意的是,如果将前道工艺 (FEOL)和后道工序的市场份额加在一起,三星在全球半导体制造上的市场份额其实是落后于英特 尔。 ...
苹果芯片,转向新封装
半导体芯闻· 2025-08-13 10:43
Core Viewpoint - Apple's upcoming M5 chip for high-end MacBook Pro will feature a new Liquid Molded Plastic (LMC) supplied exclusively by Taiwan's Changxin Materials, which is expected to enhance performance and efficiency in the coming years [2][3]. Group 1: Chip Technology and Performance - The M5 chip will not fully utilize CoWoS technology initially, but the adoption of compatible materials is a strategic move for future iterations [3]. - LMC will provide advantages such as structural integrity, better heat dissipation, and higher manufacturing efficiency, contributing to stable performance and increased efficiency [3]. - Future M6 or M7 chips may fully adopt CoWoS or even CoPoS packaging technologies, allowing for larger and more complex processors capable of handling demanding workloads [3][4]. Group 2: Supply Chain and Procurement Strategy - Changxin Materials has outperformed Japanese suppliers Namics and Nagase to secure the contract, indicating a shift in Apple's procurement strategy towards greater reliance on Taiwanese suppliers [3]. - This change grants Apple more flexibility in control and R&D collaboration within advanced chip materials [3]. Group 3: Future Developments and Cost Considerations - Apple is exploring other packaging technologies to enhance chip performance and reduce costs, with the A20 series chips expected to transition from InFO to multi-chip module packaging (WMCM) by 2026 [6][7]. - WMCM will utilize Molding Underfill (MUF) technology, which integrates bottom filling and molding processes to reduce material consumption and improve yield and efficiency [7]. - Apple is also considering System on Integrated Chips (SoIC) technology for the M5 series, allowing for high-density connections between stacked chips to reduce latency and enhance performance [8].
英伟达探索的CoWoP封装技术是什么?
半导体芯闻· 2025-08-07 10:33
Core Viewpoint - Morgan Stanley reports that Nvidia is exploring a revolutionary chip packaging technology called CoWoP (Chip-on-Wafer-on-PCB), which is expected to replace the existing CoWoS packaging solution [2][3]. Group 1: CoWoP Technology Analysis - CoWoP utilizes advanced high-density PCB technology, eliminating the ABF substrate layer found in CoWoS packaging, and directly connecting the intermediary layer to the PCB [4]. - The potential advantages of CoWoP include simplified system structure, improved thermal management, lower power consumption, reduced substrate costs, and potential reduction in backend testing steps [10]. Group 2: Supply Chain Impact - The introduction of CoWoP is seen as negative news for ABF substrate manufacturers, as the added value of substrates may significantly decrease or disappear [8]. - Conversely, PCB manufacturers are presented with significant opportunities, particularly those with advanced mSAP capabilities and deep knowledge of substrate/packaging processes [8]. Group 3: Commercialization Challenges - Morgan Stanley analysts believe that the commercialization probability of CoWoP in the medium term is low due to multiple technical challenges [3][9]. - Current PCB technologies, even with mSAP, can only achieve line/space widths of 20-30 microns, which is still far from the desired performance levels [11]. Group 4: Nvidia's Innovation Leadership - Regardless of the success of CoWoP, Nvidia continues to lead innovations in data center AI infrastructure through a system-level approach [12]. - Nvidia's ongoing innovation capabilities are expected to maintain its leading position in the GPU sector and dominate competition with ASICs in the coming years [12].
一文读懂英伟达下一代芯片封装技术“CoWoP”
硬AI· 2025-08-05 16:02
Core Viewpoint - Morgan Stanley reports that Nvidia is exploring a revolutionary chip packaging technology called CoWoP (Chip-on-Wafer-on-PCB), which is expected to replace the existing CoWoS packaging solution [4][5]. Group 1: CoWoP Technology Overview - CoWoP utilizes advanced high-density PCB technology to eliminate the ABF substrate layer found in CoWoS packaging, directly connecting the intermediary layer to the PCB [5][9]. - The potential advantages of CoWoP include simplified system architecture, improved thermal management, lower power consumption, and reduced substrate costs [18][20]. Group 2: Supply Chain Impact - The introduction of CoWoP is seen as negative news for ABF substrate manufacturers, as the added value of substrates may significantly decrease or disappear [14]. - Conversely, PCB manufacturers are presented with significant opportunities, as the technology shift may lead to increased demand for advanced PCB capabilities [15][6]. Group 3: Commercialization Challenges - Despite the potential benefits, Morgan Stanley analysts believe that the commercialization probability of CoWoP in the medium term remains low due to multiple technical challenges [7][17]. - Current PCB technologies, even with mSAP, can only achieve line/space widths of 20-30 microns, which is still far from the desired performance levels [20]. Group 4: Nvidia's Innovation Leadership - Regardless of the success of CoWoP, Nvidia continues to lead innovations in data center AI infrastructure through a system-level approach [23][24]. - Nvidia's ongoing exploration of CoWoS-L and CoPoS technologies, along with its potential leadership in large-scale CPO applications, is expected to maintain its competitive edge in the GPU market [24].
一文读懂英伟达下一代芯片封装技术“CoWoP”
Hua Er Jie Jian Wen· 2025-08-05 06:34
Core Viewpoint - Morgan Stanley's latest report highlights that Nvidia is exploring a revolutionary chip packaging technology called CoWoP (Chip-on-Wafer-on-PCB), which is expected to replace the existing CoWoS packaging solution [1] Group 1: CoWoP Technology Overview - CoWoP technology involves directly mounting the intermediary layer (with chips) onto the PCB after the chip-wafer intermediary layer manufacturing step, unlike CoWoS which binds to the ABF substrate [2] - The potential advantages of CoWoP include simplified system architecture, improved data transmission efficiency, better thermal management, lower power consumption, reduced substrate costs, and potential elimination of some backend testing steps [5] Group 2: Supply Chain Impact - The report indicates that the CoWoP technology poses a significant negative impact on ABF substrate manufacturers, as the added value of substrates may decrease or disappear, while PCB manufacturers stand to gain significantly [6] - The main challenge for PCB manufacturers is balancing performance with high current/voltage requirements, with mSAP being the best PCB technology for achieving finer line/space dimensions [6] Group 3: Commercialization Challenges - Morgan Stanley analysts believe that the probability of CoWoP's commercialization in the medium term is low due to multiple technical challenges [7] - Current PCB technology, even with mSAP, can only achieve line/space widths of 20-30 microns, which is still significantly below the desired performance [8] Group 4: Nvidia's Innovation Leadership - Regardless of the success of CoWoP, Nvidia continues to lead innovation in data center AI infrastructure through a system-level approach [9] - Nvidia's ongoing innovation capabilities are expected to maintain its leading position in the GPU sector and dominate competition with ASICs in the coming years [9]
CoWoS的下一代是CoPoS还是CoWoP?
傅里叶的猫· 2025-07-28 15:18
Core Viewpoint - The article discusses the emergence of CoWoP (Chip-on-Wafer-on-PCB) technology as a potential alternative to CoWoS (Chip-on-Wafer-on-Substrate) and CoPoS (Chip-on-Panel-on-Substrate), highlighting its advantages and disadvantages in semiconductor packaging [1][12][14]. Summary by Sections CoWoS Overview - CoWoS involves a three-stage packaging process where dies are connected to an interposer, which is then connected to a packaging substrate, followed by cutting the wafer to form chips [7]. CoPoS Technology - CoPoS replaces the wafer with a panel, allowing for a higher number of chips to be accommodated, thus improving area utilization and production capacity [11]. Introduction of CoWoP - CoWoP eliminates the packaging substrate, allowing chips to be directly soldered onto the PCB, which simplifies the design and reduces costs [12][14]. Advantages of CoWoP - CoWoP reduces packaging costs by eliminating the expensive packaging substrate, leading to lower material costs and reduced complexity [14]. - It offers shorter signal paths, enhancing bandwidth utilization and reducing latency for high-speed interfaces like PCIe 6.0 and HBM3 [15]. - The absence of a packaging cover allows for better thermal management options, which is beneficial for high-power AI chips [15]. Disadvantages of CoWoP - The direct attachment to the PCB increases the requirements for PCB reliability and precision, as the tolerance for errors is significantly reduced [16]. - The lack of protective packaging raises concerns about reliability under thermal cycling, mechanical stress, and transport vibrations [16]. - Successful implementation requires close collaboration between chip packaging and PCB manufacturing from the design stage, increasing supply chain management complexity [16]. Conclusion - CoWoP technology is considered aggressive and presents significant challenges, indicating that it may not have an immediate impact on all PCB companies in the short term [17].
英特尔先进封装,新突破
半导体行业观察· 2025-05-31 02:21
Core Viewpoint - Intel has unveiled several breakthroughs in chip packaging technology at the Electronic Components Technology Conference (ECTC), focusing on the new EMIB-T technology, which enhances power delivery and communication efficiency for advanced chip designs, particularly for HBM4 integration [5][14][32]. Group 1: EMIB-T Technology - EMIB-T integrates Through-Silicon Vias (TSVs) into the existing EMIB technology, improving power delivery efficiency and enabling ultra-high-speed communications between dies [12][14]. - The technology supports larger package sizes exceeding 120 mm x 180 mm and allows for more than 38 bridges, with die-to-die interconnection pitch scaling below 45 micrometers [12][15]. - EMIB-T is designed to be a cost-effective and scalable solution for heterogeneous integration, facilitating the mix and match of different die types on a single package [12][14]. Group 2: Thermal Management Innovations - Intel has introduced a novel disaggregated heat spreader design that improves thermal interface material (TIM) coupling, reducing voids by 25% and effectively cooling processors with a thermal design power (TDP) of up to 1000W [19]. - A new thermo-compression bonding process has been developed to minimize warping during the bonding process, enhancing yield and reliability for large package substrates [23]. Group 3: Strategic Importance of Packaging Technology - Advanced packaging technology is crucial for Intel Foundry as it aims to provide comprehensive chip manufacturing options, allowing integration of various chip types from multiple suppliers [32]. - Intel's packaging services have become a leading offering for external customers, including major industry players like AWS and Cisco, as well as government projects, contributing significantly to revenue generation [32].