如果您希望可以时常见面，欢迎标星收藏哦~ 因为智能汽车的崛起，过去几年Serdes芯片市场关注度飞升。 根据盖世汽车研究院经分析预测，至2023年全球车载SerDes芯片市场规模就将达到数十亿美元， 未来十年，这一市场将朝着百亿美元规模高速发展。这其中，基于中国智能驾驶发展现况及潜力， 有望占四成。 然而在这巨大的机遇背后，SerDes芯片存在一些固有的格局。例如迄今，这个市场主要是由ADI 和TI两家模拟芯片供应商把持，他们分别利用GMSL和FPD-Link的先发优势统领了市场。由于这 两家厂商的协议都是私有的，这就让其他想插足这个市场的厂商各出奇招。 但随着GMSL官宣开源以后，SerDes市场一夜生变。 SerDes，双王争霸 如上所述，SerDes是一个双王争霸的市场。当中，FPD-Link（Flat Panel Display Link）是由美 国国家半导体公司（现隶属于德州仪器）于 1996 年创建的原始高速数字视频接口。FPD-Link 是 低压差分信号(LVDS) 标准的首个大规模应用。美国国家半导体公司立即为 FPD-Link 技术提供了 互 操 作 性 规 范 ， 以 推 广 其 作 为 ...

Core Viewpoint - Co-packaged optics (CPO) technology is emerging as a promising solution to enhance bandwidth and energy efficiency in data centers, particularly for applications involving generative AI and large language models. However, manufacturing challenges remain, particularly in fiber-to-photonics integrated circuit (PIC) alignment, thermal management, and optical testing strategies [1][20]. Group 1: CPO Technology and Benefits - CPO enables network switches to route signals at speeds of terabits per second while significantly improving bandwidth and reducing power consumption required for AI model training [1][20]. - The technology achieves a bandwidth density of 1 Tbps/mm, optimizing rack space in increasingly crowded data centers [1][6]. - CPO can reduce power consumption associated with high-speed data transmission from approximately 15 pJ/bit to around 5 pJ/bit, with expectations to drop below 1 pJ/bit [6][7]. Group 2: Manufacturing Challenges - Key challenges in CPO manufacturing include achieving precise alignment between fiber and PIC, which is critical for effective optical signal coupling [8]. - The most common passive alignment method is the V-groove technique, which connects the fiber directly to the PIC to minimize loss [8][9]. - Efficient coupling between standard single-mode fibers and silicon waveguides is complicated due to significant differences in size and refractive index, leading to potential light loss [8][9]. Group 3: Thermal Management - CPO systems are sensitive to temperature fluctuations caused by high-power devices like GPUs and ASICs, which can affect the performance of photonic devices [11][12]. - A temperature change of just 1°C can lead to approximately 0.1nm wavelength shift in most photonic systems, necessitating careful thermal management strategies [11][12]. - Advanced thermal interface materials and monitoring circuits are deployed to maintain PIC temperature within predefined ranges [11][13]. Group 4: Reliability Design - Ensuring reliability in CPO systems is crucial, especially with multi-chip integration, requiring known good die (KGD) testing and optical testing solutions [14][16]. - High reliability designs incorporate redundancy, such as backup lasers, to maintain operation in case of component failure [15][16]. - Integrated monitoring and self-correcting features are being developed to detect performance degradation and facilitate quick recovery [15][16]. Group 5: Integration Techniques - Both 2.5D and 3D packaging methods are utilized in CPO, with 2.5D placing electronic ICs and PICs side by side on a silicon interposer [17][18]. - 3D integration allows for optimal manufacturing processes for each chip type, enhancing performance while increasing complexity and cost [18][19]. - The integration of optical features with traditional CMOS processes is becoming more compatible, facilitating advancements in CPO technology [17][18].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 9to5mac 。 苹果计划为2026款iPhone彻底革新其芯片设计，此举可能标志着该公司首次在移动设备中使用先 进的多芯片封装技术。这听起来很复杂，但这意味着什么呢？ 据分析师 Jeff Pu 在为广发证券撰写的新报告中称，iPhone 18 Pro、18 Pro Max 以及传闻已久的 iPhone 18 Fold预计将首次搭载苹果的 A20 芯片，该芯片基于台积电第二代 2nm 工艺（N2）打 造。 但这只是故事的一部分。更有趣的是这些芯片将如何组装。 苹 果 将 首 次 在 其 iPhone 处 理 器 中 采 用 晶 圆 级 多 芯 片 模 块 (WMCM ： Wafer-Level Multi-Chip Module) 封装。WMCM 允许将 SoC 和 DRAM 等不同组件直接集成在晶圆级，然后再切割成单 个芯片。 它采用一种无需中介层或基板即可连接芯片的技术，从而可以带来热完整性和信号完整性方面的好 处。 众所周知，在芯片行业，有一种根据硅晶圆的制造差异将芯片分级的技术，具体而言，将其划分为 不同性能等级的一种工艺。这些差异可能由 ...

Core Viewpoint - Cornelis Networks has launched the CN5000 series, a 400Gbps Omni-Path technology aimed at enhancing AI and HPC performance, with plans for future UltraEthernet integration [1][19]. Group 1: Product Overview - The CN5000 series is designed for AI and HPC applications, supporting deployments of up to 500,000 endpoints and providing advanced lossless data transmission and congestion avoidance features [19][20]. - The CN5000 utilizes Omni-Path architecture, which includes credit-based flow control and dynamic fine-grained adaptive routing to ensure high performance and reliability [20][22]. - The series includes both air-cooled and liquid-cooled switch options, addressing the cooling needs of large AI companies [5][22]. Group 2: Performance Metrics - The CN5000 demonstrates superior performance in HPC workloads, achieving up to 30% faster execution in computational fluid dynamics and climate modeling compared to InfiniBand NDR [22]. - For AI applications, the CN5000's collective communication speed is six times faster than RoCE, enhancing the efficiency of large language model training [19][22]. Group 3: Future Developments - The upcoming CN6000 series, set for release in 2026, will integrate Omni-Path with Ethernet support, doubling bandwidth capabilities [16][21]. - The CN7000 series, expected in 2027, will combine UltraEthernet standards with Omni-Path architecture, targeting the most demanding AI and HPC environments [17][21]. Group 4: Market Positioning - Cornelis Networks aims to provide a cost-effective alternative to NVIDIA's InfiniBand, capitalizing on the growing demand for high-performance networking solutions in AI and HPC sectors [18][19].

先进封装成为下１个技术帝国的边疆要塞，不是偶然，而是3股力道推动出来的必然结果。 第1股力道是算力井喷，但制程进展放缓，芯片必须被切割、堆叠、重组。陆行之表示，你能做到 5奈米，不代表你能塞进20倍算力，光罩极限挡住了芯片的面积，只有Chiplet 能绕过这道墙， Ncidia Blackwell 就是这样诞生的。 第2股力道则是应用百变，芯片不再单一适配，系统设计走向模组化。陆行之说，1种芯片搞定所 有应用的时代已经结束，AI训练、自驾决策、边缘运算、AR装置……每1个应用都需要不同组合 的矽，先进封装加Chiplet，就是设计弹性与效率的平衡解答。 如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容来自 自由时报 。 半导体的改变正在加速，先进封装，不再是边角料。知名分析师陆行之表示，棋盘中央如果说先进 制程是矽时代的权力中枢，那么先进封装，正在成为下１个技术帝国的边疆要塞。 陆行之在脸书上贴文指出，10年前，这条路线曾被误解，甚至被忽视，但10年后的今天，它已悄 悄从「非主流的Plan B」变成「主流赛道的Plan A」。 第3股力道则是资料搬运成本飙升，能耗变成第１瓶颈。在AI 芯片里，搬资料的耗能 ...

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内 容 综合自 theinformation 。 虽然麻烦一直增加，但英伟达还是尝试向中国销售其人工智能芯片，人们可能会想知道为什么该公 司还要继续坚持。 答案是：它实在承受不起不这么做的后果。 英伟达上周发布的第一财季财报，向特朗普政府发出了一个相当严厉的信号，即将美国芯片公司排 除在中国人工智能市场之外的危险。英伟达首席执行官黄仁勋在公司电话会议上表示："无论有没 有美国芯片，中国的人工智能都会继续发展。" 黄仁勋指出，全球一半的人工智能开发者都在中 国，阻止美国公司在中国竞争最终可能会让美国失去在全球人工智能领域的领先地位。 "最终，赢得人工智能开发者的平台才能赢得人工智能，"黄仁勋说道。"出口管制应该加强美国平 台，而不是将全球一半的人工智能人才赶往竞争对手。" 英伟达也有充分的财务理由来支持这一论点。美国政府今年4月决定禁止该公司向中国市场销售其 H20芯片，导致该公司在截至4月底的季度损失了约25亿美元的销售额，并将在截至7月底的当前季 度再损失80亿美元。这是因为H20芯片是专门为中国市场设计的，以符合当时的出口限制，因此在 其他任何地方都无法销售 ...

Core Viewpoint - China's self-sufficiency rate in AI chips is expected to exceed 80% within three years, driven by the need to overcome U.S. semiconductor export controls, which have catalyzed the strengthening of China's semiconductor ecosystem [1][2]. Group 1: AI Chip Self-Sufficiency - As of last year, China's self-sufficiency rate in AI chips was only 34%, but it is projected to soar to 82% by 2027 [1]. - The external pressure from U.S. sanctions has accelerated China's efforts to achieve self-sufficiency, leading to the rapid establishment of a self-sustaining ecosystem [1]. Group 2: Talent and Strategic Investment - Approximately half of the world's AI researchers are based in China, which is a significant driver for the explosive growth of the AI sector [2]. - China is investing heavily in its AI ecosystem through substantial R&D funding and policies favoring domestic procurement, leveraging its large domestic market to support local companies [2]. Group 3: Robotics Market Potential - The humanoid robot market is expected to grow to $5 trillion by 2050, with China projected to capture 30% of the global supply due to cost competitiveness from domestic AI chip procurement [3]. - Manufacturing humanoid robots in China could reduce production costs to one-third of those using global supply chains [3]. Group 4: Ecosystem and Industry Growth - Leading companies in China's AI rise include Huawei, SMIC, Alibaba, Tencent, and others, all contributing to accelerated AI innovation [3]. - By 2030, the core AI industry in China is expected to grow to 1 trillion RMB (approximately 190 trillion KRW) [3]. - The competitive landscape is shifting from merely acquiring high-spec semiconductor chips to effectively integrating hardware with software and systems to create value [3].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 koreajoongangdaily 。 为 了 重 夺 其 在 芯 片 行 业 的 主 导 地 位 ， 日 本 采 取 了 大 胆 举 措 ， 瞄 准 了 韩 国 半 导 体 领 域 的 " 皇 冠 明 珠"——用于人工智能（AI）的存储芯片。 该项目旨在开发用于人工智能应用的下一代存储芯片，整合了软银的资金支持、英特尔的技术、东 京大学的科研实力，以及日本在材料、零部件和设备方面的优势。 据日本财经报纸《日经新闻》周六报道，软银和英特尔成立了一家名为Saimemory的公司，致力于 引领人工智能低功耗存储芯片的研发。该公司的目标是开发高带宽内存（HBM）的替代方案，目 前HBM市场由韩国芯片制造商主导。HBM是一种先进的内存技术，堆叠了多层动态随机存取存储 器（DRAM），用于英伟达和AMD等公司生产的人工智能加速器。SK海力士和三星电子控制着全 球约90%的HBM市场。 但软银和英特尔并不打算在HBM领域直接竞争，而是计划开发一种能够显著降低功耗的"堆叠式 DRAM芯片"。这实际上是在寻求重塑市场，而非进入现有市场。 据东京电视台报道，Sai ...

Core Viewpoint - Major technology companies like Apple, MediaTek, and Qualcomm are targeting TSMC's 2nm process, which has begun accepting orders at a cost of $30,000 per wafer, presenting a significant challenge for the next generation of process nodes. The subsequent 1.4nm "A" process is expected to be even more expensive, with costs potentially reaching $45,000 per wafer, a 50% increase compared to the 2nm node [1][3][12]. Summary by Sections 1.4nm Process Cost and Features - TSMC's A14 (1.4nm) manufacturing technology promises significant improvements in performance, power consumption, and transistor density compared to the N2 (2nm) process. The A14 process is expected to cost up to $45,000 per wafer, which is a 50% increase from the 2nm node [3][5]. - The A14 process will utilize TSMC's second-generation GAA (Gate-All-Around) nanosheet transistors and NanoFlex Pro technology, which allows for greater design flexibility. It is projected to achieve a 10-15% speed improvement, a 25-30% reduction in power consumption, and a logic density increase of approximately 1.23 times compared to the N2 process [5][7]. Potential Customers for 1.4nm Process - TSMC's top customers, including Nvidia, Apple, MediaTek, Intel, Qualcomm, and Broadcom, are likely to adopt the 1.4nm process. Nvidia is expected to significantly increase its contribution to TSMC's revenue, projected to rise from 5-10% in 2023 to over 20% by 2025 [8][9]. - Apple is anticipated to place orders worth approximately NT$1 trillion (around $33 billion) for 2nm technology by 2025, which could increase its share of TSMC's revenue significantly [9][10]. Future Cost Trends - The costs of wafers are expected to continue rising, with the 1.4nm process not utilizing expensive High NA EUV lithography technology, indicating potential for further price increases in future nodes [12][13]. - Analysis suggests that if the light source power does not increase, the overall lithography costs for future nodes could rise by up to 20% compared to the current 3nm baseline [14][16]. - The semiconductor industry is observing rising costs in EDA and IP, which may contribute to the overall increase in chip production costs in the future [17].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 eenewseurope 。 四十年前，一种可以在工程师的办公桌上进行逻辑编程的革命性设备问世了。 Xilinx 开发的现场可编程门阵列 (FPGA) 使工程师能够将包含自定义逻辑的比特流下载到桌面编 程器中立即运行，而无需等待数周才能从晶圆厂返回芯片。而且，如果出现错误或问题，也可以立 即对设备进行重新编程。 AMD（该公司于2022年收购了赛灵思）产品、软件和解决方案副总裁柯克·萨班（Kirk Saban）告 诉eeNews Europe："我从1999年开始从事FPGA编程，至今已涉足FPGA领域27年。它可能是鲜 为 人 知 的 半 导 体 类 型 之 一 。 人 们 知 道 什 么 是 CPU ， 随 着 人 工 智 能 的 发 展 ， 人 们 也 知 道 什 么 是 GPU，但对FPGA的了解却较少。" 第一颗芯片 XC2064 于 1985 年 6 月问世，但这当然是经过了多年的研发，以及当年早些时候的 设计和流片。它拥有 600 个门电路和 64 个可配置逻辑块，运行频率为 70MHz。但这是一个巨大 的进步，让这款芯片载入了半导体 ...