Core Viewpoint - The article discusses the advancements in high numerical aperture (NA) EUV lithography systems, particularly the transition from 0.33 NA to 0.55 NA, highlighting the implications for multi-patterning techniques and image quality [1][3]. Group 1: Numerical Aperture and Imaging - The increase in numerical aperture (NA) from 0.33 to 0.55 allows for the use of more diffraction orders, resulting in brighter and narrower peaks in imaging [1][3]. - Higher NILS (Normalized Image Log Slope) is achieved due to sharper peaks, which reduces the impact of random effects from photon absorption noise [3][11]. - Direct printing images at 0.33 NA are more prone to quality degradation compared to 0.55 NA, necessitating higher doses to maintain low noise levels [3][13]. Group 2: Multi-Patterning Techniques - The article illustrates that DUV (Deep Ultraviolet) double patterning can achieve similar results to EUV by splitting patterns into separate exposures, improving NILS due to increased spatial frequency range [5][9]. - It is anticipated that high NA EUV will require two patterning steps, while low NA EUV will require three, and DUV will require four [5][9]. Group 3: Depth of Focus and Resist Thickness - The article emphasizes that higher numerical apertures lead to a wider range of spatial frequencies, which can result in greater phase differences and loss of image contrast due to defocus [9][11]. - A depth of focus less than 30 nanometers for high NA systems implies that resist thickness must also be under 30 nanometers, potentially leading to significant resist loss [13][15]. - The article suggests that future hyper NA systems (at least 0.75) may exacerbate these issues, as they are unlikely to provide sufficient depth of focus for reasonable resist thickness [13].

如果您希望可以时常见面，欢迎标星收藏哦~ 在这些加速器中，图形处理单元 (GPU) 已被证明在利用数据并行性进行机器学习和信号处理任务 方面尤为有效。当与主机 CPU 结合使用时，GPU 可形成加速处理单元 (APU)，从而实现一个统 一的平台，能够高效处理通用任务和计算密集型工作负载。 虽 然 存 在 各 种 GPU 实 现 方 案 ， 从 高 性 能 到 嵌 入 式 解 决 方 案 ， 但 它 们 在 超 低 功 耗 边 缘 设 备 （TinyAI）环境下的权衡利弊仍未得到深入研究。这些电池供电的设备在严格的功耗限制下运 行，通常在几十毫瓦的范围内，因此需要高效的 GPU 架构。 它们小巧的外形也对面积造成了严格的限制，完整的片上系统 (SoC) 仅占用几平方毫米的面积。 此 外 ， 由 于 缺 乏 文 件 系 统 和 多 线 程 支 持 ， 传 统 的 GPU 编 程 框 架 （ 例 如 标 准 开 放 计 算 语 言 (OpenCL) 实现）无法使用，因此需要进行自定义优化。 图形处理单元 (GPU) 擅长并行处理，但由于其功耗和面积限制，以及缺乏合适的编程框架， 在超低功耗边缘设备 (TinyAI) ...

Core Viewpoint - Broadcom has launched its next-generation switch ASIC, the Tomahawk 6 series, which features a bandwidth of 102.4Tbps and supports up to 64 ports of 1.6TbE, marking a transition from the gigabit era to the "terabit" era [1][33]. Group 1: Product Features - The Tomahawk 6 series includes two new ASICs, BCM78910 and BCM78914, designed for different applications with enhanced bandwidth capabilities [1]. - The new switch chips require SerDes for powering ports and improving load balancing and telemetry performance [1]. - The switches can scale vertically, providing massive bandwidth between fewer nodes, or horizontally, connecting numerous accelerators and nodes [3][11]. Group 2: Scalability and Cost Efficiency - The new architecture allows for the configuration of up to 512 XPUs using 200G PAM4 options, enabling significant scalability [11]. - By using fewer switches and switch layers, the overall network costs can be reduced despite the higher cost of new switches, as savings come from reduced quantities of switches, fiber, cables, and power [15]. - The transition to terabit Ethernet and faster switching speeds is beneficial for expanding larger network topologies with fewer switch layers, which is crucial in the growing AI cluster environment [33]. Group 3: Market Position and Challenges - Broadcom faces significant challenges as NVIDIA effectively locks its accelerator ecosystem to non-NVIDIA NICs and PCIe switches, impacting Broadcom's competitive position in the AI sector [34]. - The market is beginning to differentiate, with NVIDIA's recent announcements potentially undermining Broadcom's traditional AI market competition [35]. - Broadcom's ASICs are now the largest in the market, but the competitive landscape is evolving rapidly with new entrants like Astera Labs [39].

如果您希望可以时常见面，欢迎标星收藏哦~ 意法半导体首席执行官周三表示，预计未来三年将有 5,000 名员工离职，其中包括今年早些时候 宣布的 2,800 个裁员计划。 让-马克·切里 (Jean-Marc Chery) 在法国巴黎银行于巴黎主办的一场活动上表示，约有 2,000 名员 工将因自然减员离开这家法意芯片制造商，使自愿离职的员工总数达到 5,000 人。 首席执行官补充说，与利益相关者和当局就实施削减成本计划的讨论正在顺利进行。 他显然指的是意大利，他说道："我确实认为，某个国家的情况更糟。而且很有可能，好吧，会稍 微延缓我们的实施速度。"切瑞说道。 过去几个月，由于意法半导体在其主要市场面临持续低迷，意大利政府对该公司首席执行官表示不 满，并指控其进行内幕交易。意法半导体否认了这些指控。 意大利和法国政府通过一家控股公司持有意法半导体 27.5% 的股份，该公司在全球拥有 50,000 名员工。 去年 11 月，意法半导体详细制定了其成本削减计划，预计到 2027 年将节省数亿美元，其中包括 裁员和提前退休。 来源：内容综合自路透社等 。 今年 4 月，意法半导体表示，由于自愿离职，该公司将在法 ...

如果您希望可以时常见面，欢迎标星收藏哦~ "所有交易都在向好的方向发展，唯一没有达成的交易是那些本来就不应该达成的交易，"卢特尼克 说道，这似乎暗示并非所有奖项都能通过重新谈判获得成功。 拜登于 2022 年签署了《芯片与科学法案》，投入 527 亿美元用于促进美国半导体芯片的制造和 研究，并吸引芯片制造商离开亚洲。 该计划向台湾台积电、韩国三星和 SK 海力士以及美国英特尔和美光等半导体巨头提供了数十亿美 元的资助。 来源：内容综合自路透社 。 美国商务部长霍华德·卢特尼克 (Howard Lutnick) 在周三的听证会上表示，唐纳德·特朗普总统的 政府正在重新谈判前总统乔·拜登向半导体公司提供的一些拨款，暗示一些奖项可能会被取消。 卢特尼克对参议院拨款委员会的议员们表示，拜登时代的一些拨款"似乎过于慷慨，我们已经能够 重新进行谈判"，并补充说，目标是让美国纳税人受益。 这些拨款虽然已签署，但在拜登卸任时才刚刚开始发放。这些计划的细节尚未公开，但预计随着企 业在承诺的工厂扩建方面取得进展，这些资金将会发放。 卢特尼克指出，台积电就是成功重新谈判的一个例子。他表示，这家芯片制造商——赢得了60亿 美元的《芯 ...

Core Insights - Lisa Su, CEO of AMD, emphasizes the importance of curiosity and seizing opportunities in career development, highlighting her journey from near bankruptcy to industry leadership [1][12][13] - The semiconductor industry is undergoing significant transformations, with AMD focusing on high-performance computing and adapting to market changes [12][15][17] - Su encourages the next generation to dream big and embrace the opportunities presented by the current technological wave, particularly in artificial intelligence [1][24][25] Group 1: Career Development and Leadership - Lisa Su's early curiosity about technology led her to pursue a career in semiconductors, where she found her passion [4][5] - The importance of learning from experiences and being open to opportunities is a recurring theme in Su's career [5][6][8] - Su's transition from engineering to management was driven by her desire to lead teams and make a larger impact [5][10] Group 2: AMD's Transformation and Strategy - Under Su's leadership, AMD shifted from a struggling company to a leader in high-performance computing, with stock prices rising significantly [13][14] - The company strategically chose to focus on markets where it could excel, particularly in high-performance computing rather than mobile chips [14][15] - Su emphasizes the need for long-term vision and adaptability in decision-making, especially in a rapidly changing industry [15][16] Group 3: Industry Trends and Future Outlook - The semiconductor industry is at a crossroads, with significant opportunities arising from technological advancements and geopolitical factors [17][18] - AMD is positioning itself to leverage artificial intelligence and other emerging technologies to drive future growth [19][20] - Su believes that the future of computing will be shaped by the ability to solve complex problems and improve productivity through technology [24][25]

Core Insights - The article discusses the rapid growth of Ethernet networks and the competition among major players like Broadcom, Cisco, and Nvidia in the Ethernet switch ASIC market, particularly in the context of AI advancements [1][2][3] - Broadcom's Tomahawk 6 ASIC is highlighted as a leading product, with capabilities of 102.4 Tb/s and future versions expected to reach 204.8 Tb/s and 409.6 Tb/s, which are crucial for AI applications [2][3][10] - The article emphasizes the shift in enterprise networks towards higher-speed Ethernet, driven by the demands of AI workloads, which may accelerate the adoption of 100 Gb/s, 200 Gb/s, and even 400 Gb/s Ethernet [2][3] Summary by Sections Ethernet Network Growth - Ethernet networks are experiencing significant growth, allowing switch manufacturers to maintain business growth despite challenges [1] - The UltraEthernet Consortium aims to support 1 million GPU endpoints, necessitating larger capacity switch ASICs [1] Competition in the ASIC Market - Broadcom faces competition from Cisco and Nvidia, with its Tomahawk 6 ASIC leading the market with a focus on high bandwidth and cost efficiency [2][3] - The introduction of co-packaged optical devices is anticipated to reduce costs and expand network coverage [2] AI and Ethernet Adoption - The enterprise market has been slow to transition from 10 Gb/s to 100 Gb/s Ethernet, but AI's influence may accelerate this shift [2] - AI backend demands are expected to drive the adoption of higher-speed Ethernet in enterprise settings [2] Tomahawk 6 ASIC Features - Tomahawk 6 is designed to meet the bandwidth, low latency, and high base requirements of AI training and inference applications [6] - The chip utilizes a 3nm process technology, offering significant improvements in performance and efficiency compared to previous generations [10][11] Cost and Efficiency - The article discusses how the design of Tomahawk 6 allows for a reduction in the number of chips needed for equivalent performance, thereby lowering costs [8][15] - The transition to Tomahawk 6 is expected to significantly reduce power consumption compared to older ASICs, which is critical for large-scale AI deployments [15] Market Demand and Future Outlook - There is immense pressure from OEMs and cloud builders to bring Tomahawk 6 to market quickly, with expectations for product readiness by early 2026 [12][15] - The architecture of Tomahawk 6 enables efficient scaling of AI clusters, which is essential for modern data center requirements [14]

Core Viewpoint - Micron Technology presented its latest 3D NAND flash technology, the ninth generation (G9), at the 2025 IEEE International Memory Workshop, highlighting significant advancements in storage density and data transfer speeds while maintaining the same storage capacity per chip as the previous generation [1]. Summary by Sections G9 3D NAND Flash Technology - The G9 3D NAND flash has a storage capacity of 1 Tbit per chip, the same as the G8, but with a 40% increase in storage density of the memory cell array and a 30% increase in chip storage density [1]. - The maximum data transfer speed of G9 has improved by 1.5 times compared to G8 [1]. - The number of word line layers in G9 is 276, only a 19% increase from the 232 layers in G8, indicating that innovations beyond just increasing layer count contributed to the density improvements [1]. Storage Density Improvements - The storage density of Micron's memory cell array increased from 17 Gbit/mm² in G7 to 25 Gbit/mm² in G8, and further to 35 Gbit/mm² in G9 [3]. - Innovations include the removal of virtual pillars, which reduced block height by approximately 14%, and a decrease in the number of page buffers from 16 in G8 to 6 in G9, halving the page buffer's chip area [3]. Future Technology Challenges - The future of 3D NAND flash technology, including G10 and beyond, will face increasing technical challenges, akin to climbing an infinitely long spiral staircase [5]. - The introduction of "Confined SN" technology aims to reduce interference between adjacent cells, resulting in a 10% reduction in programming time and a 50% decrease in coupling capacitance between adjacent cells [9]. Innovations and Solutions - The G9 stack height exceeds 13 μm, with a layer height of 6.5 μm, and a high aspect ratio of over 43 due to the small diameter of storage holes [7]. - To mitigate electrical interference, Micron introduced air gaps in the insulation film and limited the nitrogen film to the gate side of the cell transistors [7][8]. - The transition from charge trapping to ferroelectric polarization is proposed as a solution to reduce the risk of dielectric breakdown, which is critical as the number of layers increases [16]. Cost and Performance Considerations - Micron is exploring wafer bonding technology to optimize the performance of peripheral circuits and memory cell arrays, despite the initial increase in costs associated with wafer bonding [12]. - The cost of wafer bonding is expected to decrease with each new technology generation, potentially becoming more cost-effective than single-chip manufacturing in the future [12][14].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 IEEE 。 纳文·维尔马在普林斯顿大学的实验室就像一座博物馆，展示了工程师们尝试利用模拟现象而非数 字计算来提高人工智能效率的各种方法。其中一个工作台上摆放着迄今为止最节能的基于磁存储器 的神经网络计算机。在另一个工作台上，你会发现一个基于电阻存储器的芯片，它可以计算迄今为 止任何模拟人工智能系统中最大的数字矩阵。 维尔马表示，这两种材料都没有商业前景。更糟糕的是，他的实验室这部分简直就是一片坟场。 多年来，模拟人工智能一直吸引着芯片架构师的想象力。它结合了两个关键概念，可以大幅降低机 器学习的能耗。首先，它限制了存储芯片和处理器之间昂贵的比特移动。其次，它利用电流流动的 物理原理，而不是逻辑上的1和0，来高效地进行机器学习的关键计算。 在机器学习中，"很偶然地，我们的主要运算是矩阵乘法，"Verma 说。这基本上就是取一个数字 数组，将其与另一个数组相乘，然后将所有这些乘法的结果相加。很早以前，工程师们就注意到了 一个巧合：电气工程的两个基本定律可以精确地完成这样的运算。欧姆定律说，电压乘以电导就能 得到电流。基尔霍夫电流定律说，如果一束电流从 ...

Core Viewpoint - UWB technology, which gained popularity after Apple's iPhone 11 release, has not met expectations in terms of widespread adoption and application despite its advantages in precision and security [1][5][6]. Group 1: UWB Technology Overview - UWB technology, based on IEEE 802.15.4a and 802.15.4z standards, allows for centimeter-level precision in distance and location measurement, making it suitable for applications in smartphones and asset tracking [3][4]. - UWB's advantages include strong anti-interference capabilities and high positioning accuracy, making it a preferred choice for automotive passive entry systems over BLE and NFC [4][6]. Group 2: Challenges in UWB Adoption - The slow development of UWB in recent years is attributed to the complexity of early UWB solutions, which required additional configuration and programming, posing challenges for many automotive manufacturers and smaller companies [4][5]. - Compatibility issues with third-party MCUs and the high costs associated with complex hardware integration have hindered UWB's market penetration [4][6]. Group 3: Recent Developments and Innovations - Chip manufacturers like Qorvo, NXP, and Samsung have introduced UWB SoC solutions to simplify design and accelerate product launch, such as Qorvo's QM35825 and QPF5100Q [6][8]. - The QM35825 features an "All-in-One" design that integrates multiple components, reducing design barriers and enhancing application in both industrial and consumer markets [7][8]. Group 4: Future Applications and Market Potential - UWB technology is being explored for various applications, including access control, asset tracking, and automotive safety systems, particularly in detecting child presence in vehicles [15][16]. - The technology's ability to measure direction and distance positions it favorably against other wireless technologies, with potential growth in smart locks and automotive markets [14][15].