2025年9月19日，新加坡国立大学（NUS）与POET Technologies的研究团队在国际权威期 刊 Nature Communications 上 发 表 了 题 为 《 Ferroelectric-Based Pockels Photonic Memory》的研究论文，第一作者，现香港科技大学（广州）助理教授许泽锋首次成功提出 将 锆 掺 杂 的 氧 化 铪 (HZO) 铁 电 场 效 应 晶 体 管 （ FeFET ） 与 绝 缘 体 上 铌 酸 锂 薄 膜 (Lithium Niobate on Insulator, LNOI)微环谐振器（Micro Ring Resonator, MRR）单片集成，构建 出一种新型非易失、多态、超低能耗的"Pockels光子存储器"。该器件通过铁电畴与线性电光 （Pockels）效应的协同调控，实现了6个可区分光学态/FeFET，且在单一MRR可进行多器件 堆叠，实现16个非易失态/MRR。单状态切换能耗低至65.1 fJ，数据保持时间超10年，耐久 性超过10 7 次循环，为光计算与光存储一体化提供了革命性的解决方案。 01 背景介绍 面对人工智能、物联网 ...

Core Viewpoint - Samsung is challenging TSMC by reducing its 2nm wafer price to $20,000, which is nearly one-third lower than TSMC's price of $30,000, amidst high demand for advanced chips [5][6]. Group 1: Market Dynamics - The global advanced chip production is operating at full capacity, with companies like Nvidia struggling to secure enough supply to meet their needs [5]. - Despite being a seller's market, there is still competition among chip foundries, as evidenced by Samsung's price reduction strategy [5]. Group 2: Samsung's Strategy - Samsung's decision to lower its 2nm wafer price is seen as a necessary move to avoid idle capacity in its new wafer fabrication plant and ensure a return on investment [5]. - The company previously faced significant challenges with its 2nm plans, including a reported 50% cut in wafer fab investments earlier this year [5]. Group 3: Partnerships and Opportunities - Samsung recently secured a $16.5 billion deal with Tesla to produce AI6 chips, which will be manufactured at its Texas facility, providing a boost to its chip manufacturing efforts [5]. - The collaboration with Tesla is expected to help Samsung improve its yield rates, which are targeted to reach 60% to 70% [5]. Group 4: Competitive Landscape - TSMC currently holds the largest market share in the 2nm segment, with 15 major clients including Intel, AMD, MediaTek, and Nvidia [6]. - Samsung's $20,000 wafer price presents an attractive option for customers unable or unwilling to pay TSMC's premium prices [6].

Core Viewpoint - The Trump administration is developing a policy requiring semiconductor manufacturers to match their domestic chip production with the number of chips imported into the U.S. to avoid a 100% tariff on imports [3][4]. Group 1: Policy Details - Semiconductor companies must produce one chip in the U.S. for every chip imported from other countries to avoid tariffs [1][3]. - Failure to maintain a 1:1 ratio over time will result in significant import tariffs, potentially reaching 100% [3][4]. - The policy aims to boost domestic chip production and may reshape global supply chains, but its implementation could face logistical and technical challenges [3][4]. Group 2: Credit System and Compliance - Companies committing to build new semiconductor facilities in the U.S. will receive "credits" based on promised production volumes, allowing them to import chips tariff-free during the construction phase [4]. - The complexity of tracking each chip's origin in a global supply chain poses significant compliance challenges for manufacturers [4]. Group 3: Impact on Industry Players - Major semiconductor manufacturers like Intel, GlobalFoundries, Micron, Samsung, Texas Instruments, and TSMC, which are expanding in the U.S., stand to benefit from this policy [4]. - The policy could provide these companies with a stronger negotiating position with clients seeking to source chips from the U.S. [4].

Core Viewpoint - The article discusses the evolution and significance of Gate-All-Around (GAA) transistors, particularly in the context of semiconductor technology advancements, highlighting the transition from traditional FinFET designs to GAA structures as a means to enhance performance and energy efficiency in microchips [1][2]. Group 1: Historical Context and Development - The early research from Lawrence Berkeley National Laboratory nearly 20 years ago introduced innovative methods for creating advanced transistor structures, specifically the GAA-FET technology, which is crucial for packing billions of transistors into microchips [2][4]. - Peidong Yang, a key figure in this research, emphasized the potential of GAA structures to improve transistor performance and reduce power consumption, marking a significant architectural advancement in semiconductor technology [4][5]. Group 2: Technical Advancements - GAA structures allow for more precise control of current flow compared to traditional FinFET designs, which face efficiency challenges when scaled down below 5 nanometers [5][6]. - The GAA method, which fully wraps the gate around the channel, is seen as a natural progression for advanced solid-state nanoelectronic devices, although traditional top-down lithography techniques have struggled to achieve the necessary geometries [11][12]. Group 3: Performance Metrics - The article highlights that the GAA transistors exhibit superior electrostatic control, with a reduction of short-channel effects by 35% compared to FinFETs, making them more efficient at smaller scales [13][19]. - The performance parameters of the developed Si VINFET devices, such as transconductance and mobility, are comparable to those of standard planar MOSFETs, indicating their competitive potential in the market [25][19]. Group 4: Future Prospects - The integration of vertically grown silicon nanowires in GAA structures presents a promising avenue for achieving high transistor density and performance, with the potential to compete with existing advanced solid-state devices as manufacturing techniques improve [25][24]. - The article concludes that with further optimization in processes and device structures, these GAA transistors could effectively operate at scales below 10 nanometers, continuing the trend of miniaturization in semiconductor technology [25].

Core Viewpoint - AMD is seeking a new DDR5 memory standard patent that aims to double the bandwidth to 12.8 Gbps, but its immediate adoption in PCs is uncertain [2][4][5]. Summary by Sections AMD's Patent Application - AMD's patent application for a high-bandwidth dual in-line memory module (HB-DIMM) has been revealed, designed to enhance memory bandwidth through pseudo channels, buffer chips, and intelligent signal routing [4]. - The document highlights the increasing memory bandwidth demands of modern computing platforms, particularly for high-performance graphics processors and servers [4]. Technical Details - The HB-DIMM design consists of memory chips and buffer chips, with data being transmitted at twice the rate of the memory chips via the host bus [4]. - The architecture includes a memory controller circuit (RCD) that routes command/address signals to multiple memory chips, effectively creating at least two independently addressable pseudo channels [4]. Potential Impact and Adoption - The proposed HB-DIMM could potentially double the native speed of DDR5 from 6.4 Gbps to 12.8 Gbps without requiring new generation memory chips [5]. - However, the adoption of this new standard may face challenges, as most DRAM chips currently sold comply with JEDEC's DDR standards, and the likelihood of widespread adoption hinges on support from major industry players like Intel [5].

Core Viewpoint - Automotive chips are essential for the development of electric and intelligent vehicles, facing challenges such as high reliability requirements, large-scale circuit verification, and stringent functional safety standards [2][14]. Group 1: Quality, Safety, and Reliability Challenges - Automotive chips must meet high-quality testing and zero-defect (0 DPPM) requirements, eliminating defects introduced during manufacturing [4]. - The verification cycle for automotive-grade chips is longer than for consumer-grade chips, requiring rigorous testing certifications like AEC-Q100, which increases design cycle and cost challenges [4]. - The complexity of fault types and testing scales has increased with the development of large-scale integrated circuits, leading to higher testing difficulty, time, and costs [4]. Group 2: Testing Solutions - Siemens EDA's Tessent™ solution helps automotive chip designers ensure high quality, enhance safety, and improve reliability, accelerating time-to-market [4]. - Tessent DFT technology provides high-quality testing to ensure zero defects, generating defect-oriented fault models for comprehensive testing coverage [5]. - Tessent™ LogicBIST and MemoryBIST solutions enable in-chip self-testing capabilities and non-destructive memory testing during system operation, respectively [8]. Group 3: Verification Challenges - Accurate functional verification before chip tape-out is crucial, with increasing complexity in automotive chips making this process more challenging [10]. - The new Veloce™ CS hardware-assisted verification system from Siemens EDA significantly enhances hardware acceleration performance, supporting over 40 billion gates [11]. - Veloce proFPGA CS allows for rapid execution of silicon verification, facilitating firmware and application development [12]. Group 4: Functional Safety Requirements - The performance and safety of chips directly impact driving safety, necessitating compliance with functional safety standards like ISO 26262 [14]. - There is a growing demand for higher safety levels in automotive chips, particularly for ASIL-D level designs related to advanced driver-assistance systems (ADAS) [15]. - Siemens EDA's Austemper platform enhances efficiency in safety analysis and verification, supporting clients in meeting ASIL-B and ASIL-D requirements [15][17]. Group 5: Industry Impact - Automotive chips play an indispensable role in the intelligent and electric transformation of modern vehicles, with Siemens EDA providing advanced solutions to ensure high quality and reliability [17].

Core Insights - Nvidia is collaborating with MediaTek to develop the N1x chip, which is expected to be introduced by the end of January next year, potentially coinciding with Nvidia's GTC conference [1][3]. - The N1x chip is built on TSMC's 3nm process and is anticipated to enhance MediaTek's operational growth in the coming year [4]. Group 1: Market Developments - Nvidia's entry into the AI PC market is marked by the N1x SoC's progress, with expectations for a product launch in early 2024 [3][4]. - The N1 series chips are designed to target consumer applications, focusing on edge AI and inference demands while maintaining low power consumption [4][5]. Group 2: Competitive Landscape - Qualcomm, as a pioneer in the AI PC sector, aims for a market target of $4 billion by 2029 and welcomes more competitors to increase market penetration [4]. - Qualcomm has deployed 16,000 laptops powered by its processors internally and is actively collaborating with enterprise clients, indicating a shift in the enterprise market dynamics due to the introduction of Arm PCs [5]. Group 3: Technological Advancements - Qualcomm plans to continue using advanced process nodes for its future generations of products, maintaining its leadership in mobile processors [5]. - The competition between Qualcomm and MediaTek is intensifying, with both companies vying for influence in the AI ASIC market and cloud services [5].

Core Viewpoint - Mercedes-Benz has spun off a group of chip experts into a new company, Athos Silicon, focused on developing next-generation computing brains for autonomous vehicles, drones, and other vehicles [1][3]. Group 1: Company Overview - Athos Silicon is headquartered in Santa Clara, California, and its engineering team previously worked at Mercedes-Benz's North American R&D center for five years [1]. - The company will receive intellectual property developed by the group and significant investment from Mercedes-Benz, although the transaction value has not been disclosed [3]. Group 2: Technology and Innovation - Reliability is crucial for automotive chips, leading to the use of multiple independent chips for critical autonomous driving functions to ensure backup in case of failure [3]. - Athos has developed a method using "chiplets" to achieve the same reliability, allowing multiple small chips to be packaged together, which can reduce power consumption by 10 to 20 times compared to independent chips [3]. - This energy efficiency is vital for electric vehicles, as the computing core must compete for limited battery power [3]. Group 3: Strategic Positioning - Athos Silicon plans to raise venture capital from other investors and aims to maintain a neutral stance to engage with other automakers, including competitors of Mercedes-Benz [4]. - Mercedes-Benz will hold a minority stake in Athos Silicon, which will have an independent board [3].

来源 ： 内容 编译自MIT 。 晶体管是现代电子产品的基石，通常由硅制成。由于硅是一种半导体，这种材料可以控制电路中的电 流。但硅的基本物理限制限制了晶体管的紧凑性和能效。 麻省理工学院的研究人员现已用磁性半导体取代硅，创造出一种磁性晶体管，可以实现更小、更快、 更节能的电路。这种材料的磁性强烈影响着其电子行为，从而更有效地控制电流。 该团队采用了一种新型磁性材料和优化工艺，减少了材料的缺陷，从而提高了晶体管的性能。 该材料独特的磁性还允许晶体管内置内存，这将简化电路设计并开启高性能电子产品的新应用。 "人们对磁铁的认识已有数千年，但将磁性融入电子产品的方法却非常有限。我们展示了一种有效利 用磁性的新方法，为未来的应用和研究开辟了许多可能性。"麻省理工学院电气工程与计算机科学系 （EECS）和物理系研究生、此项进展论文的共同第一作者周忠涛（Chung-Tao Chou）说道。 公众号记得加星标⭐️，第一时间看推送不会错过。 但硅半导体的基本物理限制使得晶体管无法在低于一定电压的情况下工作，从而影响了其能源效率。 为了制造更高效的电子产品，研究人员花费了数十年时间研发利用电子自旋控制电流的磁性晶体管。 电子自 ...

Core Viewpoint - The strategic alliance between NVIDIA and Intel aims to integrate AI-accelerated computing with the advantages of the x86 ecosystem, focusing on the NVLink technology architecture, which poses a significant challenge to the long-dominant PCIe standard [2][3] Group 1: NVLink vs PCIe - NVLink offers several times the bandwidth and lower latency compared to PCIe, making it superior for AI training and large-scale computing, thus threatening the PCIe technology route [2][3] - Intel's embrace of NVLink is symbolically significant, indicating a potential restructuring of CPU and GPU interconnect paradigms, which may impact the Retimer chip market that relies on PCIe [2][3] Group 2: Retimer Chips - Retimer chips are essential for addressing signal integrity issues in PCIe connections, especially as data transfer rates increase with newer PCIe versions [5][6] - The demand for Retimer chips is expected to rise significantly due to the expansion of cloud computing and AI servers, where multiple GPUs are used, necessitating 8 to 16 Retimer chips per AI server [10][11] Group 3: Market Dynamics - The Retimer chip market is characterized by a "duopoly" led by AsteraLabs and Lanqi Technology, with competition from traditional analog giants and other players [12][13] - The global PCIe Retimer chip market is projected to reach $1.8 billion by 2025, driven by the increasing need for high-speed interconnects in AI and server applications [15] Group 4: Impact of NVIDIA and Intel Alliance - The collaboration between NVIDIA and Intel may disrupt the Retimer chip market, as NVLink's superior bandwidth and lower latency could reduce the need for signal compensation chips [17][19] - If Intel's CPUs begin to support NVLink, it could accelerate the adoption of NVLink as a standard, further diminishing the role of Retimer chips in the ecosystem [19][20] Group 5: Future Outlook - Despite the potential challenges posed by NVLink, Retimer chips may still hold value in scenarios where long-distance transmission and complex topologies are involved, ensuring data integrity in non-GPU device interconnections [23]