Core Viewpoint - Anmo Technology (China) Co., Ltd. has launched the next-generation SPU IP "Shan Hai" S30FP/S30P, providing a comprehensive security solution for high-performance computing chips, enhancing physical attack resistance and system reliability, and supporting high-level security certifications such as CC EAL4+ and national secret level two [1][9]. Group 1: Product Features - The "Shan Hai" S30FP/S30P features a complete HSM subsystem that effectively resists physical attacks, supporting high-level security certifications like CC EAL4+ and national secret level two [4][9]. - The product achieves the highest functional safety certification level ASIL D, with flexible configuration options to meet different safety requirements, suitable for various industries such as smart automotive and smart healthcare [9][10]. - It supports a wide range of information security algorithms and provides rich isolation methods, ensuring robust security across different applications [4][5][10]. Group 2: Application Scenarios - The "Shan Hai" S30P is designed for high-security scenarios such as artificial intelligence, data centers, and robotics, offering multiple security algorithms and strong physical attack resistance [12]. - In functional safety-critical areas like intelligent driving and smart transportation, the S30FP provides high reliability with ASIL D-level safety assurance while maintaining high information security [12]. - The launch of the "Shan Hai" S30FP/S30P enhances Anmo Technology's SPU IP product family, aligning with the "AI+" action plan to support diverse AI computing needs from edge AI to smart automotive [12].

Core Viewpoint - The article discusses the current state and future potential of Co-Packaged Optics (CPO) technology in the AI infrastructure landscape, emphasizing that while CPO is seen as a next-generation technology, its widespread adoption is not imminent due to existing technological limitations and market dynamics [1][24]. Group 1: Current Industry Sentiment on CPO - Broadcom's CEO Hock Tan stated that silicon photonics will not play a significant role in data centers in the short term, indicating that CPO is not a leapfrog technology but rather a last resort when existing technologies reach their limits [1][24]. - Major industry players, including Arista, Credo, Marvell, and Lumentum, echoed similar sentiments at the Barclays Global Technology Conference, suggesting a cautious approach towards CPO adoption [1][24]. Group 2: Shift in Industry Focus - The AI industry has shifted its focus from merely increasing computing power to addressing interconnectivity and system-level architecture, as the bottleneck has moved from computational capacity to interconnect capabilities [3][4]. - Companies are now prioritizing terms like Scale-Out, Scale-Up, and Scale-Across, indicating a deeper understanding of the infrastructure bottlenecks in AI [4]. Group 3: Horizontal and Vertical Scaling - Horizontal scaling (Scale-Out) is currently dominated by pluggable optics, with CPO technology not yet widely adopted due to the existing 800G and 1.6T technologies still being the main focus [7][8]. - Vertical scaling (Scale-Up) was initially seen as a promising application for CPO, but its timeline has been pushed back, with large-scale deployment expected around 2027-2028 [9][10]. Group 4: Challenges Facing CPO - CPO faces significant challenges, including higher costs, reliability issues, and power consumption concerns, which have delayed its mass production [18][24]. - The complexity of system design and the need for a mature supply chain are also major obstacles to the widespread adoption of CPO technology [19][24]. Group 5: Alternative Solutions - Transition solutions like LPO, AEC, and ALC are increasingly being recognized as viable alternatives to CPO, with many companies focusing on these technologies to meet current demands [15][25]. - LPO technology has already seen large-scale deployment, providing cost and power advantages, while AEC and ALC are being developed to offer reliability similar to copper cables with the bandwidth of optical solutions [15][25]. Group 6: Future Outlook - Industry predictions suggest that CPO will begin to see deployment in specific high-density systems around 2028, but the current focus remains on optimizing existing technologies [26][27]. - The industry consensus is that CPO will not be the immediate solution until existing technologies reach their limits in terms of power, density, and reliability [27].

公众号记得加星标⭐️，第一时间看推送不会错过。 据 CNBC 报 道 ， 英 伟 达 已 同 意 以 200 亿 美 元 的 全 现 金 交 易 收 购 高 性 能 人 工 智 能 加 速 芯 片 设 计 商 Groq。该报道援引 Disruptive 首席执行官兼这家初创公司的长期支持者 Alex Davis 的话说，这笔 交易很快就完成了，就在 Groq 以约 69 亿美元的估值筹集了 7.5 亿美元之后几个月。 自 2016 年成立以来，Disruptive 已向该公司投资超过 5 亿美元。最近一轮融资吸引了包括贝莱德、 纽伯格伯曼、三星、思科、Altimeter 和 1789 Capital 在内的投资者。 戴维斯表示，Groq预计将于周三晚些时候向投资者通报这笔交易。虽然此次收购包括Groq的资产， 但其早期云业务并不包含在交易范围内。 这家初创公司由谷歌张量处理单元（TPU）背后的前工程师创立，TPU 是一款旨在与英伟达在人工 智能工作负载领域竞争的芯片。 如果交易完成，这将是英伟达迄今为止规模最大的收购，凸显了该公司致力于加强其在先进人工智能 硬件领域地位的决心。 对此，英伟达否认有关交易，澄清 ...

Group 1 - TEL announced organizational changes and personnel adjustments effective February 1, 2026, including the appointment of a new chairman and president for its Taiwan subsidiary [1] - The changes are interpreted as a response to the involvement of TEL's Taiwan subsidiary in the TSMC 2nm leak case, with TEL's president expressing regret and seeking to restore relationships with TSMC [1][2] - The restructuring aims to enhance TEL Taiwan's operational framework, improve customer service quality, and boost employee motivation and corporate cohesion [1] Group 2 - TEL's headquarters announced the establishment of a next-generation equipment project organization starting January 1, 2026, to align with TSMC's 1nm process development [2] - The organizational changes involve twelve senior executives, many of whom have previously held general manager positions, taking on leadership roles in different projects [2] - The adjustments are seen as beneficial for TEL to secure a place on TSMC's important procurement list for future 1nm technology [2]

Core Insights - David Patterson delivered a highly praised keynote speech at the RISC-V summit, reflecting on the birth of Reduced Instruction Set Computing (RISC) at the University of California, Berkeley in 1981 [1][3] - The computing landscape in 1981 was dominated by mainframes and minicomputers, with IBM as the industry leader, and the VAX minicomputer representing the peak of technology at that time [1][2] - The prevailing belief was that Complex Instruction Set Computing (CISC) could bridge the "semantic gap" between high-level languages and hardware, but this was later proven to be inefficient [2][3] Summary by Sections Historical Context - In 1981, the computing environment was characterized by large machines, with the VAX being a 32-bit system running at 5 MHz and equipped with 2 KB cache [1] - The era also saw significant cultural events, including Ronald Reagan's presidency and the rise of disco music [1] RISC Principles - The RISC principles emerged from the realization that simpler instruction sets could lead to better performance, prioritizing fast clock cycles and easy decoding over the complexity of instruction sets [2][3] - Patterson compared CISC to an overly decorated 1950s Cadillac and RISC to a sleek, agile sports car, emphasizing the efficiency of simplicity [2] RISC-I Development - Patterson and student David Ditzel published a paper in 1980 that sparked widespread attention and debate regarding RISC versus CISC [3] - The RISC-I design was completed in under two years by a small group of students, demonstrating performance that was approximately twice as fast as the VAX, validating the RISC concept [3] Legacy and Impact - After 45 years, the simplicity and elegance of RISC have powered billions of devices globally and continue to thrive within the open RISC-V ecosystem [4]

Core Viewpoint - Nvidia has paused testing of advanced chips using Intel's 18A manufacturing process, leading to a decline in Intel's stock price, despite Intel claiming progress in the 18A technology [1] Group 1: Nvidia and Intel Relationship - Nvidia recently tested the 18A process but has halted further progress, impacting Intel's stock negatively by approximately 2.2% [1] - Nvidia agreed to invest $5 billion in Intel, seen as a boost for Intel, which has struggled to keep pace with competitors [1] Group 2: Intel's 18A Technology - The 18A technology aims to enhance chip efficiency and reduce power consumption through innovations like "full-ring gate" technology, allowing for better control of transistors [2] - Intel's new Fab 52 factory in Arizona is the first to mass-produce chips using the 18A process, marking a significant step in the company's efforts to localize advanced chip production [1][2] Group 3: Intel's 14A Process - Intel is focusing on the 14A process as a potential turning point for its foundry services, with plans to control initial capacity based on market demand, contrasting with the aggressive capacity increase seen in the 18A strategy [2][3] - The 14A process is being developed in collaboration with external customers, allowing for early feedback and adjustments, which is expected to lead to a clearer success trajectory by mid-2026 to early 2027 [3]

Core Viewpoint - The article discusses the significant price increase of DDR4 DRAM due to supply chain adjustments by major manufacturers, particularly Samsung Electronics, which is delaying the phase-out of DDR4 production to maximize profits and meet rising demand, especially in server applications [1][3]. Group 1: Market Dynamics - DDR4 16Gb spot prices have surged to $60, driven by supply constraints and increased demand from specific customers [1]. - Samsung is expected to slow down the planned discontinuation of DDR4 production, with a focus on securing long-term supply contracts under Non-Cancellable, Non-Returnable (NCNR) terms [1][2]. - The shift in Samsung's strategy indicates a prioritization of profit maximization in its memory business, as it aims to reclaim its position as an industry leader [1][3]. Group 2: Contractual Implications - NCNR contracts are being discussed with customers, allowing them to lock in prices and quantities, thus protecting against future market fluctuations [2]. - While customers face potential penalties for breach of contract, the stability offered by NCNR agreements is appealing amid rising prices [2][3]. Group 3: Production Adjustments - Samsung plans to transition production capacity from DDR4 to DDR5 and HBM-related products, but the current demand for DDR4 has led to a temporary retention of its production [3]. - The company is expected to maintain DDR4 production at least until the end of 2026 for specific applications, such as automotive and in-house brands [3][4]. - Other memory manufacturers are also struggling to meet DDR4 demand, leading to continued price increases and supply shortages [4]. Group 4: Industry Collaborations - Micron is actively seeking to expand its DRAM production capacity through partnerships and facility rentals, indicating a high level of collaboration within the industry to address capacity constraints [5].

Core Viewpoint - Apple's M series processors have significantly disrupted the computing industry, showcasing the potential of ARM architecture and leading to a re-evaluation of performance and efficiency standards in personal computing [1]. Group 1: Transition from Intel to M Series - Apple transitioned from Intel processors to its own M series chips starting in 2020, a decision influenced by years of collaboration with Intel and the need for greater control over performance and efficiency [2]. - The experience gained from developing chips for iPhone and iPad provided Apple with the confidence and knowledge necessary to create its own Mac processors [2]. Group 2: Development and Design Insights - The design of the M series chips was heavily influenced by Apple's experience with the iPad Pro, focusing on creating a powerful yet energy-efficient processor [4]. - The integration of Mac experts into the chip development process was crucial, allowing for a better understanding of user needs and system requirements [4]. Group 3: Performance and Efficiency - The M1 chip's performance exceeded expectations, particularly in battery life and energy efficiency, allowing for significant performance gains at lower power consumption levels [5][6]. - The unified architecture of the M series, which integrates CPU, GPU, and memory, has enabled developers to operate without the limitations of traditional hardware setups [7][9]. Group 4: Impact on the Industry - The shift to M series chips has transformed Apple's control over its hardware and software, allowing for a more cohesive and optimized user experience [14][15]. - Competitors like AMD and Intel have been forced to rethink their efficiency strategies in response to Apple's focus on performance per watt [15][24]. Group 5: User Experience and Workflow Changes - Users have reported significant improvements in their workflows, with M series Macs providing the necessary performance for demanding tasks without the need for separate desktop machines [18][19]. - The addition of dedicated video encoding and decoding cores in the M series has enhanced video editing capabilities, making it easier for users to handle complex tasks [19]. Group 6: Future Prospects - Apple is expected to continue innovating with its M series chips, with potential advancements in AI integration and new designs for Mac products [23][25]. - The ongoing development of the M series suggests that Apple will maintain its competitive edge in the computing market, with future iterations expected to deliver even greater performance improvements [21][22].

公众号记得加星标⭐️，第一时间看推送不会错过。 12 月 12 日，AMD 更新了其技术文档，并发布了" AMD Family 1Ah Model 50h-57h 处理器的性能 监视器计数器"， InstLatX64首先注意到了这一点。 首先，确定性能监视器计数器的位置。 每个线程有 6 个性能事件计数器，每个 L3 复合体有 6 个性能事件计数器，每个数据结构有 16 个性 能事件计数器。 顺便一提，AMD μProf 性能分析器是" AMD μProf 开发工具" 的组件之一，并且可以免费使用。撰 写本文时，最新版本为 5.2 版，于 12 月 11 日发布，而上述文档于次日发布，这意味着 Zen 6 架构 的支持预计将在下一个 μProf 版本（5.3 版？）中实现。 性 能 监 视 器 计 数 器 并 非 Zen 6 的 新 功 能 ， 它 已 经 推 出 一 段 时 间 了 。 EPYC 9005 系 列 （ 或 Zen 5 EPYC）的相关说明请参见本文档。 到目前为止一切正常，但有一家网站开始声称，关于 Zen 6 兼容性能监视器计数器的文档，Zen 6 并 非 Zen 5 的扩展，而是一种面向 ...

Core Viewpoint - The semiconductor industry is struggling to meet the immense demand for computing power driven by artificial intelligence (AI), particularly in data centers that consume significant electricity. The traditional computing architectures, such as the von Neumann architecture, are inadequate for the parallel processing needs of AI systems, necessitating a new approach to chip design [1][4][19]. Group 1: Challenges in Current Architectures - The traditional von Neumann architecture is inefficient for neural networks due to its sequential instruction processing, which does not align with the matrix-based structure of AI models [2][4]. - Large language models (LLMs) require extensive computations, with inference potentially needing between 100 billion to 10 trillion operations, highlighting the limitations of memory access times in von Neumann architectures [4][5]. - The inherent memory access issues in traditional CPUs and GPUs hinder their performance and power efficiency, as they cannot place sufficient memory close enough to the arithmetic logic units (ALUs) [5][6]. Group 2: Innovative Solutions - The exploration of alternative architectures, such as pulse arrays, aims to better align computing structures with neural network topologies, but previous attempts have faced challenges in practical implementation [6][8]. - Ambient Scientific's DigAn technology enables the creation of configurable matrix computers, which optimize the processing of AI workloads by integrating memory and computation more effectively [9][11]. - The new architecture features a novel computing unit called the analog MAC, which addresses the memory and computation separation issue inherent in von Neumann designs, allowing for significant improvements in efficiency [11][13]. Group 3: Performance and Power Efficiency - The DigAn architecture dramatically reduces the number of cycles needed for neural network operations, achieving a performance increase of over 100 times compared to typical microcontroller units (MCUs) while consuming less than 1% of the power of conventional GPUs [13][19]. - The GPX series chips, utilizing this innovative architecture, are designed for high performance and low power consumption, making them suitable for embedded systems and edge AI applications [14][16]. - The GPX10 Pro model features clusters of MX8 cores, providing a complete system-on-chip (SoC) solution that supports mainstream machine learning frameworks, facilitating easier model training and deployment [18][19].