公众号记得加星标⭐️，第一时间看推送不会错过。 随着人工智能（AI）半导体需求强度远超市场预期，全球封测龙头日月光投控正迎接前所未有的成长 契机。大摩(摩根士丹利，Morgan Stanley）在最新的研究报告中，将日月光投控的投资评等重申为 「买进」，并将目标价从新台币228 元大幅上调至308 元。此一调整，反映了分析师对其2026 年至 2027 年获利成长的强劲信心，特别是看好其在先进封装领域的领先地位及定价权的提升。 报告指出，由于AI 半导体需求极为强劲，加上日月光的产能已趋近极限，预计该公司将在2026 年调 涨后段晶圆代工服务价格，涨幅预期落在5% 至20% 之间，高于原先预期的5-10%。这波涨价主要导 因于半导体通膨压力，日月光已决定将包含基板、贵金属及电费在内的增加成本转嫁给客户。同时， 公司将优先向毛利率较高的AI 客户供货，以优化产品组合。 报告表示，大中华区外包封测（OSAT）的产能利用率（UTR）在2025 年已持续复苏，预计2026 年 将进一步成长。日月光2025 年第三季的产能利用率已达90%，在实务上什至已接近满载，这使其在 2026 年的价格谈判中拥有极强的议价筹码。 ...

Core Insights - Nvidia's CEO Jensen Huang announced the launch of the Rubin platform, claiming it to be the strongest computing chip ever, which is expected to drive significant business growth for Nvidia and its partner TSMC in 2026 [1][2] Group 1: Nvidia's Rubin Platform - The Rubin platform integrates six types of computing chips, including the Rubin GPU, Vera CPU, and advanced networking platforms like Spectrum 6 and BlueField-4 DPU, marking a significant innovation in chip technology [1] - Nvidia has received substantial orders for the Rubin platform, alongside continued demand for the existing GB300, indicating a strong market response [1] - The platform utilizes TSMC's 3nm process technology combined with CoWoS-L advanced packaging, enhancing its performance capabilities [2] Group 2: Impact on TSMC and Related Companies - TSMC is expected to experience significant growth in 2026 due to the strong order flow from Nvidia's Rubin platform, with ongoing collaboration between the two companies [1][2] - The introduction of NVL72 computing technology indicates a substantial increase in procurement units for cloud service providers, which will positively impact Nvidia and TSMC's operational performance [2] - Related companies such as ASE Technology Holding, King Yuan Electronics, and probe card suppliers like Wanshih and Yungwei are also anticipated to benefit from the growth driven by the Rubin platform [2]

Group 1: TSMC's 2nm Technology - TSMC is set to begin mass production of its 2nm technology in Q4 2025, marking a significant advancement in transistor architecture with the introduction of GAA (Gate-All-Around) transistors, which is the most substantial change since the FinFET technology was introduced in 2011 [1][2] - The 2nm process will enhance wafer production density by 30% to 50%, leading to a prolonged capital expenditure cycle, with SEMI predicting it will reach $156 billion by 2027 [1] - TSMC's N2 technology will provide performance and power efficiency improvements across all process nodes, addressing the growing demand for energy-efficient computing [1][2] Group 2: Performance Metrics - Compared to the 3nm N3E process, TSMC's 2nm technology will increase speed by 10% to 15% at the same power level, while reducing power consumption by 25% to 30% and increasing chip density by over 15% [2] - TSMC plans to launch the N2P process as an extension of the 2nm family, targeting mass production in H2 2026 for applications in smartphones and high-performance computing [2] Group 3: Advanced Packaging Challenges - The real bottleneck in the semiconductor industry is shifting from transistor density to advanced packaging technologies, particularly CoWoS (Chip-on-Wafer-on-Substrate) [3][17] - TSMC's CEO confirmed that supply remains tight and is expected to continue until 2025, with advanced packaging prices increasing by 10-20% annually, while logic wafer prices only rise by 5% [23] Group 4: CoWoS Capacity and Market Dynamics - TSMC is accelerating the expansion of its CoWoS capacity to meet the surging demand for AI chips, with projections for capacity to reach 125K wafers per month by the end of 2026 and further increase to 170K wafers per month by the end of 2027 [24] - NVIDIA is expected to secure over 70% of the CoWoS-L allocation, creating a structural advantage, while other major players like Broadcom and AMD are also vying for the remaining capacity [23][36] Group 5: Future Roadmap and Innovations - TSMC's roadmap includes the introduction of new technologies such as CoPoS (Chip-on-Package-on-Substrate) expected to be implemented post-2027, aimed at improving packaging area utilization and production efficiency [24] - The transition from FinFET to GAA technology signifies a generational shift in semiconductor manufacturing complexity, with a structural demand increase of 30-50% per wafer startup [36]

Core Viewpoint - TSMC's transition to 2nm GAA technology marks a significant advancement in semiconductor manufacturing, with expectations of increased production capacity and efficiency, while the real bottleneck lies in advanced packaging technologies like CoWoS, rather than transistor density [1][40]. Group 1: 2nm Technology and Production - TSMC's 2nm technology is set to begin mass production in Q4 2025, utilizing nanosheet transistors that enhance performance and power efficiency across all process nodes [1]. - Compared to the 3nm N3E process, the 2nm technology offers a 10% to 15% speed increase at the same power level, and a 25% to 30% reduction in power consumption while increasing chip density by over 15% [2]. - TSMC plans to establish five 2nm fabs in Kaohsiung, with a total investment exceeding NT$1.5 trillion, creating 7,000 high-tech jobs [2]. Group 2: Advanced Packaging Challenges - The CoWoS (Chip-on-Wafer-on-Substrate) technology is critical for integrating advanced chips with HBM memory; without it, even the most advanced chips could become excess inventory [3][40]. - Advanced packaging capabilities are becoming the key limiting factor in the AI semiconductor sector, overshadowing the importance of transistor density [40]. - TSMC's CEO confirmed that supply constraints are expected to persist until 2025, despite plans to double production capacity in 2024 and 2025 [21]. Group 3: Market Dynamics and Competitors - NVIDIA is projected to secure over 70% of the CoWoS-L capacity, creating a structural advantage, while companies like Broadcom are also vying for a share of the remaining capacity [23][40]. - The AI chip market is evolving, with companies like Broadcom capturing approximately 70% of the custom AI accelerator market, and their AI revenue expected to reach $12.2 billion in FY2024, a 220% year-over-year increase [32]. - The competition in the AI chip market is intensifying, with major players like AMD and Intel also making significant strides in developing their own AI hardware solutions [35][37]. Group 4: Future Developments and Innovations - TSMC is diversifying its advanced packaging technologies, including the development of CoPoS (Chip-on-Package-on-Substrate) technology, expected to be introduced after 2027 [24]. - The transition from FinFET to GAA technology introduces new manufacturing complexities, requiring specialized equipment and processes, which could extend production timelines [11][40]. - The demand for advanced packaging is expected to grow significantly, with OSAT (Outsourced Semiconductor Assembly and Test) companies also ramping up their capabilities to meet the increasing needs of AI chip production [43].

公众号记得加星标⭐️，第一时间看推送不会错过。 半导体设备业者透露，按照台积电与"非台积阵营"包括日月光集团、Amkor与联电等计画，双双加速 扩充先进封装CoWoS产能，从订单分布观察，2026~2027年GPU、特用芯片（ASIC）客户需求皆超 乎预期。 这带动台积电近期再度上调2026年CoWoS月产能，非台积阵营原预期2026年月产能约2.6万片，现已 调升逾5成。其中，NVIDIA持续预订台积CoWoS过半产能，博通（Broadcom）与超微（AMD）分 占二、三名，而联发科2026年也正式进入ASIC赛局。 近期Google TPU声名大噪，市场不断涌现ASIC阵营侵蚀版图看法，然半导体相关业者多认为，拥有 CUDA护城河的NVIDIA仍是大型模型训练的主导者。 ASIC以客制化、低功耗与推论效率见长，两 者发展为"共生共荣非互斥。"NVIDIA执行长黄仁勋也强调："GPU与ASIC的定位完全不同。" 设备业者证实，受惠GPU、ASIC需求同步爆发，台积电与非台积阵营双双上调2026年CoWoS产能规 模。 台积2026年月产能至年底约可达12.7万片，而非台积阵营原预期2026年底月产能约2.6 ...

Core Viewpoint - TSMC is facing a significant capacity bottleneck in its CoWoS advanced packaging, unable to meet the explosive demand for AI chips from clients like Nvidia and Apple, leading to a strategic shift towards outsourcing overflow orders to partners like ASE and SPIL [1][3]. Group 1: Capacity Challenges - TSMC's CoWoS production lines are fully booked, severely limiting the delivery speed of AI chips [3]. - The company has decided to implement an outsourcing strategy to alleviate the pressure of unfulfilled orders by distributing some of the overflow to capable partners [3]. Group 2: Outsourcing Strategy - The primary partners for outsourcing are ASE and SPIL, which will handle the overflow orders that TSMC cannot process in a timely manner [3]. - ASE and other firms have announced investments of several billion dollars to expand their production capacity to meet this demand [3]. Group 3: Competitive Landscape - TSMC's decision to outsource is also driven by competitive pressures, particularly from Intel, which is actively trying to attract clients like Apple and Qualcomm in the advanced packaging sector [3]. - By expanding available capacity through outsourcing, TSMC aims to prevent clients from turning to competitors due to long wait times, thereby solidifying its dominance in the high-end packaging market [3].

Core Viewpoint - Google's TPU has gained significant attention in the AI sector, but supply chain limitations may hinder its ability to meet market expectations for production capacity [3][4]. Group 1: Google's TPU and Supply Chain Challenges - The interest in Application-Specific Integrated Circuits (ASICs) is rising, with companies like Meta and Anthropic showing interest in integrating Google's TPU into their workloads [3]. - Google's TPU production may fall short of market expectations due to difficulties in obtaining advanced packaging materials from suppliers like TSMC, which are crucial for successful mass production [3][4]. - TSMC's existing supply chain is heavily focused on clients like Apple and Nvidia, making it challenging for Google to secure priority for its orders [4]. Group 2: TSMC's Advanced Packaging Demand - TSMC is experiencing a surge in orders for its CoWoS advanced packaging technology, driven by demand from major clients such as Nvidia, Google, and Amazon [6][9]. - TSMC plans to expand its CoWoS capacity significantly, with expectations to reach a monthly capacity of 100,000 wafers by the end of 2026, primarily due to the influx of AI and HPC orders [6][9]. - The demand for advanced packaging is expected to remain high, with TSMC's CoWoS capacity projected to increase by 20%-30% by 2026 [9][10]. Group 3: Market Dynamics and Competitors - Despite rumors of major companies considering Intel's advanced packaging as an alternative, TSMC's deep partnerships with clients are likely to limit the flow of orders to Intel [7]. - Nvidia's demand for CoWoS capacity is substantial, with projections for its needs increasing from 590,000 to 700,000 units by 2026, reflecting the strong growth potential in the AI semiconductor market [10]. - Other companies, such as MediaTek and AMD, are also expected to benefit from the growing demand for AI-related products, with their orders for CoWoS technology increasing as well [11]. Group 4: Winners in the Semiconductor Supply Chain - Companies like ASE Technology and Siliconware Precision Industries are positioned to benefit from TSMC's overflow orders, as they ramp up production capabilities to meet demand [13]. - ASE Technology anticipates strong performance in its advanced packaging and testing business, projecting revenues of $1.6 billion for the year and an increase of over $1 billion by 2026 [14]. - The ongoing demand for advanced packaging driven by AI applications is prompting significant investments from these companies to enhance their production capabilities [14].

Core Viewpoint - TSMC's advanced packaging capacity is fully booked, leading to significant outsourcing opportunities, benefiting companies like ASE Technology Holding and Siliconware Precision Industries [1][2] Group 1: TSMC's Outsourcing and Market Impact - TSMC is experiencing strong demand for its advanced packaging services, particularly in CoWoS and CoWoP technologies, which are critical for high-performance computing [1] - The company has fully booked its advanced process capacities, including 2nm and 3nm technologies, prompting it to accelerate outsourcing of advanced packaging and testing to meet AI customer demands [1] Group 2: ASE Technology Holding and Siliconware Precision Industries - ASE Technology Holding and Siliconware Precision Industries have invested over NT$11.17 billion in the past two months to expand production and acquire equipment in response to TSMC's outsourcing orders [1][2] - ASE Technology Holding anticipates strong performance in its advanced packaging and testing business, projecting annual revenue of $1.6 billion for this year, with expectations to increase by over $1 billion by 2026, reflecting a growth rate of over 60% [2] Group 3: Industry Trends and Future Outlook - The demand for high-performance computing driven by generative AI is expected to remain strong, with major companies like NVIDIA, AMD, Microsoft, Meta, Amazon AWS, and Google competing for capacity [1] - ASE Technology Holding's new facilities, including the Dulin and Douliu plants, are expected to be operational by next year, further solidifying its position in the semiconductor packaging market [2]

Core Viewpoint - TSMC is experiencing a surge in orders for advanced packaging, particularly from major clients like Nvidia, Google, Amazon, and MediaTek, leading to full capacity utilization of its CoWoS series [1][2] Group 1: Advanced Packaging Demand - TSMC's CoWoS advanced packaging orders are reportedly overflowing, with both CoWoS-L and CoWoS-S processes fully loaded [1] - The demand for advanced packaging is expected to remain high, with TSMC aiming to expand CoWoS-L capacity to 100,000 wafers per month by the end of 2026, driven by orders from Nvidia's GPUs and custom ASICs [1][2] Group 2: Capacity Expansion and Partnerships - TSMC is actively expanding its CoWoS capacity and collaborating with partners to meet customer demands, with plans to achieve supply-demand balance by 2025-2026 [2] - The company is outsourcing some of its advanced packaging processes to partners to ensure seamless integration of technologies and timely fulfillment of customer needs [1] Group 3: Competitive Landscape - Despite rumors of major clients like Apple and Qualcomm considering Intel's advanced packaging as a backup option, industry insights suggest that TSMC's deep partnerships and comprehensive service offerings will limit the flow of orders to Intel [2]

Group 1 - The core viewpoint of the article highlights the increasing demand for advanced packaging and testing in the semiconductor industry, driven by memory and AI applications [1][2] - The company, ASE Technology Holding Co., announced two significant real estate transactions to enhance its production capacity, including a purchase of a 72.15% stake in a new factory in Zhongli for NT$42.31 billion [1] - The first transaction involves acquiring a factory in Zhongli, which will be used for advanced packaging and testing, while the second focuses on developing a new facility in Kaohsiung's Nanzih Technology Park, with a shared investment model [2] Group 2 - The Zhongli factory acquisition includes approximately 14,065.17 ping of building area and 2,119.02 ping of land, aimed at expanding the company's high-end packaging testing production lines [1] - The Kaohsiung project will involve a rental base of about 7,533.76 ping, with a total floor area of approximately 26,509.3 ping, and a distribution of rights valued at 3% for ASE and 97% for the partner [2] - The company emphasizes that these expansions will strengthen its advanced packaging and testing capabilities, addressing both short-term AI demand and long-term competitiveness in high-end processes in Taiwan [2]