这是先进封装领域增长最快的细分市场，Yole Group 预计混合键合设备在 2025 年至 2030 年间 将以 21% 的复合年增长率增长。在人工智能、高性能计算和其他基于芯片的架构的强劲需求推动 下，混合键合能够实现芯片之间的高带宽互连，且信号损耗可忽略不计。 混合键合技术已在一些高端应用中得到应用，但仍需进一步改进键合界面的质量，使键合铜互连的 性能如同在同一芯片上制造而成。考虑到需要无颗粒表面、在300mm晶圆上实现纳米级铜凹陷以 及晶圆变形极小以实现晶圆间50nm的对准精度，这无疑是一项艰巨的任务。 即便如此，将目前量产芯片上采用的9µm铜-铜连接（周围环绕绝缘介质）的混合键合工艺，扩展 到2µm甚至更小，似乎可以通过晶圆对晶圆或芯片对晶圆的混合键合来实现。这始终是所有领先代 工厂发展路线图上的重点方向。 混合键合技术最初是为了提高CMOS图像传感器的亮度而提出的巧妙解决方案。如今，它正在推动 高性能计算（HPC）的SRAM/处理器堆叠和多层3D NAND器件的突破性发展，并有望在未来实现 更紧凑的HBM模块、3D DRAM和物联网设备。 如果您希望可以时常见面，欢迎标星收藏哦~ 半导体制造的未来 ...

半导体制造的未来不再仅仅取决于尺寸的缩小。相反，芯片制造商正在重新思考器件的构建、堆叠和 供电方式。 混合键合技术或许是实现3D集成最重要的结构性推动因素，因为它可以在相同的封装尺寸内实现比 焊球多几个数量级的互连，同时还能提高信号和电源的完整性。它对于在每个封装中集成多个芯片至 关重要，并且能够降低内存/处理器的延迟，同时减少功耗。 公众号记得加星标⭐️，第一时间看推送不会错过。 这是先进封装领域增长最快的细分市场，Yole Group 预计混合键合设备在 2025 年至 2030 年间将以 21% 的复合年增长率增长。在人工智能、高性能计算和其他基于芯片的架构的强劲需求推动下，混 合键合能够实现芯片之间的高带宽互连，且信号损耗可忽略不计。 混合键合技术已在一些高端应用中得到应用，但仍需进一步改进键合界面的质量，使键合铜互连的性 能如同在同一芯片上制造而成。考虑到需要无颗粒表面、在300mm晶圆上实现纳米级铜凹陷以及晶 圆变形极小以实现晶圆间50nm的对准精度，这无疑是一项艰巨的任务。 即便如此，将目前量产芯片上采用的9µm铜-铜连接（周围环绕绝缘介质）的混合键合工艺，扩展到 2µm甚至更小，似乎可以通过晶 ...

Core Viewpoint - The article discusses the disruptive potential of hybrid bonding technology in increasing the density and complexity of integrated circuit (IC) products, while also highlighting its environmental implications [2][3]. Group 1: Hybrid Bonding Technology - Hybrid bonding is a revolutionary technology initially applied in CMOS image sensors (CIS) and is now penetrating high-performance computing (HPC) in processors and memory [3]. - The demand for hybrid bonding is expected to grow significantly, with the transition to hybrid bonding in advanced memory being a key market driver by the end of the 2020s [4]. Group 2: Environmental Impact - The number of DRAM chips in each stack is projected to triple, leading to a more than 3.5 times increase in chip emissions [5]. - While hybrid bonding processes may increase emissions at the chip level, the critical issue lies in the significant increase in silicon density, which will lead to higher carbon emissions [9][12]. Group 3: Market Projections - Revenue from hybrid bonding is expected to grow from nearly zero in 2025 to approximately $120 billion by 2029, driven by demand for high-bandwidth memory (HBM), particularly in AI applications [9]. - The emissions from HBM stacks are projected to increase significantly as the complexity of the stacks rises, with emissions per stack expected to grow substantially from HBM2E to HBM5 [13][14]. Group 4: Technical Challenges and Innovations - High-stacking HBM requires thinner DRAM chips and lower thermal budgets, which pose challenges for bonding processes [17]. - Despite these challenges, the demand for hybrid bonding technology remains strong, and innovations in the field are expected to mitigate some of the emission increases [17].

Core Insights - The article discusses the rising costs associated with advanced semiconductor processes, highlighting that the transition from planar FET to FinFET and Nanosheet technologies has led to exponential increases in design and manufacturing costs, making it difficult for small and medium enterprises to invest in advanced processes [8][9]. - The industry is shifting towards higher concentration among leading foundries, while advanced packaging technologies allow smaller companies to participate in high-end chip design without relying on advanced processes [9][11]. - The article emphasizes the importance of heterogeneous integration and the need for tailored architectures based on application scenarios, indicating a trend towards dynamic adjustments in advanced packaging strategies [25][56]. Cost Trends - Design costs have surged from $28 million for 65nm processes to $725 million for 2nm processes, with manufacturing investments also increasing significantly [9]. - The investment required for a 5nm factory is five times that of a 20nm factory, indicating a substantial financial barrier for smaller players in the industry [8]. Architectural Comparisons - The article compares four architectures, noting that smaller systems (like mobile chips) benefit from a "large chip + 3D stacking" approach, while larger systems (like AI servers) favor a "chiplet + 3D stacking" strategy to balance performance and cost [16][24]. - As system complexity increases, the advantages of chiplet-based designs become more pronounced, particularly in terms of cost efficiency [17][23]. Advanced Packaging Technologies - Advanced packaging is evolving to meet the demands of AI and high-performance computing, with technologies like 2.5D and 3D packaging becoming standard for high-end chips [36][72]. - The integration of HBM (High Bandwidth Memory) with 2.5D packaging has become a standard, driven by the need for high memory bandwidth in AI applications [29][36]. Interconnect Technologies - The article highlights the critical role of interconnect technologies in enhancing I/O density, with projections showing a significant increase in interconnect density from 1960s levels of 2/mm² to future levels of 131072/mm² [38]. - Advanced packaging is shifting from being a secondary process to a core component of performance enhancement, with interconnect-related technologies expected to yield higher profit margins than traditional packaging [39][42]. Market Dynamics - The article notes that the demand for advanced packaging is driven by the need for high bandwidth, miniaturization, and low power consumption, particularly in edge AI applications [49][50]. - The automotive sector's transition from distributed ECUs to centralized computing is pushing for higher integration levels, which in turn drives advancements in packaging technologies [53][56]. Technology Evolution - The evolution of packaging technologies is characterized by a shift from single technology optimization to system-level engineering design, necessitating cross-domain integration capabilities [68][70]. - The article outlines a clear roadmap for the evolution of interconnect technologies, indicating that the industry is entering a phase of rapid technological iteration driven by market demands [154][165]. Cost Structure - The cost structure for 2.5D packaging is primarily driven by the interposer (Si/mold/silicon bridge) and packaging substrate, while for 3D packaging, the key cost factor is the bonding process [168][169]. - The differences in cost structures dictate the profitability models for companies, with 2.5D packaging firms needing to manage interposer and substrate costs, while 3D packaging firms focus on optimizing bonding yields and efficiency [169].

Core Viewpoint - The storage market is experiencing a rare price increase across all segments, driven by the growing demand for AI servers and high-density storage, leading to a tightening of upstream capacity and healthier inventory levels [2]. Group 1: Market Dynamics - NAND manufacturers' decisions on next-generation technology routes are becoming increasingly critical, as any lead or lag will directly impact cost and performance competition over the next two to three years [3]. - SK Hynix has made a disruptive decision to introduce hybrid bonding at the 300-layer NAND node, a technology previously expected to be implemented only after reaching 400 layers [5]. - The competitive landscape is intensifying, with Samsung Electronics pushing for 400+ layer V10 NAND and Kioxia applying hybrid bonding technology in its 218-layer BiCS 3D NAND, achieving a 59% increase in bit density and a 33% improvement in NAND interface speed [5][6]. Group 2: Technological Shifts - The necessity for hybrid bonding is increasing as NAND layer counts rise, with traditional single-chip manufacturing architectures facing systemic bottlenecks beyond 300 layers [8]. - Hybrid bonding allows for separate manufacturing of storage unit wafers and peripheral circuit wafers, significantly reducing the thermal burden on peripheral circuits and enabling independent advancements in both areas [8][10]. - Kioxia's CBA technology and Samsung's CoP architecture demonstrate the advantages of hybrid bonding, achieving higher I/O speeds and improved power efficiency [11][12]. Group 3: Competitive Strategies - Samsung's aggressive dual-track strategy aims to lead in both high-layer stacking and hybrid bonding technology, although it faces significant manufacturing challenges [15]. - Kioxia's more cautious approach focuses on gradual advancements and cost control through partnerships, with plans to produce over 1000-layer 3D NAND by 2031 [16]. - Yangtze Memory Technologies has leveraged its early adoption of hybrid bonding technology to expand capacity amid a market contraction, positioning itself favorably against competitors [17]. Group 4: Industry Trends - The surge in enterprise SSD demand, driven by AI model growth, is pushing NAND manufacturers to rapidly enhance capacity and technology to seize market opportunities [20]. - The traditional PUC architecture is reaching its limits, necessitating a shift to hybrid bonding as a required option rather than a choice [24]. - The upcoming years are critical for SK Hynix as it aims to convert existing production capacity to V9 while advancing V10 development, highlighting the urgency of technological upgrades [25]. Group 5: Future Outlook - The breakthrough of hybrid bonding technology instills confidence in NAND manufacturers to pursue ultra-high layer counts, with Samsung and Kioxia setting ambitious goals for 1000-layer NAND development [27]. - Achieving 1000-layer stacking will require overcoming significant engineering challenges, including deep aspect ratio etching and maintaining reliability while compressing thickness [28][29]. - The industry is exploring various paths for expansion, including logical, physical, and performance enhancements, indicating that future NAND development will focus on a comprehensive optimization of layers, architecture, materials, and processes [38].

Core Insights - Advanced packaging technology is crucial for overcoming performance bottlenecks in the semiconductor industry, driven by emerging applications like AI, high-performance computing, and 5G communication [3] - The global advanced packaging market is projected to grow from approximately $45 billion in 2024 to $80 billion by 2030, with a compound annual growth rate (CAGR) of 9.4% [3][75] Technical Evolution Dimension - TSMC's CoWoS technology has evolved from supporting 1.5x to 3.3x mask sizes, with plans for a 5.5x version by 2025-2026 and a 9x version by 2027, significantly increasing integration density and reducing signal transmission latency [6][7] - Hybrid bonding technology is emerging as a core technology for next-generation advanced packaging, enabling direct wafer bonding without bumps, thus enhancing interconnect density and reducing power consumption [10][11] - AMD's MI300X AI accelerator utilizes a 3.5D packaging architecture, combining TSMC's SoIC and CoWoS technologies, achieving unprecedented integration levels with 1,530 billion transistors [14][15] - Intel employs a multi-technology strategy in advanced packaging, focusing on EMIB and Foveros technologies, with plans for further enhancements to improve performance and integration [18][19] - Glass substrate technology is gaining traction as a disruptive innovation, offering advantages in electrical performance, thermal stability, and cost-effectiveness, with a projected market penetration exceeding 50% within five years [22][23] Material System Analysis - BT resin substrates are the most widely used packaging material, accounting for over 70% of IC substrates, known for their excellent thermal and electrical properties [26][27] - ABF substrates, developed by Ajinomoto, are preferred for high-end chip packaging due to their superior processing capabilities and electrical performance, despite higher costs [28][30] - Ceramic substrates, particularly AlN and Si3N4, are ideal for high-performance applications due to their high thermal conductivity and mechanical strength [32][34] Equipment and Process Dimension - TCB equipment is critical for HBM packaging, with ASMPT holding over 80% market share, driven by the demand for AI chips and high-performance computing [45][47] - The global die bonder market is dominated by four major players, with ASMPT leading at 31% market share, followed by BESI, Ficontec, and Neways [49][51] - The back-end packaging equipment market is characterized by a diverse competitive landscape, with Disco leading in wafer thinning and cutting technologies [54] Industry Layout Analysis - TSMC is experiencing exponential growth in CoWoS capacity, projected to reach 65,000-75,000 units per month by 2025, driven by AI chip demand [63][65] - The HBM market is dominated by three players: SK Hynix, Samsung, and Micron, collectively holding over 95% market share, with SK Hynix leading at 60-70% [67][68] - China's packaging industry is rapidly advancing, with Jiangsu Changjiang Electronics Technology, Tongfu Microelectronics, and Huada Semiconductor becoming significant players globally [70][71] - The global advanced packaging market is shifting towards IDM manufacturers, who leverage integrated design and manufacturing advantages, with Taiwan companies holding a dominant position in the AI packaging market [73][74]

Core Viewpoint - The article discusses the advancements and challenges in heterogeneous integration technology, particularly in the context of the 2025 Heterogeneous Integration Frontier Forum held in Ningbo, highlighting the importance of collaboration among industry leaders and research institutions to drive innovation in this field [3]. Group 1: Heterogeneous Integration Technology - Advanced chip technologies such as AI, high-speed computing, and 5G/6G are driving the development of multi-chip heterogeneous integration technology, with mixed bonding technology offering advantages like smaller pitch (<2um), higher I/O density (1000X), and lower power consumption [8]. - The 2.5D/3D stacked chip design is a trend, with 2.5D Chiplet design tools becoming mature, emphasizing the need for collaboration across chip design, packaging, and EDA design [12]. - The period from 2026 to 2028 is critical for the acceleration of advanced packaging technology, which will also drive growth in supply chain materials and equipment markets [16]. Group 2: Market Demand and Applications - The magnetic sensor market has a vast application range across industrial control, medical, automotive, and consumer electronics, with annual sales reaching billions of units and a market value of hundreds of billions of dollars [18]. - High-density integrated circuit manufacturing and advanced packaging materials are crucial for the semiconductor industry chain in China, with a strong emphasis on domestic material innovation and industrialization [24]. Group 3: Technical Challenges and Innovations - Key challenges in semiconductor hybrid bonding integration technology include controlling bonding bubbles, improving edge quality, and ensuring uniform bonding energy [31]. - The development of melting/mixed bonding technology is essential for future 3D integration, with optimized chuck designs reducing local stress and improving overlay performance [37]. - Advanced packaging mass production faces difficulties related to surface smoothness, cleanliness, alignment precision, thermal control, efficiency, and yield [39].

Summary of Conference Call on Storage Industry and Key Companies Industry Overview - The storage industry is experiencing a significant upward trend in capital expenditure driven by product iterations, particularly the transition from over 200-layer to over 300-layer NAND products, with a capital expenditure slope of approximately 20%-30% per 10,000 wafers [1][2] - DRAM technology innovations, such as the increase in DDR5 market share, the implementation of 3D DRAM projects, and the industrialization of domestic HBM, are expected to further drive capital expenditure growth in the coming year [1][2] Impact on Equipment Companies - The cyclical changes in the storage industry significantly affect the revenue of upstream equipment companies. Since 2019, overseas equipment companies have seen a compound annual growth rate (CAGR) of 25%-30% in storage chain revenue [1][3] - Domestic companies like Zhongwei and Tuojing Technology benefit from the high localization rate of long-term storage equipment, with revenue exposure from the storage sector reaching 60%-70% [4][5] Key Companies Recommended - **Tuojing Technology and Zhongwei Company** are recommended due to their expected growth in orders from long-term storage expansion, with Zhongwei anticipating a 30%-40% increase in orders next year [1][5] - Tuojing Technology is expected to see rapid improvement in profitability driven by accelerated order delivery, a gross margin recovery to over 40%, and a reduction in expense ratios to 20%-25% [1][5][6] Factors Driving Profitability for Tuojing Technology - Key factors for Tuojing Technology's future profitability include: - Accelerated order delivery leading to significant revenue growth - Recovery of gross margins to over 40% - Expense reductions, including stable employee compensation and decreased stock incentive costs, allowing profit margins to potentially rise to 20%-25% [6] - New layouts in the hybrid bonding sector are expected to create additional market demand, particularly with the rollout of 3D DRAM projects and HBM 5 industrialization [6] Importance of Hybrid Bonding Technology - Hybrid bonding technology is crucial for Tuojing Technology's development, meeting current demands and extending into future markets [7] - By 2026, successful validation from downstream customers and expanded demand in sectors such as SOIC, GPO, and smart glasses will enhance the company's growth potential [7] Additional Equipment Companies to Watch - Besides the core recommendations, smaller equipment companies like Jiao Cheng Ultrasonic and Jing Zhi Da are also worth monitoring. These companies may experience favorable order elasticity and exposure as HBM 0-1 enters industrialization in 2026 [8]

Core Viewpoint - The article emphasizes the critical role of hybrid bonding technology in advancing semiconductor manufacturing, particularly as it moves towards sub-micron dimensions, highlighting the challenges and necessary innovations in process control and design integration [2][3][26]. Group 1: Current State of Hybrid Bonding - Hybrid bonding has been in production for years, achieving stable yields with 10µm interconnects, but as the process scales down to 5µm, the tolerances become extremely tight, requiring precise control of surface morphology and alignment [2][3]. - Most manufacturers currently operate within the 8 to 6µm range, with new bonding and measurement equipment pushing defect rates closer to the sub-micron thresholds needed for next-generation applications [3][5]. Group 2: Challenges in Sub-Micron Bonding - As bonding distances shrink below 1µm, surface treatment and alignment become equally critical, with even minor defects potentially leading to significant yield loss [5][6]. - Defect control extends beyond microscopic features; macro defects like edge chipping and residue can critically impact yield, necessitating rigorous inspection of the entire wafer [6][7]. Group 3: Process Control and Measurement - The complexity of managing variables in sub-micron bonding requires a fundamental restructuring of design, measurement, and process control interactions [2][5]. - Real-time monitoring and feedback control systems are essential to maintain alignment and process parameters, as even slight deviations can lead to yield loss [15][16]. Group 4: Integration of Design and Manufacturing - The separation between design and manufacturing becomes a burden as hybrid bonding technology advances, necessitating early consideration of bonding process parameters in design [23][24]. - Assembly Design Kits (ADK) bridge the gap by translating manufacturing constraints into actionable design rules, ensuring that designs are manufacturable and yield-friendly [23][24]. Group 5: Future Directions and Economic Viability - The success of sub-micron hybrid bonding hinges on the integration of design, process, and supply chain ecosystems, with a focus on achieving predictable economic benefits [26][27]. - The industry must address interoperability issues among equipment from different suppliers and the challenges posed by heterogeneous stacking to realize the full potential of hybrid bonding technology [26][27].

Group 1 - Major South Korean semiconductor companies, including Samsung Electronics and SK Hynix, are slowing down investments in advanced NAND due to high demand uncertainty and a focus on DRAM and packaging sectors [1][2] - Samsung Electronics has been transitioning investments at its P1 and Xi'an NAND factories from 6th and 7th generation NAND to 8th and 9th generation NAND, with conversion investments being more efficient and less costly than building new production lines [1] - The conversion speed for the latest NAND technology is slowing, with the 9th generation NAND conversion at the P1 factory being delayed and the Xi'an factory's X2 production line only planning to execute a minimal scale of 5,000 wafers per month [1][2] Group 2 - A semiconductor industry insider indicated that Samsung plans to continue mass production of older generation NAND on the X2 production line until at least mid-next year due to low demand for advanced NAND [2] - Samsung has decided to postpone the application of hybrid bonding technology for V9 NAND, originally intended for the Xi'an X2 production line, with plans to start using this technology from the 10th generation NAND (V10) at the earliest by mid-next year [2] - SK Hynix is also focusing its investments on advanced DRAM and HBM, with slower R&D progress for V10 NAND compared to Samsung, leading to a cautious investment approach based on downstream demand [2]