公众号记得加星标⭐️，第一时间看推送不会错过。 来源 ：内容 编译自 semienginerring 。 混合键合已投入生产多年，其成熟的流程能够使用 10µm 互连实现稳定的良率。在这种规模下，工艺 可以容忍数百纳米的套刻偏差、晶圆翘曲度的细微差异以及与互连高度相当的颗粒尺寸，而不会造成 灾难性的影响。混合键合与光学计量、现有的 CMP 工艺以及先进的工艺控制兼容。 然而，当堆叠器件的键合工艺扩展到 5µm 间距时，工艺窗口会缩小到两位数纳米的公差。颗粒尺寸 限制急剧缩小，局部表面形貌必须精确控制，键合过程中即使是轻微的热漂移或机械漂移也可能会系 统性地影响良率。现有的检测方法开始达到衍射极限，校正回路必须实时运行，并且设计必须从一开 始就考虑键合约束。 Lam Research高级副总裁 Vahid Vahedi在 ITF World 的一次演讲中表示："解决方案领域正变得非 常非常具有挑战性，我们正处于一个关键时刻，单靠人类的力量无法实现所需的创新。最先进的工具 在反应堆上拥有足够多的旋钮，可以提供 10 到 18 个独特的配方，但如果你是一名工艺工程师，想 要调整这些配方，你该如何找到合适的方案呢？" ...

Group 1 - Major South Korean semiconductor companies, including Samsung Electronics and SK Hynix, are slowing down investments in advanced NAND due to high demand uncertainty and a focus on DRAM and packaging sectors [1][2] - Samsung Electronics has been transitioning investments at its P1 and Xi'an NAND factories from 6th and 7th generation NAND to 8th and 9th generation NAND, with conversion investments being more efficient and less costly than building new production lines [1] - The conversion speed for the latest NAND technology is slowing, with the 9th generation NAND conversion at the P1 factory being delayed and the Xi'an factory's X2 production line only planning to execute a minimal scale of 5,000 wafers per month [1][2] Group 2 - A semiconductor industry insider indicated that Samsung plans to continue mass production of older generation NAND on the X2 production line until at least mid-next year due to low demand for advanced NAND [2] - Samsung has decided to postpone the application of hybrid bonding technology for V9 NAND, originally intended for the Xi'an X2 production line, with plans to start using this technology from the 10th generation NAND (V10) at the earliest by mid-next year [2] - SK Hynix is also focusing its investments on advanced DRAM and HBM, with slower R&D progress for V10 NAND compared to Samsung, leading to a cautious investment approach based on downstream demand [2]

Core Viewpoint - The article discusses the advancements in semiconductor technology, particularly in AI applications, focusing on key trends such as advanced packaging, CPO technology, and cooling solutions to address performance and efficiency challenges in AI accelerators [2][3]. Advanced Packaging Technology - Advanced packaging is evolving through Chiplet technology and hybrid bonding to enhance AI processor performance. The shift from silicon interposers to silicon bridges and organic RDL is aimed at cost reduction, with a future transition to panel-level packaging expected by 2028-2029 [4][5]. - Hybrid bonding is crucial for improving performance by reducing the bonding area through enhanced alignment precision [5]. CPO Technology - CPO (Co-Packaged Optics) is identified as the next-generation connection technology for AI data center servers, effectively reducing power consumption in high-bandwidth scenarios. However, high costs and the complexity of precise assembly remain significant challenges [6]. - The introduction of next-generation 448Gb SerDes technology may increase CPO adoption, as it addresses signal degradation issues by minimizing transmission distances [6]. Client Device Packaging - In client devices, semiconductor manufacturers are carefully selecting between Chiplet and monolithic architectures based on cost and performance considerations. For instance, AMD's latest Radeon series GPU has integrated previously Chiplet-based SRAM into a monolithic design [7]. - Apple's Vision Pro features a Chiplet package with two high-bandwidth custom DRAM chips, showcasing the trend towards specialized high-performance processors [7]. Cooling Solutions - Traditional cooling methods like air and water cooling are becoming less effective due to increasing power density in AI accelerators. Two-phase liquid cooling is emerging as a key solution due to its high energy efficiency and broad applicability [3][9]. - Different cooling technologies are suited for varying thermal densities: air cooling for below 10W/cm², two-phase liquid cooling for 10-100W/cm², and water cooling for above 100W/cm². The next-generation 3nm AI data center GPUs are expected to have thermal densities around 100W/cm², making two-phase liquid cooling particularly relevant [10][11][12].

Group 1 - The core concept of hybrid bonding technology is gaining traction among major semiconductor companies like TSMC and Samsung, as it is seen as a key to advancing packaging technology for the next decade [2][4][10] - Hybrid bonding allows for high-density, high-performance interconnections between different chips, significantly improving signal transmission speed and reducing power consumption compared to traditional methods [5][11] - The technology is particularly relevant for high bandwidth memory (HBM) products, with leading manufacturers like SK Hynix, Samsung, and Micron planning to adopt hybrid bonding in their upcoming HBM5 products to meet increasing bandwidth demands [10][12] Group 2 - TSMC's SoIC technology utilizes hybrid bonding, achieving a 15-fold increase in chip connection density compared to traditional methods, which enhances performance and reduces size [14][15] - Intel has also entered the hybrid bonding space with its 3D Foveros technology, which significantly increases the number of interconnections per square millimeter, enhancing integration capabilities [19] - SK Hynix and Samsung are actively testing and planning to implement hybrid bonding in their next-generation HBM products, with Samsung emphasizing the need for this technology to meet height restrictions in memory packaging [20][22] Group 3 - The global hybrid bonding technology market is projected to grow from $123.49 million in 2023 to $618.42 million by 2030, with a compound annual growth rate (CAGR) of 24.7%, particularly strong in the Asia-Pacific region [22]

Core Viewpoint - The article emphasizes the rapid development and industrialization of hybrid bonding technology as a key enabler for overcoming performance bottlenecks in the semiconductor industry, particularly in the post-Moore's Law era [1][12]. Group 1: Hybrid Bonding Technology Overview - Hybrid bonding technology, also known as direct bonding interconnect, is a core technology in advanced packaging, enabling high-density vertical interconnections between chips through copper-copper and dielectric bonding [3][12]. - This technology allows for interconnect distances below 1μm, significantly increasing the number of I/O contacts per unit area compared to traditional bump bonding, which has distances above 20μm [3][5]. - Advantages include improved thermal management, enhanced reliability, flexibility in 3D integration, and compatibility with existing wafer-level manufacturing processes [3][5]. Group 2: Industry Adoption and Applications - Major semiconductor companies like SK Hynix and Samsung are adopting hybrid bonding in their products, such as HBM3E and 3D DRAM, achieving significant improvements in thermal performance and chip density [5][8]. - Samsung's implementation of hybrid bonding has reduced chip area by 30% while enhancing integration [8]. - TSMC's SoIC technology and NVIDIA's GPUs also utilize hybrid bonding to improve performance and density in advanced applications [10][11]. Group 3: Market Growth and Equipment Demand - The global hybrid bonding equipment market is projected to grow from approximately $421 million in 2023 to $1.332 billion by 2030, with a compound annual growth rate (CAGR) of 30% [13]. - Equipment manufacturers are competing to meet the rising demand for high-precision bonding machines and related technologies, with companies like Applied Materials and ASMPT leading the charge [13][14]. Group 4: Competitive Landscape - Applied Materials is focusing on building a comprehensive hybrid bonding ecosystem through strategic investments and partnerships, aiming to cover the entire process from material to bonding [14][15]. - ASMPT is enhancing its position by developing high-precision bonding technologies and collaborating with industry leaders to drive standardization [17][22]. - BESI is capitalizing on the demand for AI chips and HBM packaging, with a significant market share in CIS sensors and a focus on high-precision bonding equipment [18][19]. Group 5: Future Trends and Challenges - The shift from 2D scaling to 3D integration is reshaping the competitive landscape in the semiconductor industry, with hybrid bonding technology at the forefront [22][23]. - Despite its potential, hybrid bonding faces challenges such as high costs and stringent manufacturing environment requirements, which may slow its widespread adoption [23][21].

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Core Viewpoint - Samsung Electronics is focusing on "Fluxless" as a new bonding technology for high-bandwidth memory (HBM), currently in the research and development phase, with evaluations expected to be completed by the end of the year [1][4][5]. Group 1: Current Technology and Developments - Samsung is currently using Non-Conductive Film (NCF) as a post-processing technology for HBM manufacturing, which involves stacking multiple DRAMs to enhance data processing performance [2][3]. - The existing MR-MUF (Mass Reflow Underfill) technology requires the application of a flux to remove oxidation from bumps, which may not be effective with the increased number of I/O terminals in HBM4, potentially compromising chip reliability [3][4]. Group 2: Future Technology Considerations - Samsung is closely examining the application of fluxless bonding, initially intended for logic semiconductors but now prioritized for HBM4 due to investment focus [4][5]. - The industry anticipates that Samsung will consider three bonding technologies for HBM4: NCF, fluxless, and hybrid bonding, with challenges in reliability and thermal characteristics for NCF and maturity for hybrid bonding [6]. Group 3: Competitive Landscape - SK Hynix is also exploring the application of fluxless bonding for HBM4, benefiting from its existing use of MR-MUF technology, which may provide easier access to fluxless methods [6].