"宁波膜智信息科技有限公司"为势银（TrendBank）唯一工商注册实体及收款账户 添加文末微信，加 异质异构集成产业 群 11月18-19日， 2025异质异构集成前沿论坛暨甬江实验室信息材料与微纳器件制备平台验证线通线仪式 在宁波泛太平洋大酒店举行。 论坛现场 吸引了国内外相关领域的龙头企业和科研机构参会，各方围绕前沿成果、技术趋势和关键挑战进行了深入交流，探讨合作路径。 嘉宾签到&论坛现场 ▼ 左右滑动查看更多 18日下午，大会1号厅举行 异质集成与先进封装论坛 —— 赵毅： 2.5D / 3D 堆叠芯片是时代趋势，其中 2.5D Chiplet 部分设计工具成熟 ， 设计前移 ，各环节协同 ， 可靠性测试 值得探索； 3D IC 设 计方法学， 全局优化复杂度 极高特殊；因此产业整体的发展还需要芯片设计、封装制造、EDA 设计通力配合。 简志宏 ： 先进 Chiplets 整合技术的延伸和快速发展，使得HDFO、2.5 D、3D 等异质/异构整合集成技术方案及结构正突破封IC集成的痛点，极大 推进先进性能晶圆级封装技术的发展。 高占占 ： 2026-2028 年是全球先进封装技术加速渗透，以及新技术从 ...

Summary of Conference Call on Storage Industry and Key Companies Industry Overview - The storage industry is experiencing a significant upward trend in capital expenditure driven by product iterations, particularly the transition from over 200-layer to over 300-layer NAND products, with a capital expenditure slope of approximately 20%-30% per 10,000 wafers [1][2] - DRAM technology innovations, such as the increase in DDR5 market share, the implementation of 3D DRAM projects, and the industrialization of domestic HBM, are expected to further drive capital expenditure growth in the coming year [1][2] Impact on Equipment Companies - The cyclical changes in the storage industry significantly affect the revenue of upstream equipment companies. Since 2019, overseas equipment companies have seen a compound annual growth rate (CAGR) of 25%-30% in storage chain revenue [1][3] - Domestic companies like Zhongwei and Tuojing Technology benefit from the high localization rate of long-term storage equipment, with revenue exposure from the storage sector reaching 60%-70% [4][5] Key Companies Recommended - **Tuojing Technology and Zhongwei Company** are recommended due to their expected growth in orders from long-term storage expansion, with Zhongwei anticipating a 30%-40% increase in orders next year [1][5] - Tuojing Technology is expected to see rapid improvement in profitability driven by accelerated order delivery, a gross margin recovery to over 40%, and a reduction in expense ratios to 20%-25% [1][5][6] Factors Driving Profitability for Tuojing Technology - Key factors for Tuojing Technology's future profitability include: - Accelerated order delivery leading to significant revenue growth - Recovery of gross margins to over 40% - Expense reductions, including stable employee compensation and decreased stock incentive costs, allowing profit margins to potentially rise to 20%-25% [6] - New layouts in the hybrid bonding sector are expected to create additional market demand, particularly with the rollout of 3D DRAM projects and HBM 5 industrialization [6] Importance of Hybrid Bonding Technology - Hybrid bonding technology is crucial for Tuojing Technology's development, meeting current demands and extending into future markets [7] - By 2026, successful validation from downstream customers and expanded demand in sectors such as SOIC, GPO, and smart glasses will enhance the company's growth potential [7] Additional Equipment Companies to Watch - Besides the core recommendations, smaller equipment companies like Jiao Cheng Ultrasonic and Jing Zhi Da are also worth monitoring. These companies may experience favorable order elasticity and exposure as HBM 0-1 enters industrialization in 2026 [8]

Core Viewpoint - The article emphasizes the critical role of hybrid bonding technology in advancing semiconductor manufacturing, particularly as it moves towards sub-micron dimensions, highlighting the challenges and necessary innovations in process control and design integration [2][3][26]. Group 1: Current State of Hybrid Bonding - Hybrid bonding has been in production for years, achieving stable yields with 10µm interconnects, but as the process scales down to 5µm, the tolerances become extremely tight, requiring precise control of surface morphology and alignment [2][3]. - Most manufacturers currently operate within the 8 to 6µm range, with new bonding and measurement equipment pushing defect rates closer to the sub-micron thresholds needed for next-generation applications [3][5]. Group 2: Challenges in Sub-Micron Bonding - As bonding distances shrink below 1µm, surface treatment and alignment become equally critical, with even minor defects potentially leading to significant yield loss [5][6]. - Defect control extends beyond microscopic features; macro defects like edge chipping and residue can critically impact yield, necessitating rigorous inspection of the entire wafer [6][7]. Group 3: Process Control and Measurement - The complexity of managing variables in sub-micron bonding requires a fundamental restructuring of design, measurement, and process control interactions [2][5]. - Real-time monitoring and feedback control systems are essential to maintain alignment and process parameters, as even slight deviations can lead to yield loss [15][16]. Group 4: Integration of Design and Manufacturing - The separation between design and manufacturing becomes a burden as hybrid bonding technology advances, necessitating early consideration of bonding process parameters in design [23][24]. - Assembly Design Kits (ADK) bridge the gap by translating manufacturing constraints into actionable design rules, ensuring that designs are manufacturable and yield-friendly [23][24]. Group 5: Future Directions and Economic Viability - The success of sub-micron hybrid bonding hinges on the integration of design, process, and supply chain ecosystems, with a focus on achieving predictable economic benefits [26][27]. - The industry must address interoperability issues among equipment from different suppliers and the challenges posed by heterogeneous stacking to realize the full potential of hybrid bonding technology [26][27].

Group 1 - Major South Korean semiconductor companies, including Samsung Electronics and SK Hynix, are slowing down investments in advanced NAND due to high demand uncertainty and a focus on DRAM and packaging sectors [1][2] - Samsung Electronics has been transitioning investments at its P1 and Xi'an NAND factories from 6th and 7th generation NAND to 8th and 9th generation NAND, with conversion investments being more efficient and less costly than building new production lines [1] - The conversion speed for the latest NAND technology is slowing, with the 9th generation NAND conversion at the P1 factory being delayed and the Xi'an factory's X2 production line only planning to execute a minimal scale of 5,000 wafers per month [1][2] Group 2 - A semiconductor industry insider indicated that Samsung plans to continue mass production of older generation NAND on the X2 production line until at least mid-next year due to low demand for advanced NAND [2] - Samsung has decided to postpone the application of hybrid bonding technology for V9 NAND, originally intended for the Xi'an X2 production line, with plans to start using this technology from the 10th generation NAND (V10) at the earliest by mid-next year [2] - SK Hynix is also focusing its investments on advanced DRAM and HBM, with slower R&D progress for V10 NAND compared to Samsung, leading to a cautious investment approach based on downstream demand [2]

Core Viewpoint - The article discusses the advancements in semiconductor technology, particularly in AI applications, focusing on key trends such as advanced packaging, CPO technology, and cooling solutions to address performance and efficiency challenges in AI accelerators [2][3]. Advanced Packaging Technology - Advanced packaging is evolving through Chiplet technology and hybrid bonding to enhance AI processor performance. The shift from silicon interposers to silicon bridges and organic RDL is aimed at cost reduction, with a future transition to panel-level packaging expected by 2028-2029 [4][5]. - Hybrid bonding is crucial for improving performance by reducing the bonding area through enhanced alignment precision [5]. CPO Technology - CPO (Co-Packaged Optics) is identified as the next-generation connection technology for AI data center servers, effectively reducing power consumption in high-bandwidth scenarios. However, high costs and the complexity of precise assembly remain significant challenges [6]. - The introduction of next-generation 448Gb SerDes technology may increase CPO adoption, as it addresses signal degradation issues by minimizing transmission distances [6]. Client Device Packaging - In client devices, semiconductor manufacturers are carefully selecting between Chiplet and monolithic architectures based on cost and performance considerations. For instance, AMD's latest Radeon series GPU has integrated previously Chiplet-based SRAM into a monolithic design [7]. - Apple's Vision Pro features a Chiplet package with two high-bandwidth custom DRAM chips, showcasing the trend towards specialized high-performance processors [7]. Cooling Solutions - Traditional cooling methods like air and water cooling are becoming less effective due to increasing power density in AI accelerators. Two-phase liquid cooling is emerging as a key solution due to its high energy efficiency and broad applicability [3][9]. - Different cooling technologies are suited for varying thermal densities: air cooling for below 10W/cm², two-phase liquid cooling for 10-100W/cm², and water cooling for above 100W/cm². The next-generation 3nm AI data center GPUs are expected to have thermal densities around 100W/cm², making two-phase liquid cooling particularly relevant [10][11][12].

Group 1 - The core concept of hybrid bonding technology is gaining traction among major semiconductor companies like TSMC and Samsung, as it is seen as a key to advancing packaging technology for the next decade [2][4][10] - Hybrid bonding allows for high-density, high-performance interconnections between different chips, significantly improving signal transmission speed and reducing power consumption compared to traditional methods [5][11] - The technology is particularly relevant for high bandwidth memory (HBM) products, with leading manufacturers like SK Hynix, Samsung, and Micron planning to adopt hybrid bonding in their upcoming HBM5 products to meet increasing bandwidth demands [10][12] Group 2 - TSMC's SoIC technology utilizes hybrid bonding, achieving a 15-fold increase in chip connection density compared to traditional methods, which enhances performance and reduces size [14][15] - Intel has also entered the hybrid bonding space with its 3D Foveros technology, which significantly increases the number of interconnections per square millimeter, enhancing integration capabilities [19] - SK Hynix and Samsung are actively testing and planning to implement hybrid bonding in their next-generation HBM products, with Samsung emphasizing the need for this technology to meet height restrictions in memory packaging [20][22] Group 3 - The global hybrid bonding technology market is projected to grow from $123.49 million in 2023 to $618.42 million by 2030, with a compound annual growth rate (CAGR) of 24.7%, particularly strong in the Asia-Pacific region [22]

Core Viewpoint - The article emphasizes the rapid development and industrialization of hybrid bonding technology as a key enabler for overcoming performance bottlenecks in the semiconductor industry, particularly in the post-Moore's Law era [1][12]. Group 1: Hybrid Bonding Technology Overview - Hybrid bonding technology, also known as direct bonding interconnect, is a core technology in advanced packaging, enabling high-density vertical interconnections between chips through copper-copper and dielectric bonding [3][12]. - This technology allows for interconnect distances below 1μm, significantly increasing the number of I/O contacts per unit area compared to traditional bump bonding, which has distances above 20μm [3][5]. - Advantages include improved thermal management, enhanced reliability, flexibility in 3D integration, and compatibility with existing wafer-level manufacturing processes [3][5]. Group 2: Industry Adoption and Applications - Major semiconductor companies like SK Hynix and Samsung are adopting hybrid bonding in their products, such as HBM3E and 3D DRAM, achieving significant improvements in thermal performance and chip density [5][8]. - Samsung's implementation of hybrid bonding has reduced chip area by 30% while enhancing integration [8]. - TSMC's SoIC technology and NVIDIA's GPUs also utilize hybrid bonding to improve performance and density in advanced applications [10][11]. Group 3: Market Growth and Equipment Demand - The global hybrid bonding equipment market is projected to grow from approximately $421 million in 2023 to $1.332 billion by 2030, with a compound annual growth rate (CAGR) of 30% [13]. - Equipment manufacturers are competing to meet the rising demand for high-precision bonding machines and related technologies, with companies like Applied Materials and ASMPT leading the charge [13][14]. Group 4: Competitive Landscape - Applied Materials is focusing on building a comprehensive hybrid bonding ecosystem through strategic investments and partnerships, aiming to cover the entire process from material to bonding [14][15]. - ASMPT is enhancing its position by developing high-precision bonding technologies and collaborating with industry leaders to drive standardization [17][22]. - BESI is capitalizing on the demand for AI chips and HBM packaging, with a significant market share in CIS sensors and a focus on high-precision bonding equipment [18][19]. Group 5: Future Trends and Challenges - The shift from 2D scaling to 3D integration is reshaping the competitive landscape in the semiconductor industry, with hybrid bonding technology at the forefront [22][23]. - Despite its potential, hybrid bonding faces challenges such as high costs and stringent manufacturing environment requirements, which may slow its widespread adoption [23][21].

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Core Viewpoint - Samsung Electronics is focusing on "Fluxless" as a new bonding technology for high-bandwidth memory (HBM), currently in the research and development phase, with evaluations expected to be completed by the end of the year [1][4][5]. Group 1: Current Technology and Developments - Samsung is currently using Non-Conductive Film (NCF) as a post-processing technology for HBM manufacturing, which involves stacking multiple DRAMs to enhance data processing performance [2][3]. - The existing MR-MUF (Mass Reflow Underfill) technology requires the application of a flux to remove oxidation from bumps, which may not be effective with the increased number of I/O terminals in HBM4, potentially compromising chip reliability [3][4]. Group 2: Future Technology Considerations - Samsung is closely examining the application of fluxless bonding, initially intended for logic semiconductors but now prioritized for HBM4 due to investment focus [4][5]. - The industry anticipates that Samsung will consider three bonding technologies for HBM4: NCF, fluxless, and hybrid bonding, with challenges in reliability and thermal characteristics for NCF and maturity for hybrid bonding [6]. Group 3: Competitive Landscape - SK Hynix is also exploring the application of fluxless bonding for HBM4, benefiting from its existing use of MR-MUF technology, which may provide easier access to fluxless methods [6].