点击 最 下方 关注《材料汇》 ， 点击"❤"和" "并分享 添加 小编微信 ，寻 志同道合 的你 正文 先进制程的成本暴涨体现在设计和建厂两端： 制程从平面 FET 演进至 FinFET、Nanosheet 后，量子效应、测试验证难度激增，导致设计成本指数级上 升；5nm 工厂投资是 20nm 的 5 倍，中小企业已无力承担先进制程的资本开支。 图表清晰展示，随着关键尺寸微缩，设计成本从 65nm 的 2800 万美元飙升至 2nm 的 7.25 亿美元，建厂投入同步激增。 这背后意味着 行业集中度将向头部晶圆厂倾斜，而先进封装通过 "混合制程" 让中小企业无需依赖先进制程即可参与高端芯片设计，成为行业格局重构的 关键变量。 芯粒异构集成的核心是 "按需分配工艺" ——CPU 等核心部件用 3nm 先进制程，I/O、模拟电路用成熟制程，最大化性价比。 与单片集成相比，其优势集中在 "IP 复用""良率改善""缩短上市时间"： IP 复用避免重复设计，研发周期缩短 30% 以上；小芯片良率远高于大芯片，拆 分后整体良率叠加，实际生产成本大幅降低；独立验证机制减少试错成本，快速响应市场需求。 这背后是 芯片行业 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 为何混合键合成为必选项？ 对于NAND厂商而言，伴随着层数的不断攀升，采用混合键合的必要性正在不断增加。 从技术层面来看，当NAND层数突破300层后，传统的单片制造架构开始遭遇系统性瓶颈。在PUC （Peri under Cell，单元下外围电路）架构中，外围电路被构建在晶圆的最底部，而数百层的存储单 元堆叠在其上。这意味着外围电路必须承受整个堆叠制程的高温考验——其长期暴露在高温环境中， 导致晶体管性能退化、良率恶化，可靠性问题日益突出。 而根据业内人士透露，SK海力士在321层V9 NAND之前一直采用PUC工艺。但随着层数增加，外围 电路故障的可能性也随之增加。三星电子在推进V9（286层）到V10（400+层）的过程中，同样面临 这一挑战。更关键的是，堆叠效率的下降让单纯依靠增加层数变得越来越不经济。 提前一个世代的决策背后，是残酷的市场竞争现实。三星电子正全力冲刺400多层的V10 NAND，其 采用的混合键合外围单元（CoP）架构已经完成技术验证。虽然三星V10的量产之路并不顺利——原 定今年年底开始量产的计划已经推迟，超低温蚀刻设备的评估仍在进行 ...

Core Insights - Advanced packaging technology is crucial for overcoming performance bottlenecks in the semiconductor industry, driven by emerging applications like AI, high-performance computing, and 5G communication [3] - The global advanced packaging market is projected to grow from approximately $45 billion in 2024 to $80 billion by 2030, with a compound annual growth rate (CAGR) of 9.4% [3][75] Technical Evolution Dimension - TSMC's CoWoS technology has evolved from supporting 1.5x to 3.3x mask sizes, with plans for a 5.5x version by 2025-2026 and a 9x version by 2027, significantly increasing integration density and reducing signal transmission latency [6][7] - Hybrid bonding technology is emerging as a core technology for next-generation advanced packaging, enabling direct wafer bonding without bumps, thus enhancing interconnect density and reducing power consumption [10][11] - AMD's MI300X AI accelerator utilizes a 3.5D packaging architecture, combining TSMC's SoIC and CoWoS technologies, achieving unprecedented integration levels with 1,530 billion transistors [14][15] - Intel employs a multi-technology strategy in advanced packaging, focusing on EMIB and Foveros technologies, with plans for further enhancements to improve performance and integration [18][19] - Glass substrate technology is gaining traction as a disruptive innovation, offering advantages in electrical performance, thermal stability, and cost-effectiveness, with a projected market penetration exceeding 50% within five years [22][23] Material System Analysis - BT resin substrates are the most widely used packaging material, accounting for over 70% of IC substrates, known for their excellent thermal and electrical properties [26][27] - ABF substrates, developed by Ajinomoto, are preferred for high-end chip packaging due to their superior processing capabilities and electrical performance, despite higher costs [28][30] - Ceramic substrates, particularly AlN and Si3N4, are ideal for high-performance applications due to their high thermal conductivity and mechanical strength [32][34] Equipment and Process Dimension - TCB equipment is critical for HBM packaging, with ASMPT holding over 80% market share, driven by the demand for AI chips and high-performance computing [45][47] - The global die bonder market is dominated by four major players, with ASMPT leading at 31% market share, followed by BESI, Ficontec, and Neways [49][51] - The back-end packaging equipment market is characterized by a diverse competitive landscape, with Disco leading in wafer thinning and cutting technologies [54] Industry Layout Analysis - TSMC is experiencing exponential growth in CoWoS capacity, projected to reach 65,000-75,000 units per month by 2025, driven by AI chip demand [63][65] - The HBM market is dominated by three players: SK Hynix, Samsung, and Micron, collectively holding over 95% market share, with SK Hynix leading at 60-70% [67][68] - China's packaging industry is rapidly advancing, with Jiangsu Changjiang Electronics Technology, Tongfu Microelectronics, and Huada Semiconductor becoming significant players globally [70][71] - The global advanced packaging market is shifting towards IDM manufacturers, who leverage integrated design and manufacturing advantages, with Taiwan companies holding a dominant position in the AI packaging market [73][74]

Core Viewpoint - The article discusses the advancements and challenges in heterogeneous integration technology, particularly in the context of the 2025 Heterogeneous Integration Frontier Forum held in Ningbo, highlighting the importance of collaboration among industry leaders and research institutions to drive innovation in this field [3]. Group 1: Heterogeneous Integration Technology - Advanced chip technologies such as AI, high-speed computing, and 5G/6G are driving the development of multi-chip heterogeneous integration technology, with mixed bonding technology offering advantages like smaller pitch (<2um), higher I/O density (1000X), and lower power consumption [8]. - The 2.5D/3D stacked chip design is a trend, with 2.5D Chiplet design tools becoming mature, emphasizing the need for collaboration across chip design, packaging, and EDA design [12]. - The period from 2026 to 2028 is critical for the acceleration of advanced packaging technology, which will also drive growth in supply chain materials and equipment markets [16]. Group 2: Market Demand and Applications - The magnetic sensor market has a vast application range across industrial control, medical, automotive, and consumer electronics, with annual sales reaching billions of units and a market value of hundreds of billions of dollars [18]. - High-density integrated circuit manufacturing and advanced packaging materials are crucial for the semiconductor industry chain in China, with a strong emphasis on domestic material innovation and industrialization [24]. Group 3: Technical Challenges and Innovations - Key challenges in semiconductor hybrid bonding integration technology include controlling bonding bubbles, improving edge quality, and ensuring uniform bonding energy [31]. - The development of melting/mixed bonding technology is essential for future 3D integration, with optimized chuck designs reducing local stress and improving overlay performance [37]. - Advanced packaging mass production faces difficulties related to surface smoothness, cleanliness, alignment precision, thermal control, efficiency, and yield [39].

Summary of Conference Call on Storage Industry and Key Companies Industry Overview - The storage industry is experiencing a significant upward trend in capital expenditure driven by product iterations, particularly the transition from over 200-layer to over 300-layer NAND products, with a capital expenditure slope of approximately 20%-30% per 10,000 wafers [1][2] - DRAM technology innovations, such as the increase in DDR5 market share, the implementation of 3D DRAM projects, and the industrialization of domestic HBM, are expected to further drive capital expenditure growth in the coming year [1][2] Impact on Equipment Companies - The cyclical changes in the storage industry significantly affect the revenue of upstream equipment companies. Since 2019, overseas equipment companies have seen a compound annual growth rate (CAGR) of 25%-30% in storage chain revenue [1][3] - Domestic companies like Zhongwei and Tuojing Technology benefit from the high localization rate of long-term storage equipment, with revenue exposure from the storage sector reaching 60%-70% [4][5] Key Companies Recommended - **Tuojing Technology and Zhongwei Company** are recommended due to their expected growth in orders from long-term storage expansion, with Zhongwei anticipating a 30%-40% increase in orders next year [1][5] - Tuojing Technology is expected to see rapid improvement in profitability driven by accelerated order delivery, a gross margin recovery to over 40%, and a reduction in expense ratios to 20%-25% [1][5][6] Factors Driving Profitability for Tuojing Technology - Key factors for Tuojing Technology's future profitability include: - Accelerated order delivery leading to significant revenue growth - Recovery of gross margins to over 40% - Expense reductions, including stable employee compensation and decreased stock incentive costs, allowing profit margins to potentially rise to 20%-25% [6] - New layouts in the hybrid bonding sector are expected to create additional market demand, particularly with the rollout of 3D DRAM projects and HBM 5 industrialization [6] Importance of Hybrid Bonding Technology - Hybrid bonding technology is crucial for Tuojing Technology's development, meeting current demands and extending into future markets [7] - By 2026, successful validation from downstream customers and expanded demand in sectors such as SOIC, GPO, and smart glasses will enhance the company's growth potential [7] Additional Equipment Companies to Watch - Besides the core recommendations, smaller equipment companies like Jiao Cheng Ultrasonic and Jing Zhi Da are also worth monitoring. These companies may experience favorable order elasticity and exposure as HBM 0-1 enters industrialization in 2026 [8]

Core Viewpoint - The article emphasizes the critical role of hybrid bonding technology in advancing semiconductor manufacturing, particularly as it moves towards sub-micron dimensions, highlighting the challenges and necessary innovations in process control and design integration [2][3][26]. Group 1: Current State of Hybrid Bonding - Hybrid bonding has been in production for years, achieving stable yields with 10µm interconnects, but as the process scales down to 5µm, the tolerances become extremely tight, requiring precise control of surface morphology and alignment [2][3]. - Most manufacturers currently operate within the 8 to 6µm range, with new bonding and measurement equipment pushing defect rates closer to the sub-micron thresholds needed for next-generation applications [3][5]. Group 2: Challenges in Sub-Micron Bonding - As bonding distances shrink below 1µm, surface treatment and alignment become equally critical, with even minor defects potentially leading to significant yield loss [5][6]. - Defect control extends beyond microscopic features; macro defects like edge chipping and residue can critically impact yield, necessitating rigorous inspection of the entire wafer [6][7]. Group 3: Process Control and Measurement - The complexity of managing variables in sub-micron bonding requires a fundamental restructuring of design, measurement, and process control interactions [2][5]. - Real-time monitoring and feedback control systems are essential to maintain alignment and process parameters, as even slight deviations can lead to yield loss [15][16]. Group 4: Integration of Design and Manufacturing - The separation between design and manufacturing becomes a burden as hybrid bonding technology advances, necessitating early consideration of bonding process parameters in design [23][24]. - Assembly Design Kits (ADK) bridge the gap by translating manufacturing constraints into actionable design rules, ensuring that designs are manufacturable and yield-friendly [23][24]. Group 5: Future Directions and Economic Viability - The success of sub-micron hybrid bonding hinges on the integration of design, process, and supply chain ecosystems, with a focus on achieving predictable economic benefits [26][27]. - The industry must address interoperability issues among equipment from different suppliers and the challenges posed by heterogeneous stacking to realize the full potential of hybrid bonding technology [26][27].

Group 1 - Major South Korean semiconductor companies, including Samsung Electronics and SK Hynix, are slowing down investments in advanced NAND due to high demand uncertainty and a focus on DRAM and packaging sectors [1][2] - Samsung Electronics has been transitioning investments at its P1 and Xi'an NAND factories from 6th and 7th generation NAND to 8th and 9th generation NAND, with conversion investments being more efficient and less costly than building new production lines [1] - The conversion speed for the latest NAND technology is slowing, with the 9th generation NAND conversion at the P1 factory being delayed and the Xi'an factory's X2 production line only planning to execute a minimal scale of 5,000 wafers per month [1][2] Group 2 - A semiconductor industry insider indicated that Samsung plans to continue mass production of older generation NAND on the X2 production line until at least mid-next year due to low demand for advanced NAND [2] - Samsung has decided to postpone the application of hybrid bonding technology for V9 NAND, originally intended for the Xi'an X2 production line, with plans to start using this technology from the 10th generation NAND (V10) at the earliest by mid-next year [2] - SK Hynix is also focusing its investments on advanced DRAM and HBM, with slower R&D progress for V10 NAND compared to Samsung, leading to a cautious investment approach based on downstream demand [2]

Core Viewpoint - The article discusses the advancements in semiconductor technology, particularly in AI applications, focusing on key trends such as advanced packaging, CPO technology, and cooling solutions to address performance and efficiency challenges in AI accelerators [2][3]. Advanced Packaging Technology - Advanced packaging is evolving through Chiplet technology and hybrid bonding to enhance AI processor performance. The shift from silicon interposers to silicon bridges and organic RDL is aimed at cost reduction, with a future transition to panel-level packaging expected by 2028-2029 [4][5]. - Hybrid bonding is crucial for improving performance by reducing the bonding area through enhanced alignment precision [5]. CPO Technology - CPO (Co-Packaged Optics) is identified as the next-generation connection technology for AI data center servers, effectively reducing power consumption in high-bandwidth scenarios. However, high costs and the complexity of precise assembly remain significant challenges [6]. - The introduction of next-generation 448Gb SerDes technology may increase CPO adoption, as it addresses signal degradation issues by minimizing transmission distances [6]. Client Device Packaging - In client devices, semiconductor manufacturers are carefully selecting between Chiplet and monolithic architectures based on cost and performance considerations. For instance, AMD's latest Radeon series GPU has integrated previously Chiplet-based SRAM into a monolithic design [7]. - Apple's Vision Pro features a Chiplet package with two high-bandwidth custom DRAM chips, showcasing the trend towards specialized high-performance processors [7]. Cooling Solutions - Traditional cooling methods like air and water cooling are becoming less effective due to increasing power density in AI accelerators. Two-phase liquid cooling is emerging as a key solution due to its high energy efficiency and broad applicability [3][9]. - Different cooling technologies are suited for varying thermal densities: air cooling for below 10W/cm², two-phase liquid cooling for 10-100W/cm², and water cooling for above 100W/cm². The next-generation 3nm AI data center GPUs are expected to have thermal densities around 100W/cm², making two-phase liquid cooling particularly relevant [10][11][12].

Group 1 - The core concept of hybrid bonding technology is gaining traction among major semiconductor companies like TSMC and Samsung, as it is seen as a key to advancing packaging technology for the next decade [2][4][10] - Hybrid bonding allows for high-density, high-performance interconnections between different chips, significantly improving signal transmission speed and reducing power consumption compared to traditional methods [5][11] - The technology is particularly relevant for high bandwidth memory (HBM) products, with leading manufacturers like SK Hynix, Samsung, and Micron planning to adopt hybrid bonding in their upcoming HBM5 products to meet increasing bandwidth demands [10][12] Group 2 - TSMC's SoIC technology utilizes hybrid bonding, achieving a 15-fold increase in chip connection density compared to traditional methods, which enhances performance and reduces size [14][15] - Intel has also entered the hybrid bonding space with its 3D Foveros technology, which significantly increases the number of interconnections per square millimeter, enhancing integration capabilities [19] - SK Hynix and Samsung are actively testing and planning to implement hybrid bonding in their next-generation HBM products, with Samsung emphasizing the need for this technology to meet height restrictions in memory packaging [20][22] Group 3 - The global hybrid bonding technology market is projected to grow from $123.49 million in 2023 to $618.42 million by 2030, with a compound annual growth rate (CAGR) of 24.7%, particularly strong in the Asia-Pacific region [22]

Core Viewpoint - The article emphasizes the rapid development and industrialization of hybrid bonding technology as a key enabler for overcoming performance bottlenecks in the semiconductor industry, particularly in the post-Moore's Law era [1][12]. Group 1: Hybrid Bonding Technology Overview - Hybrid bonding technology, also known as direct bonding interconnect, is a core technology in advanced packaging, enabling high-density vertical interconnections between chips through copper-copper and dielectric bonding [3][12]. - This technology allows for interconnect distances below 1μm, significantly increasing the number of I/O contacts per unit area compared to traditional bump bonding, which has distances above 20μm [3][5]. - Advantages include improved thermal management, enhanced reliability, flexibility in 3D integration, and compatibility with existing wafer-level manufacturing processes [3][5]. Group 2: Industry Adoption and Applications - Major semiconductor companies like SK Hynix and Samsung are adopting hybrid bonding in their products, such as HBM3E and 3D DRAM, achieving significant improvements in thermal performance and chip density [5][8]. - Samsung's implementation of hybrid bonding has reduced chip area by 30% while enhancing integration [8]. - TSMC's SoIC technology and NVIDIA's GPUs also utilize hybrid bonding to improve performance and density in advanced applications [10][11]. Group 3: Market Growth and Equipment Demand - The global hybrid bonding equipment market is projected to grow from approximately $421 million in 2023 to $1.332 billion by 2030, with a compound annual growth rate (CAGR) of 30% [13]. - Equipment manufacturers are competing to meet the rising demand for high-precision bonding machines and related technologies, with companies like Applied Materials and ASMPT leading the charge [13][14]. Group 4: Competitive Landscape - Applied Materials is focusing on building a comprehensive hybrid bonding ecosystem through strategic investments and partnerships, aiming to cover the entire process from material to bonding [14][15]. - ASMPT is enhancing its position by developing high-precision bonding technologies and collaborating with industry leaders to drive standardization [17][22]. - BESI is capitalizing on the demand for AI chips and HBM packaging, with a significant market share in CIS sensors and a focus on high-precision bonding equipment [18][19]. Group 5: Future Trends and Challenges - The shift from 2D scaling to 3D integration is reshaping the competitive landscape in the semiconductor industry, with hybrid bonding technology at the forefront [22][23]. - Despite its potential, hybrid bonding faces challenges such as high costs and stringent manufacturing environment requirements, which may slow its widespread adoption [23][21].