Core Viewpoint - NVIDIA plans to upgrade its existing CoWoS technology to CoWoP solution by around 2027, which will eliminate the packaging substrate and directly install the CoW wafer-level packaged semi-finished products onto a reinforced PCB. This transition poses significant challenges in PCB wiring technology and signal transmission design [2]. Group 1: Technology Analysis - The current advanced packaging substrate L/S for CoWoS is below 10/10 microns, utilizing a semi-additive process more aligned with semiconductor manufacturing. In contrast, the PCB industry primarily employs mature subtractive processes, with high-precision PCBs typically having L/S concentrated around 75-50 microns [2]. - High-end HDI boards and SLP substrates, even with improved semi-additive processes, can only achieve a maximum L/S of 30-25 microns, which is significantly less precise than the required 10-micron ultra-fine pitch [2]. Group 2: Market Implications - Traditional PCB manufacturers may find it challenging to benefit from the CoWoP concept, but it could help IC substrate manufacturers establish a new competitive edge. The main challenge for substrate manufacturers is to increase the size of organic substrates and update equipment suppliers' products [3]. - Glass substrate developers may benefit from this transition due to superior thermal conductivity and stability compared to current PCBs and organic substrates. The primary challenge lies in controlling the graphic process during large-size production, particularly regarding fragmentation, film adhesion, and fine wiring [3]. - Current PCB large board glass substrates can achieve line width and spacing breakthroughs of 20/20 microns. If the initial CoWoP technology can utilize this precision glass packaging substrate, it would represent a significant step towards industrialization [3].

Group 1 - The company has indicated that its eSinC 2.5D packaging technology platform includes SiCS, FoCS, and BiCS, which are comparable to CoWoS technology [2] - The company does not possess CoWoP packaging technology [2]

Core Viewpoint - Morgan Stanley believes that the transition from CoWoS to CoWoP faces significant technical challenges, and the reliance on ABF substrates is unlikely to change in the short term [1][2][8] Group 1: Technical Challenges - The CoWoP technology requires PCB line/space (L/S) to be reduced to below 10/10 microns, which is significantly more challenging than the current standards of ABF substrates [5][6] - The current high-density interconnect (HDI) PCB has an L/S of 40/50 microns, and even the PCB used in iPhone motherboards only reaches 20/35 microns, making the transition to CoWoP technically difficult [5][6] Group 2: Supply Chain Risks - Transitioning from CoWoS to CoWoP could introduce significant yield risks and necessitate a reconfiguration of the supply chain, which is not commercially logical given the timeline for mass production [8] - TSMC's CoWoS yield rate is nearly 100%, making a switch to a new technology unnecessarily risky [8] Group 3: Potential Advantages of CoWoP - Despite the short-term challenges, CoWoP technology has potential advantages, including shorter signal paths, improved thermal performance suitable for >1000W GPUs, better power integrity, and addressing organic substrate capacity bottlenecks [10] - The goals of adopting CoWoP include solving substrate warping issues, increasing NVLink coverage on PCBs without additional substrates, achieving higher thermal efficiency without packaging lids, and eliminating bottlenecks in certain packaging materials [10]

Summary of Key Points from Conference Call Records Industry or Company Involved - **Semiconductor Packaging Industry**: Focus on TSMC's CoWoS technology and related companies - **RISC-V Architecture**: Development and adoption in high-performance computing - **Micro-Short Drama Industry**: Growth and government support in Shenzhen - **Brain-Computer Interface (BCI) Technology**: Medical applications and market potential - **AI in Healthcare**: Investment trends and technological advancements - **Tourism and Cruise Industry**: Summer tourism trends and company initiatives - **Robotics and AI**: Development in military and healthcare applications Core Insights and Arguments Semiconductor Packaging - TSMC is advancing its CoWoS technology, with expected Q3 sales between $31.8 billion and $33.1 billion, exceeding market estimates [2][3] - The global market for CoWoS technology is projected to exceed $10 billion by 2026, with China leading growth at 71% [2] RISC-V Architecture - The fifth RISC-V China Summit highlighted the acceleration of high-performance computing products [4] - Companies like Aojie Technology and Allwinner Technology are leading in RISC-V CPU subsystem development [5] Micro-Short Drama - Shenzhen's government has introduced measures to support the micro-short drama industry, with a market size expected to reach 68.6 billion yuan in 2025, growing at 36% [6][7] Brain-Computer Interface - The global BCI medical application market is projected to reach $40 billion by 2030, with significant growth in central nervous system disease treatments [8] - Companies like Yanshan Technology and Sanbo Brain Science are pioneering BCI applications [9] AI in Healthcare - The global AI healthcare investment landscape is heating up, with significant advancements in molecular modeling technology [11] - The company is collaborating with Tencent AI Lab to enhance drug discovery processes [11] Tourism and Cruise - The domestic summer tourism consumption is expected to reach 1.8 trillion yuan, with the company launching themed cruise lines [13] Robotics and AI - The military robotics sector is accelerating, with new developments in multifunctional robots for reconnaissance and inspection [16] - Companies are also focusing on healthcare robotics, with applications in rehabilitation and elderly care [15] Other Important but Potentially Overlooked Content - The CoWoS technology's capacity is directly linked to HBM production, indicating a critical supply chain relationship [2] - The RISC-V architecture's integration into data centers could disrupt traditional CPU markets [4] - The micro-short drama market's growth is driven by free content, highlighting a shift in consumer preferences [6] - The BCI technology's commercialization is supported by new pricing regulations in Hubei province [8] - The AI healthcare sector is seeing a convergence of technology and traditional pharmaceutical practices, enhancing drug development efficiency [11] - The cruise tourism initiative is part of a broader strategy to diversify offerings in response to changing consumer demands [13] - The military robotics market is expected to see increased government investment and interest, particularly in AI applications [16]

Core Viewpoint - The article discusses the retirement of TSMC's Vice President of R&D, Dr. Yu Zhenhua, highlighting his significant contributions to the semiconductor industry, particularly in advanced packaging technologies and the establishment of TSMC as a leader in the foundry sector [3][5][7]. Group 1: Contributions of Dr. Yu Zhenhua - Dr. Yu Zhenhua joined TSMC in 1994 and played a pivotal role in the development of advanced packaging technologies such as CoWoS and InFO, which have been crucial for TSMC's success in the semiconductor industry [3][5][9]. - He has accumulated over 190 U.S. patents and 173 Taiwanese patents, focusing on low dielectric materials and packaging integration technologies [9]. - Dr. Yu's leadership in the development of 3D chip integration and TSV technology has strengthened the Taiwanese semiconductor supply chain [9]. Group 2: Transition of Leadership - Following Dr. Yu's retirement, his responsibilities will be taken over by Xu Guojin, who has over 30 years of experience in the semiconductor industry and previously held senior positions at Micron [5][11][13]. - Xu Guojin is currently the Vice President of Integrated Interconnect & Packaging at TSMC, focusing on 3D IC and advanced packaging technologies [13]. Group 3: Historical Context and Achievements of TSMC - TSMC's rise to prominence in the semiconductor industry is attributed to key technological breakthroughs, including the 0.13-micron copper process developed in 2003, which significantly enhanced its market position [16][17]. - The article refers to the "Six Knights of TSMC," a group of key figures, including Dr. Yu, who have been instrumental in TSMC's technological advancements and overall success [15][17][22]. - TSMC's focus on advanced packaging has become a major area of growth, with the establishment of the "3D Fabric" brand for its 2.5D and 3D packaging products [25].

Core Viewpoint - The ongoing AI boom is driving advancements in semiconductor packaging technologies, particularly Fan-out Panel Level Packaging (FOPLP), which is expected to enhance chip efficiency and market competitiveness [1][2]. Group 1: Advanced Packaging Technologies - Advanced packaging integrates different chips to improve performance, reduce space, and lower power consumption, with TSMC's CoWoS technology being a notable example [1]. - FOPLP technology utilizes square substrates for IC packaging, significantly increasing usable area compared to traditional round wafers, achieving a utilization rate of 95% [1]. - The development of mid-to-high-end semiconductor packaging using 3.5 generation FOPLP glass substrates can provide an area seven times larger than that of a 12-inch glass wafer [1]. Group 2: Industry Collaboration and Development - The Ministry of Economic Affairs, in collaboration with companies like Innolux and the Industrial Technology Research Institute, has launched initiatives to promote FOPLP technology and enhance the value of existing panel production lines [1][2]. - Despite challenges in production technology, such as panel warping and yield issues, ongoing collaboration aims to reduce defects and improve manufacturing processes [2]. Group 3: Market Position and Strategy - Innolux is not competing directly with established semiconductor manufacturers but is leveraging its existing panel production capabilities to transition into advanced packaging [2][3]. - The company plans to utilize its larger glass substrates to meet the increasing demand for IC packaging, with a focus on chip-first solutions to gain market recognition [3]. - The company is committed to continuous improvement in technology and talent development in the FOPLP sector, with expectations for tangible results and shipments this year [3]. Group 4: Future Prospects and Innovations - The company is exploring various advanced technologies, including chip last and redistribution layer (RDL) techniques, while maintaining a focus on validating these technologies rather than solely on mass production [4].

如果您希望可以时常见面，欢迎标星收藏哦~ 今天，台积电在美国举办了tsmc symposium 2025，会上他们发布了一系列新技术，并对路线 图做了更新。值得一提的是，公司第二代GAA工艺14A也首次曝光。 台积电表示，A14代表了台积电业界领先的N2工艺的重大进步，旨在通过提供更快的计算速度和 更高的能效来推动人工智能（AI）转型。此外，它还有望通过提升智能手机的内置AI功能，使其 更加智能。根据台积电的规划，A14计划于2028年投产，目前开发进展顺利，良率已提前实现。 台积电指出，与即将于今年晚些时候量产的 N2 工艺相比，A14 将在相同功耗下实现高达 15% 的 速度提升，或在相同速度下降低高达 30% 的功耗，同时逻辑密度将提升 20% 以上。台积电凭借 其在纳米片晶体管设计与技术协同优化方面的经验，正在将其 TSMC NanoFlex 标准单元架构升 级为 NanoFlex Pro，从而实现更高的性能、能效和设计灵活性。 台积电董事长兼首席执行官魏哲家博士表示："我们的客户始终着眼于未来，而台积电的技术领导 力和卓越的制造能力为他们提供了可靠的创新路线图。台积电的尖端逻辑技术（例如 A14）是 ...