随着摩尔定律趋近物理极限，异构集成已成为提升芯片系统性能、功能与集成度的核心路 径。而在这一技术演进中， 玻璃基板正从一种备选材料，迅速崛起为支撑下一代高密度、高 性能、多功能集成的 "关键路径"平台 。 玻璃基板作为具备高平整度、低热膨胀系数、低介电损耗及优异机械与化学稳定性的核心半 导体关键材料，已从传统显示领域核心应用，全面拓展至先进半导体封装、 MEMS 与传感 器、AI 高性能计算、5G/6G 射频通信、光电子集成及功率半导体等领域的核心赛道。 "宁波膜智信息科技有限公司"为势银（TrendBank）唯一工商注册实体及收款账户 添加文末微信，加 电子玻璃 群 依托玻璃通孔（ TGV）等核心技术实现芯片高密度异构集成与互连升级，是后摩尔时代突破 芯片性能瓶颈、支撑半导体产业技术迭代的战略性基础材料，其应用边界与市场渗透率正持 续扩容，成为半导体材料领域的重要发展方向。 要将玻璃的理论优势转化为可靠的量产产品，传统加工技术因应力、微裂纹和精度限制而面 临挑战 ，为此势银网络研讨会有幸邀请到了来自 乐普科（上海）光电有限公司 的 EQ&WQ 部门经理 李建先生 和 RENA Technologies Gm ...

Investment Rating - The report gives a "Buy" rating for the company, indicating a positive outlook for investment [6]. Core Insights - The company is a leading manufacturer of front-end thin film deposition equipment in China, with core products including PECVD, ALD, SACVD, and HDPCVD, which are widely used in integrated circuit manufacturing and advanced packaging [9][14]. - The global thin film deposition equipment market is expected to reach $34 billion by 2025, with a CAGR of 13.3% from 2020 to 2025, driven by the continuous evolution of advanced logic processes and the increasing complexity of storage devices [6][43]. - The company has a clear layout in three-dimensional integration and is transitioning from a single deposition equipment focus to a dual-engine platform that includes both deposition and bonding technologies [6][9]. Financial Data and Profit Forecast - The company’s total revenue is projected to grow from 2,705 million yuan in 2023 to 10,817 million yuan in 2027, with a CAGR of 54.4% [5]. - The net profit attributable to the parent company is expected to increase from 663 million yuan in 2023 to 2,522 million yuan in 2027, reflecting a growth rate of 40.4% [5]. - The gross margin is forecasted to stabilize around 41.1% by 2027, after experiencing fluctuations due to new product introductions and validation costs [29]. Company and Industry Situation - The company has established a strong competitive position in the PECVD segment, which accounts for approximately 33% of the thin film deposition market value, and is the only domestic manufacturer to achieve stable mass production of PECVD equipment [47][59]. - The thin film deposition equipment is a core component of the semiconductor front-end equipment system, with a stable market share of about 22% in wafer manufacturing equipment [47]. - The company is well-positioned to benefit from the ongoing expansion of domestic wafer fabs and the trend towards domestic substitution in semiconductor equipment [6][43]. Product and Technology Development - The company’s product lineup includes advanced bonding equipment and supporting measurement devices, which have already achieved mass production in fields such as advanced storage and image sensors [19][21]. - The PECVD series products have maintained a competitive advantage, with significant production scale expansion, while ALD products have also begun to receive repeat orders due to their leading domestic process coverage [19][20]. - The company’s new product introductions, including ALD and SACVD, are expected to enhance profitability as they transition from validation to mass production [21][25].

公众号记得加星标⭐️，第一时间看推送不会错过。 几十年来，半导体技术的进步一直以不断缩小的纳米尺寸来衡量。但随着晶体管尺寸缩小速度放缓， 瓶颈已从器件转移到互连，先进封装成为新的前沿领域。采用硅通孔（TSV）的硅中介层实现了高密 度2.5D集成，缩短了信号路径，并支持远超衬底和引线键合所能提供的带宽。 下一阶段的发展趋势与直觉相反：更大的TSV（宽度可达50μm，深度可达300μm）蚀刻到更厚的中 介层中，可带来更好的电气性能、更稳定的电源传输、更佳的散热性能和更高的制造良率。 从引线键合到中介层 在TSV区域和中介层顶层的微凸点之间是重分布层（RDL）。该层包含主要的水平界面连接，用于连 接中介层顶层的元件芯片。RDL中的互连结构类似于HDI PCB中的盲孔/埋孔。 中介层通常由三种材料制成：硅、玻璃或有机衬底。中介层完全由代工厂制造（台积电是主要供应 商），包括与封装衬底和半导体芯片键合的硅通孔 (TSV) 和水平互连。中介层可以设计成两种功 能：作为有源器件或无源器件。 硅中介层的一个主要应用是将高带宽内存 (HBM) 连接到高速处理器（图 2）。每个 HBM 器件本身 都是一个由 TSV 构建的 3D ...

然而，随着芯片服务提供商加速自主研发ASIC芯片以满足更复杂的功能需求，其对封装尺寸的 要求也大幅增长。因此，一些芯片服务提供商正在考虑从台积电的CoWoS芯片转向英特尔的 EMIB芯片。 TrendForce指出，CoWoS技术通过中介层将计算逻辑、内存和I/O芯片连接起来，并将这些芯片 安 装 在 基 板 上 。 该 技 术 已 扩 展 到 包 括 CoWoS-S 、 CoWoS-R 和 CoWoS-L 。 随 着 NVIDIA 的 Blackwell平台在2025年接近量产，市场需求正迅速转向CoWoS-L，因为它将硅中介层集成到了 封装中。预计随着NVIDIA即将推出的Rubin架构的推出，这一趋势还将继续，Rubin架构将采用 更大的光罩尺寸。 人工智能/高性能计算需求的增长导致了CoWoS技术的重大瓶颈，包括产能短缺、光罩尺寸限制 和制造成本上升。TrendForce观察到，大部分CoWoS产能已被NVIDIA GPU占用，其他客户的 选择十分有限。 此外，对更大封装尺寸的需求不断增长以及美国本地化要求，促使谷歌和 Meta 等北美主要 CSP 与英特尔合作，共同采用 EMIB。 英特尔的EMIB ...

如果您希望可以时常见面，欢迎标星收藏哦~ 半导体激光设备概述 激光凭借高能量密度、非接触加工以及对材料适应性强等优势，被广泛应用于消费电子、汽车制 造、新能源和半导体产业链等领域。随着半导体制造和封装工艺的发展，激光设备在半导体行业中 发挥越来越重要的作用。近年来，随着下游行业对轻量化、精密化和智能化需求的不断增加，半导 体激光加工设备正加快迭代升级。从传统的二极管泵浦到光纤耦合、超快激光技术，设备在功率稳 定性、加工精度和能耗表现上均显著提升。与此同时，国产厂商也在技术突破和成本控制方面不断 追赶，逐步缩小与国际领先企业的差距。可以预见，未来半导体激光设备将不仅是单一制造环节的 工具，而是成为驱动制造业转型升级的重要引擎。在新兴产业快速发展的背景下，其市场需求有望 持续扩大，带动产业链迎来新的增长机遇。 目前根据应用原理和应用工艺环节的不同，可将半导体激光设备分为应用于前道制程的激光退火设 备、激光材料改性设备和应用于硅片和后道制程的激光打标设备、激光划片设备、解键合设备和修 边（Trimming）设备等。 1.1 激光退火设备 半导体激光退火设备是一种半导体制造工艺中的关键设备，主要用于对半导体晶圆进行退 ...

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has received acceptance for its IPO on the Sci-Tech Innovation Board, indicating a significant step in its growth trajectory in the semiconductor industry [3]. Company Overview - Shenghe Jingwei is an advanced packaging and testing enterprise for integrated circuits, focusing on 12-inch silicon wafer processing and providing wafer-level packaging (WLP) and multi-chip integration packaging services [3]. - The company aims to support high-performance chips, particularly GPUs, CPUs, and AI chips, through heterogeneous integration methods that enhance performance metrics such as computing power, bandwidth, and energy efficiency [3]. Financial Performance - The company reported revenues of 1.633 billion yuan, 3.038 billion yuan, and 4.705 billion yuan for the years 2022, 2023, and 2024 respectively, with a projected revenue of 3.178 billion yuan for the first half of 2025 [3]. - Net profits for the same periods were -329 million yuan, 34.13 million yuan, 214 million yuan, and 43.5 million yuan for the first half of 2025 [3]. Market Position - According to Gartner, Shenghe Jingwei is projected to be the 10th largest packaging and testing company globally and the 4th largest domestically by 2024, with the highest compound annual growth rate in revenue among the top ten companies from 2022 to 2024 [3]. Shareholding Structure - As of the date of the prospectus, the largest shareholder is Wuxi Chanfang Fund with a 10.89% stake, followed by a group of shareholders from the China Merchants Bank system with a combined 9.95% [4]. - The company has no controlling shareholder or actual controller, ensuring a dispersed shareholding structure where no single shareholder can dominate the shareholder meetings [5].

Core Insights - Shenghe Jingwei's application for listing on the Sci-Tech Innovation Board has been accepted, marking a significant step in the ongoing trend of semiconductor companies going public in China [1] - Shenghe Jingwei is a leading global provider of advanced packaging services for integrated circuits, focusing on high-performance chips such as GPUs, CPUs, and AI chips, with a strong technological platform in the 2.5D integration field [2] - Since 2020, Shangfeng has invested over 2 billion yuan in more than 20 semiconductor companies, with a significant portion of these companies either in the listing process or already listed, showcasing its strategic focus on the semiconductor sector [3] Company Overview - Shenghe Jingwei specializes in advanced wafer-level packaging and multi-chip integration packaging, aiming to enhance performance metrics like computing power, bandwidth, and energy efficiency [2] - The company is recognized as one of the earliest and largest producers of 2.5D integration technology in mainland China, achieving a market share of approximately 85% in this segment for 2024 [2] Investment Strategy - Shangfeng's investment in Shenghe Jingwei amounted to 150 million yuan, part of a broader strategy to strengthen its competitive edge in the semiconductor industry [3] - The company has focused on investing in sectors that address critical technology gaps, with a significant portion of its investments directed towards semiconductor and new materials companies [3] - Over 60% of the invested companies are either in the process of applying for listing or have already gone public, indicating a successful investment strategy that enhances financial returns and industry influence [3]

Core Viewpoint - The company, through its wholly-owned subsidiary Ningbo Shangrong Logistics Co., Ltd., has established a private equity investment fund to invest in Shenghe Jingwei Semiconductor Co., Ltd., which has applied for an IPO on the Sci-Tech Innovation Board [1] Group 1: Company Overview - Shenghe Jingwei is a leading global advanced packaging and testing enterprise for integrated circuits, focusing on advanced 12-inch silicon wafer processing [1] - The company provides a full range of advanced packaging and testing services, including wafer-level packaging (WLP) and chiplet multi-chip integration packaging [1] Group 2: Industry Focus - Shenghe Jingwei aims to support various high-performance chips, particularly graphics processing units (GPUs), central processing units (CPUs), and artificial intelligence chips [1] - The company emphasizes performance enhancement through heterogeneous integration methods that exceed Moore's Law, achieving high computing power, high bandwidth, and low power consumption [1]

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has submitted its IPO application to the Shanghai Stock Exchange's Sci-Tech Innovation Board, aiming to raise 4.8 billion yuan, positioning itself as a leading advanced packaging and testing enterprise in the integrated circuit industry [1] Group 1: Company Overview - Shenghe Jingwei specializes in advanced packaging and testing services for integrated circuits, focusing on high-performance chips such as GPUs, CPUs, and AI chips, utilizing heterogeneous integration methods to enhance performance metrics like computing power, bandwidth, and energy efficiency [1][3] - The company is recognized as one of the earliest and largest players in the multi-chip integration packaging sector in mainland China, with capabilities to compete with global leaders [1][3] Group 2: Technological Advancements - In the mid-sized silicon wafer processing sector, Shenghe Jingwei is one of the first companies in mainland China to achieve mass production of 12-inch bumping technology and is the first to offer 14nm advanced process bumping services, filling a gap in the high-end integrated circuit manufacturing supply chain [2] - The company has achieved significant advancements in 12-inch wafer-level chip packaging (WLCSP), leading the market with a 31% share in 2024 [2][4] Group 3: Market Position - Shenghe Jingwei holds the largest 12-inch bumping capacity in mainland China and ranks first in revenue for both 12-inch WLCSP and 2.5D integration packaging, with market shares of approximately 31% and 85% respectively in 2024 [2][4][3] - The company is projected to be the tenth largest advanced packaging and testing enterprise globally and the fourth largest in mainland China by revenue in 2024, with a compound annual growth rate leading among the top ten global firms from 2022 to 2024 [3] Group 4: Financial Performance - The company reported revenues of approximately 1.633 billion yuan, 3.038 billion yuan, and 4.705 billion yuan for the years 2022, 2023, and 2024 respectively, with a projected revenue of 3.178 billion yuan for the first half of 2025 [5] - Net profits for the same periods were approximately -329 million yuan, 34.13 million yuan, and 214 million yuan, with a forecast of 43.5 million yuan for the first half of 2025 [5][6] Group 5: Fund Utilization - The funds raised from the IPO will be allocated to projects including a three-dimensional multi-chip integration packaging project with a total investment of 8.4 billion yuan, of which 4 billion yuan will come from the IPO proceeds [5]

Core Insights - The SRC has released the Microelectronics and Advanced Packaging Technology (MAPT) Roadmap 2.0, which is a comprehensive update to the industry's first 3D semiconductor roadmap [1] - The roadmap emphasizes the exponential growth in data volume required for information and communication technology (ICT), highlighting the limitations of traditional semiconductor technologies and the urgent need for heterogeneous integration (HI) to enhance system performance and energy efficiency [1][2] Group 1: System Integration and Design Challenges - Different applications require specific architectures and system integration strategies to effectively balance performance, power, area, and cost (PPAC) while ensuring signal integrity, power conversion, thermal management, reliability, and security [2][3] - The challenges of system integration extend beyond chip packaging to include material selection, interconnect scaling, and thermal management solutions, all of which must meet reliability and yield targets [3] - The transition to 2.5D/3D heterogeneous integration is crucial for achieving significant performance and cost advantages in future ICT systems [5] Group 2: Heterogeneous Integration (HI) and Chiplet Design - Chiplets and their signaling interfaces introduce a new silicon module to the microelectronics ecosystem, offering high bandwidth, area efficiency, and low cost, necessitating design capabilities for defining physical cores and chip-to-chip interfaces [7] - Design Space Exploration (DSE) utilizes analytical models and AI-assisted technologies to rapidly evaluate HI system designs, becoming increasingly important as HI system integration scales [8] - Close collaboration between chiplet and packaging design throughout the design cycle is essential, requiring early involvement of system architects to analyze system and packaging trade-offs [9] Group 3: Testing, Reliability, and Security - Future heterogeneous systems will require modular testing solutions to address the unique electrical, mechanical, and thermal characteristics of various components, balancing coverage, complexity, and cost [10] - As multi-chip system-level packaging (SiP) becomes more complex, security considerations must be integrated into design automation tools to mitigate potential threats from untrusted components and external attacks [11][12] Group 4: Advanced Packaging and Interconnect Technologies - The demand for more efficient, scalable, and high-performance solutions is driving innovations in heterogeneous integration and advanced packaging technologies, which are critical for high-performance computing, AI, and edge computing applications [14] - Key advancements in interconnect technologies include the development of through-silicon vias (TSVs), intermediate layers, and hybrid bonding methods, which are essential for enhancing performance, increasing data bandwidth, and reducing energy consumption [14][15] - The exploration of photonic interconnect technologies aims to overcome the limitations of electrical connections, providing low-latency, high-throughput connections for high-bandwidth and long-distance communication [17] Group 5: Power Delivery and Thermal Management - Integrated Voltage Regulators (IVRs) are becoming key solutions for addressing power delivery challenges, particularly as processor power levels continue to rise, especially in data center CPUs and GPUs [25] - The increasing complexity of power delivery networks necessitates the development of robust platform-level voltage regulators to efficiently distribute power across integrated voltage regulators on the chip [25][26] - Advanced packaging and heterogeneous integration face significant thermal management challenges due to rising power densities and the need for effective cooling solutions, including embedded cooling structures [29][30] Group 6: Material Innovations and Future Directions - The transition from traditional substrates to integrated platforms requires new materials and processing techniques to enhance system-level performance, particularly in high-performance computing and electrification applications [34][36] - Future developments in high-density substrate technologies will focus on achieving finer bump pitches and higher routing densities to meet the demands of advanced applications [42][43] - The need for innovative solutions in RF devices and systems, particularly those operating at frequencies above 6 GHz, is driving the demand for new materials, structures, and assembly techniques [44][45]