Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has received acceptance for its IPO on the Sci-Tech Innovation Board, indicating a significant step in its growth trajectory in the semiconductor industry [3]. Company Overview - Shenghe Jingwei is an advanced packaging and testing enterprise for integrated circuits, focusing on 12-inch silicon wafer processing and providing wafer-level packaging (WLP) and multi-chip integration packaging services [3]. - The company aims to support high-performance chips, particularly GPUs, CPUs, and AI chips, through heterogeneous integration methods that enhance performance metrics such as computing power, bandwidth, and energy efficiency [3]. Financial Performance - The company reported revenues of 1.633 billion yuan, 3.038 billion yuan, and 4.705 billion yuan for the years 2022, 2023, and 2024 respectively, with a projected revenue of 3.178 billion yuan for the first half of 2025 [3]. - Net profits for the same periods were -329 million yuan, 34.13 million yuan, 214 million yuan, and 43.5 million yuan for the first half of 2025 [3]. Market Position - According to Gartner, Shenghe Jingwei is projected to be the 10th largest packaging and testing company globally and the 4th largest domestically by 2024, with the highest compound annual growth rate in revenue among the top ten companies from 2022 to 2024 [3]. Shareholding Structure - As of the date of the prospectus, the largest shareholder is Wuxi Chanfang Fund with a 10.89% stake, followed by a group of shareholders from the China Merchants Bank system with a combined 9.95% [4]. - The company has no controlling shareholder or actual controller, ensuring a dispersed shareholding structure where no single shareholder can dominate the shareholder meetings [5].

Core Insights - Shenghe Jingwei's application for listing on the Sci-Tech Innovation Board has been accepted, marking a significant step in the ongoing trend of semiconductor companies going public in China [1] - Shenghe Jingwei is a leading global provider of advanced packaging services for integrated circuits, focusing on high-performance chips such as GPUs, CPUs, and AI chips, with a strong technological platform in the 2.5D integration field [2] - Since 2020, Shangfeng has invested over 2 billion yuan in more than 20 semiconductor companies, with a significant portion of these companies either in the listing process or already listed, showcasing its strategic focus on the semiconductor sector [3] Company Overview - Shenghe Jingwei specializes in advanced wafer-level packaging and multi-chip integration packaging, aiming to enhance performance metrics like computing power, bandwidth, and energy efficiency [2] - The company is recognized as one of the earliest and largest producers of 2.5D integration technology in mainland China, achieving a market share of approximately 85% in this segment for 2024 [2] Investment Strategy - Shangfeng's investment in Shenghe Jingwei amounted to 150 million yuan, part of a broader strategy to strengthen its competitive edge in the semiconductor industry [3] - The company has focused on investing in sectors that address critical technology gaps, with a significant portion of its investments directed towards semiconductor and new materials companies [3] - Over 60% of the invested companies are either in the process of applying for listing or have already gone public, indicating a successful investment strategy that enhances financial returns and industry influence [3]

Core Viewpoint - The company, through its wholly-owned subsidiary Ningbo Shangrong Logistics Co., Ltd., has established a private equity investment fund to invest in Shenghe Jingwei Semiconductor Co., Ltd., which has applied for an IPO on the Sci-Tech Innovation Board [1] Group 1: Company Overview - Shenghe Jingwei is a leading global advanced packaging and testing enterprise for integrated circuits, focusing on advanced 12-inch silicon wafer processing [1] - The company provides a full range of advanced packaging and testing services, including wafer-level packaging (WLP) and chiplet multi-chip integration packaging [1] Group 2: Industry Focus - Shenghe Jingwei aims to support various high-performance chips, particularly graphics processing units (GPUs), central processing units (CPUs), and artificial intelligence chips [1] - The company emphasizes performance enhancement through heterogeneous integration methods that exceed Moore's Law, achieving high computing power, high bandwidth, and low power consumption [1]

Core Viewpoint - Shenghe Jingwei Semiconductor Co., Ltd. has submitted its IPO application to the Shanghai Stock Exchange's Sci-Tech Innovation Board, aiming to raise 4.8 billion yuan, positioning itself as a leading advanced packaging and testing enterprise in the integrated circuit industry [1] Group 1: Company Overview - Shenghe Jingwei specializes in advanced packaging and testing services for integrated circuits, focusing on high-performance chips such as GPUs, CPUs, and AI chips, utilizing heterogeneous integration methods to enhance performance metrics like computing power, bandwidth, and energy efficiency [1][3] - The company is recognized as one of the earliest and largest players in the multi-chip integration packaging sector in mainland China, with capabilities to compete with global leaders [1][3] Group 2: Technological Advancements - In the mid-sized silicon wafer processing sector, Shenghe Jingwei is one of the first companies in mainland China to achieve mass production of 12-inch bumping technology and is the first to offer 14nm advanced process bumping services, filling a gap in the high-end integrated circuit manufacturing supply chain [2] - The company has achieved significant advancements in 12-inch wafer-level chip packaging (WLCSP), leading the market with a 31% share in 2024 [2][4] Group 3: Market Position - Shenghe Jingwei holds the largest 12-inch bumping capacity in mainland China and ranks first in revenue for both 12-inch WLCSP and 2.5D integration packaging, with market shares of approximately 31% and 85% respectively in 2024 [2][4][3] - The company is projected to be the tenth largest advanced packaging and testing enterprise globally and the fourth largest in mainland China by revenue in 2024, with a compound annual growth rate leading among the top ten global firms from 2022 to 2024 [3] Group 4: Financial Performance - The company reported revenues of approximately 1.633 billion yuan, 3.038 billion yuan, and 4.705 billion yuan for the years 2022, 2023, and 2024 respectively, with a projected revenue of 3.178 billion yuan for the first half of 2025 [5] - Net profits for the same periods were approximately -329 million yuan, 34.13 million yuan, and 214 million yuan, with a forecast of 43.5 million yuan for the first half of 2025 [5][6] Group 5: Fund Utilization - The funds raised from the IPO will be allocated to projects including a three-dimensional multi-chip integration packaging project with a total investment of 8.4 billion yuan, of which 4 billion yuan will come from the IPO proceeds [5]

Core Insights - The SRC has released the Microelectronics and Advanced Packaging Technology (MAPT) Roadmap 2.0, which is a comprehensive update to the industry's first 3D semiconductor roadmap [1] - The roadmap emphasizes the exponential growth in data volume required for information and communication technology (ICT), highlighting the limitations of traditional semiconductor technologies and the urgent need for heterogeneous integration (HI) to enhance system performance and energy efficiency [1][2] Group 1: System Integration and Design Challenges - Different applications require specific architectures and system integration strategies to effectively balance performance, power, area, and cost (PPAC) while ensuring signal integrity, power conversion, thermal management, reliability, and security [2][3] - The challenges of system integration extend beyond chip packaging to include material selection, interconnect scaling, and thermal management solutions, all of which must meet reliability and yield targets [3] - The transition to 2.5D/3D heterogeneous integration is crucial for achieving significant performance and cost advantages in future ICT systems [5] Group 2: Heterogeneous Integration (HI) and Chiplet Design - Chiplets and their signaling interfaces introduce a new silicon module to the microelectronics ecosystem, offering high bandwidth, area efficiency, and low cost, necessitating design capabilities for defining physical cores and chip-to-chip interfaces [7] - Design Space Exploration (DSE) utilizes analytical models and AI-assisted technologies to rapidly evaluate HI system designs, becoming increasingly important as HI system integration scales [8] - Close collaboration between chiplet and packaging design throughout the design cycle is essential, requiring early involvement of system architects to analyze system and packaging trade-offs [9] Group 3: Testing, Reliability, and Security - Future heterogeneous systems will require modular testing solutions to address the unique electrical, mechanical, and thermal characteristics of various components, balancing coverage, complexity, and cost [10] - As multi-chip system-level packaging (SiP) becomes more complex, security considerations must be integrated into design automation tools to mitigate potential threats from untrusted components and external attacks [11][12] Group 4: Advanced Packaging and Interconnect Technologies - The demand for more efficient, scalable, and high-performance solutions is driving innovations in heterogeneous integration and advanced packaging technologies, which are critical for high-performance computing, AI, and edge computing applications [14] - Key advancements in interconnect technologies include the development of through-silicon vias (TSVs), intermediate layers, and hybrid bonding methods, which are essential for enhancing performance, increasing data bandwidth, and reducing energy consumption [14][15] - The exploration of photonic interconnect technologies aims to overcome the limitations of electrical connections, providing low-latency, high-throughput connections for high-bandwidth and long-distance communication [17] Group 5: Power Delivery and Thermal Management - Integrated Voltage Regulators (IVRs) are becoming key solutions for addressing power delivery challenges, particularly as processor power levels continue to rise, especially in data center CPUs and GPUs [25] - The increasing complexity of power delivery networks necessitates the development of robust platform-level voltage regulators to efficiently distribute power across integrated voltage regulators on the chip [25][26] - Advanced packaging and heterogeneous integration face significant thermal management challenges due to rising power densities and the need for effective cooling solutions, including embedded cooling structures [29][30] Group 6: Material Innovations and Future Directions - The transition from traditional substrates to integrated platforms requires new materials and processing techniques to enhance system-level performance, particularly in high-performance computing and electrification applications [34][36] - Future developments in high-density substrate technologies will focus on achieving finer bump pitches and higher routing densities to meet the demands of advanced applications [42][43] - The need for innovative solutions in RF devices and systems, particularly those operating at frequencies above 6 GHz, is driving the demand for new materials, structures, and assembly techniques [44][45]

Core Viewpoint - The article highlights the launch of the third Integrated Chip and Chiplet Conference, showcasing North Polar Xiongxin's innovative shelf chiplet solutions aimed at reducing costs and enhancing efficiency in high-end chip production, while addressing the industry's growing demand for flexible and adaptable technologies [1][6]. Group 1: Product Innovations - North Polar Xiongxin introduced a "function decoupling, flexible integration" shelf chiplet solution, combining a general-purpose HUB Chiplet with functional Chiplets to overcome traditional ASIC SoC development challenges such as long cycles, high costs, and significant risks [3][6]. - The HUB Chiplet features a 12-core ARM Cortex A72 CPU, PCIe 5.0 support, and high-speed interconnect capabilities, while the functional Chiplets cover GPU and NPU categories, with GPU chiplets offering 1.3 TFLOPS computing power and NPU chiplets achieving 50 TOPS [3][4]. Group 2: Technical Advancements - The PB-Link automotive-grade chiplet interface developed by North Polar Xiongxin supports 8 channels at 32 Gbps transmission bandwidth, with a bit error rate of less than 10^-15, and is compatible with various packaging technologies [4][11]. - The company has validated multiple packaging solutions, including configurations like 1-to-6 and 4-to-10, achieving over 90% efficiency in large model runs, thus ensuring robust application stability [5][13]. Group 3: Market Positioning - The global integrated circuit industry is shifting from "size reduction" to "heterogeneous integration," with chiplet technology being pivotal in addressing high-end chip development bottlenecks [6]. - North Polar Xiongxin aims to build a collaborative ecosystem among IC designers, IP providers, and packaging companies, allowing for the direct procurement of standardized IP chips and customized solutions without the need for repeated investments [6][19]. Group 4: Future Developments - The company plans to launch the world's only HUB+FPGA prototype verification platform in December, which integrates a 12-core ARM Cortex A72 processor and an 80 TOPS high-performance reconfigurable co-accelerator, providing comprehensive support from solution validation to mass production [5][14]. - North Polar Xiongxin's shelf chiplet solutions are expected to significantly reduce traditional chip development NRE costs to one-fifth or one-tenth, thereby shortening product time-to-market and lowering innovation barriers for enterprises [5][19].

Core Viewpoint - The article discusses the evolution of semiconductor technology, highlighting the shift from Moore's Law to chiplet technology as a solution to the challenges faced in semiconductor manufacturing [2][5]. Summary by Sections Moore's Law and Its Challenges - Moore's Law, proposed by Gordon Moore in 1965, states that the number of transistors on a semiconductor chip doubles approximately every two years, driving performance improvements and cost reductions [2]. - Recent advancements in chip manufacturing have faced physical limits, increased complexity, and rising costs, leading to a belief that Moore's Law may no longer be applicable [2]. Introduction of Chiplets - Chiplets are small chips that perform specific functions and can be combined into a single package, improving manufacturing yield and efficiency by allowing the use of "known good die" [2]. - This technology allows for the integration of different types of circuits, enhancing performance while maintaining cost-effectiveness, particularly in high-performance computing and automotive applications [3]. Heterogeneous Integration - Heterogeneous integration enables the combination of chips made with different processes and functionalities into a single package, which is particularly beneficial for the automotive industry [3]. - Major automotive manufacturers are exploring chiplet technology for future vehicle systems, aiming for mass production post-2030 [3]. Advantages Beyond Automotive - Chiplet technology is expanding into artificial intelligence and telecommunications, driving innovation across various industries [5]. - The technology relies on an intermediary layer that connects chips, enhancing communication speed and efficiency [5]. Advanced Packaging Techniques - The mainstream method for chiplet integration is 2.5D integration, while the next significant advancement is 3D integration, which stacks chips vertically for higher density [5][8]. - Combining flexible chip designs with 3D integration allows for faster, smaller, and more energy-efficient semiconductors, crucial for high-performance applications [7]. Challenges and Innovations - Vertical stacking of chips presents challenges such as heat management and maintaining high manufacturing yields, prompting research into advanced packaging technologies [8]. - The combination of chiplets and 3D integration is viewed as a disruptive innovation that could lead the semiconductor industry into a new era, potentially replacing Moore's Law [8].

Summary of Key Points from the Conference Call Industry and Company Overview - The discussion centers around the semiconductor industry, particularly focusing on advanced packaging technologies and the role of Silicon Carbide (SiC) in AI chip design and manufacturing. Key players mentioned include TSMC, NVIDIA, AMD, Google, and AWS, with a specific emphasis on TSMC's strategies and innovations in packaging solutions [1][2][3]. Core Insights and Arguments 1. **Challenges in AI Chip Design**: The increasing complexity and power demands of AI chips have led to significant challenges in power delivery networks (PDNs) and thermal management. Traditional methods are becoming inadequate, with single GPUs now requiring over 1000A of current [5][19]. 2. **Innovative Solutions**: Companies like Marvell and ASE are proposing solutions such as Package-Integrated Voltage Regulators (PIVR) and optimized PDN platforms to address these challenges. TSMC is also innovating with its CoWoS-L platform, which integrates embedded voltage regulators and advanced thermal management techniques [7][10][11]. 3. **Emergence of SiC**: SiC is highlighted as a critical material for AI chip and system design due to its superior properties, including high thermal conductivity and mechanical strength. It is increasingly being viewed as essential for advanced packaging and heterogeneous integration [13][14][16]. 4. **Market Demand**: The demand for ultra-large-scale GPUs and ASICs is driven by generative AI and large-scale model training, with power consumption often exceeding 1 kW. This has exposed bottlenecks in thermal management and power delivery [19][20]. 5. **Bottlenecks Identified**: The exponential growth in AI computing has revealed three critical bottlenecks: thermal challenges, power delivery bottlenecks, and electro-optical integration demands. TSMC is actively addressing these through its 3DFabric strategy and various packaging solutions [22][28][30][32]. Additional Important Content 1. **SiC's Role in Advanced Packaging**: SiC is positioned as a hybrid integration enabler, linking power delivery, thermal dissipation, and optical interconnects. Its unique properties make it suitable for high-voltage integrated circuits (HVICs) and optical interposers [40][44]. 2. **Competitive Landscape**: TSMC's exploration of SiC as an interposer material could provide a competitive edge in thermal management and electro-optical integration, especially compared to Intel and Samsung, who are also advancing their own technologies [45][46]. 3. **Challenges Ahead**: The successful commercialization of SiC in advanced packaging faces challenges such as defect density control in large-size wafers, process compatibility, and cost structure improvements [53][54]. 4. **Future Directions**: The integration of SiC into TSMC's platforms like COUPE and CoWoS-Next could reshape the AI semiconductor supply chain, establishing new industrial advantages in the AI and high-performance computing (HPC) era [44][97]. This summary encapsulates the critical insights and developments discussed in the conference call, emphasizing the strategic importance of SiC in the evolving semiconductor landscape.

Core Viewpoint - The interposer has transitioned from a supporting role to a focal point in the semiconductor industry, with major companies like Resonac and NVIDIA leading initiatives to develop advanced interposer technologies [1][28]. Group 1: Definition and Importance of Interposer - Interposer serves as a critical layer between chips and packaging substrates, enabling high-density interconnections and efficient integration of various chiplets into a system-in-package (SiP) [3][5]. - The interposer is essential for achieving higher bandwidth, lower latency, and increased computational density in advanced packaging [3][5]. Group 2: Types of Interposers - Two main types of interposers are currently in production: Silicon Interposer (inorganic) and Organic Interposer (Redistribution Layer) [5][6]. - Silicon Interposer has been established since the late 2000s, with TSMC pioneering its use in high-performance computing [6]. - Organic Interposer is gaining traction due to its lower production costs and flexibility, despite challenges in wiring precision and reliability [6][23]. Group 3: JOINT3 Alliance - The JOINT3 alliance, led by Resonac, consists of 27 global companies aiming to develop next-generation semiconductor packaging, focusing on panel-level organic interposers [8][11]. - The alliance plans to establish a dedicated center in Japan for advanced organic interposer development, targeting a significant increase in production efficiency and cost reduction [11][12]. - The shift to organic interposers is driven by the limitations of silicon interposers, particularly in terms of geometric losses and production costs [11][12]. Group 4: SiC Interposer as a New Direction - NVIDIA is exploring the use of Silicon Carbide (SiC) interposers for its next-generation GPUs, indicating a potential shift in materials used for interposers [17][19]. - SiC offers superior thermal conductivity and electrical insulation, making it suitable for high-performance AI and HPC applications, although manufacturing challenges remain [19][25]. Group 5: Competitive Landscape of Interposer Materials - The competition among silicon, organic, and SiC interposers is characterized by their respective advantages and disadvantages, influencing performance, cost, and scalability [20][22][23]. - Silicon interposers are currently dominant but face challenges as chip sizes increase, while organic interposers are expected to gain market share due to cost advantages [22][26]. - SiC interposers, if successfully developed, could become the standard for cutting-edge AI and HPC packaging in the long term [26]. Group 6: Future Trends - In the short term, silicon interposers will remain the market leader, while organic interposers are anticipated to see widespread adoption in the mid-term due to their cost and scalability benefits [26]. - Long-term projections suggest that SiC interposers may emerge as the preferred choice for advanced packaging once manufacturing hurdles are overcome [26].

Core Insights - The semiconductor packaging and testing technology has become a crucial element in overcoming the dual challenges of "physical limits" and "industrial chain disruptions" in the context of the global semiconductor industry's rapid transformation and geopolitical tensions [1] Group 1: Industry Trends - The advanced packaging sector is seen as a core pathway to continue Moore's Law, with technologies such as 2.5D/3D, Chiplet, and Fan-Out accelerating the integration of design and manufacturing [1] - The geopolitical landscape is reshaping supply chains, necessitating a dual approach of self-sufficiency and globalization for China's packaging industry [1] Group 2: Regional Developments - Jiangsu province, holding nearly half of the national packaging capacity, has become a significant hub for the semiconductor packaging industry, with the Yangtze River Delta region accounting for over 81% of the national total [2] - By 2024, Jiangsu's packaging revenue is projected to exceed 170 billion yuan, with key enterprises achieving breakthroughs in system-level packaging and 2.5D packaging technologies [2] Group 3: Market Dynamics - The domestic integrated circuit industry has seen a continuous increase in prosperity, with sales reaching 1,045.8 billion yuan, a year-on-year growth of 18% [3] - The advanced packaging market is growing at a rate that outpaces traditional packaging, driven by the demand for high-density, diversified, and miniaturized packaging solutions [3]