公众号记得加星标⭐️，第一时间看推送不会错过。 来源：内容综合自ADI 。 总 部 位 于 美 国 的 全 球 半 导 体 制 造 公 司 ADI 公 司 宣 布 推 出 其 首 个 企 业 风 险 投 资 基 金 ， 名 为 ADVentures (ADV)。 该基金将专注于在全球范围内寻找并投资那些在先进系统和机器人技术、气候与能源以及人类健康领 域开发开创性解决方案的早期初创企业。其他关注领域包括新型传感模式、计算架构、安全连接和人 工智能。 ADI 公 司 副 总 裁 兼 战 略 主 管 Stephanie Sidelko 在 宣 布 成 立 该 基 金 的 新 闻 稿 中 表 示 ： " 通 过 ADVentures，ADI将继续确保当今的创新者始终领先于一切可能。通过将我们数十年的专业知识与 新兴初创企业的大胆构想相结合，ADV将有助于加速应对世界上最棘手、最复杂、最紧迫挑战的变 革性解决方案。" CVC 部门将由 Kimberly Blakemore 领导，她曾担任 ADI 公司气候技术战略总监。 ADI公司推出新的企业风险投资基金ADVentures ADI公司（ADI）今天宣布推出 ADVe ...

Core Viewpoint - The article highlights the launch of the ALPIX-Maloja event sensor by AlpsenTek, emphasizing its competitive advantages in low power consumption, low latency, and cost-effectiveness for edge AI applications in various sectors such as smart home appliances and real-time monitoring [1][4]. Product Features - ALPIX-Maloja is designed for AI smart terminals, meeting the demands for ultra-low power, low computing requirements, and privacy protection [4]. - The sensor boasts a high frame rate of 1000 fps, a wide dynamic range of 120 dB, and a low power consumption of less than 4 mW at 1000 fps, making it suitable for edge visual systems [4]. - It has a resolution of 256 × 256 with a pixel size of 20 μm × 20 μm, enabling it to perform well in complex lighting conditions while reducing costs [4]. Key Advantages 1. **Basic Advantages of Pure Event Cameras**: - Ultra-low power consumption: less than 4 mW at 1000 fps, supporting always-on applications [4]. - High sensitivity in low light conditions, maintaining low latency for motion and human detection [4][10]. - Capable of high-speed output of motion characteristics in complex lighting environments [6]. - Reduced redundant data volume, only 10-20% of traditional image sensors, making it compatible with low-power MCUs [8]. 2. **New IN-PULSE DiADC Architecture**: - Integrates sensing, storage, and computation within a single pixel unit, enhancing performance and reducing power consumption [9]. - The design minimizes signal transmission paths, lowering external noise impact and improving sensor stability [9]. - Larger pixels increase light sensitivity and reduce noise, simplifying design and enhancing flexibility [9]. Typical Use Cases - **Consumer Electronics**: Applications in AI-PCs, tablets, gaming consoles, and smart screens for gesture recognition and pose detection [12]. - **Healthcare Monitoring**: Devices for fall detection and posture monitoring in homes and medical institutions, providing low-intrusion, high-privacy solutions [14]. - **Smart Home Appliances**: Integration in devices like TVs, air conditioners, and smart beds for presence detection and touchless control [15]. - **Smart Hardware**: Used in pet cameras and robotic vacuums for low-power, high-sensitivity motion detection [17]. - **Smart Business and Transportation**: Lightweight, non-intrusive solutions for counting people in malls and buses [19]. - **Always-On Sensing**: Providing ultra-low power, always-on monitoring systems [20]. Market Positioning - AlpsenTek positions ALPIX-Maloja as a competitive and cost-effective visual sensor, aiming to adapt to the evolving trends in machine vision from "seeing" to "sensing" [9].

公众号记得加星标⭐️，第一时间看推送不会错过。 来源：内容 编译自 tomshardware 。 近年来，AI GPU 的功耗稳步上升，预计随着 AI 处理器集成更多计算能力和 HBM 芯片，功耗还将 继 续 上 升 。 我 们 一 些 业 内 人 士 表 示 ， Nvidia 计 划 将 其 下 一 代 GPU 的 热 设 计 功 耗 (TDP) 设 定 在 6,000 瓦至 9,000 瓦之间，但韩国领先的研究机构 KAIST 的专家认为，未来 10 年，AI GPU 的热 设计功耗 (TDP) 将一路飙升至 15,360 瓦。因此，它们需要相当极端的冷却方法，包括浸入式冷却甚 至嵌入式冷却。 直到最近，高性能风冷系统（包括铜散热器和高压风扇）足以冷却 Nvidia 的 H100 AI 处理器。然 而，随着 Nvidia 的 Blackwell 将其散热功率提升至 1200W，Blackwell Ultra 又将其 TDP 提升至 1400W，液冷解决方案几乎成为必需。Rubin 的散热性能将进一步提升，TDP 将提升至 1800W；而 Rubin Ultra 的 GPU 芯片和 HBM 模块数量将翻倍， ...

Core Viewpoint - AMD's CDNA 4 architecture represents a moderate update over CDNA 3, focusing on enhancing matrix multiplication performance for low-precision data types, which are crucial for machine learning workloads [2][26]. Architecture Overview - CDNA 4 maintains a similar system-level architecture to CDNA 3, utilizing a large chiplet setup with eight compute dies (XCD) and a memory-side cache of 256 MB [4][20]. - The architecture employs AMD's Infinity Fabric technology for consistent memory access across multiple chips [4]. Performance Comparison - The MI355X GPU, based on CDNA 4, features a clock speed of 2.4 GHz and 256 cores, compared to MI300X's 304 cores at 2.1 GHz, indicating a slight reduction in core count but improved clock speed [5]. - MI355X offers 288 GB of HBM3E memory with a bandwidth of 8 TB/s, surpassing Nvidia's B200, which has a maximum capacity of 180 GB and bandwidth of 7.7 TB/s [25]. Matrix and Vector Throughput - CDNA 4 has rebalanced execution units to focus on low-precision matrix multiplication, doubling matrix throughput per compute unit (CU) in many cases [6][39]. - The architecture supports new low-precision data formats, significantly enhancing AI performance, with matrix core improvements leading to nearly four times the computational throughput for low-precision formats [46][47]. Local Data Sharing (LDS) Enhancements - CDNA 4 increases the Local Data Share (LDS) capacity to 160 KB and doubles the read bandwidth to 256 bytes per clock, improving data locality for matrix multiplication routines [14][48]. - The architecture introduces new instructions for reading transposed LDS, optimizing memory access patterns for matrix operations [18]. Memory Hierarchy and Cache - The memory hierarchy includes a shared 4 MB L2 cache and a 32 KB L1 vector cache per CU, with enhancements for caching non-coherent data from DRAM [49][50]. - The Infinity Cache remains at 256 MB, providing high bandwidth and supporting the increased memory demands of modern AI workloads [53]. Chiplet Architecture - The CDNA 4 architecture continues to leverage a chiplet-based design, allowing for independent evolution of each chiplet for improved performance and manufacturability [35][36]. - Each XCD contains 36 compute units, organized into arrays, with a focus on maximizing yield and operational frequency [39]. System Communication and Expansion - The architecture includes eight AMD Infinity Fabric links, with improved speeds of up to 38.4 Gbps, enhancing communication bandwidth within server nodes [63]. - The design supports both direct compatibility with previous generations and progressive improvements for high-performance systems [62]. Conclusion - AMD's CDNA 4 architecture builds on the success of CDNA 3, focusing on optimizing performance for machine learning workloads while maintaining a competitive edge against Nvidia [26][27].

Core Viewpoint - The article discusses the current state and future directions of photomask manufacturing, emphasizing the importance of curved masks and advanced computational tools in extending the viability of non-EUV lithography technologies [1][3][4]. Group 1: Innovations in Photomask Technology - The use of curved photomasks is a significant innovation that leverages current writing technologies to create complex shapes previously unattainable [3]. - Advanced computational tools, such as Mask Process Correction (MPC) and high-level simulations, are increasingly used in the mask design flow, reducing the need for expensive experiments and pushing technological limits [3][6]. - The evolution of variable shape beam (VSB) writing technology to multi-beam writing technology has made curved mask shapes feasible without increasing writing time or costs [5]. Group 2: Challenges and Infrastructure Needs - There is a substantial need for infrastructure development to support the complexity of curved shapes, as traditional rectangular descriptions are simpler to manage [8]. - The transition to curved processes is seen as an exception rather than the norm, impacting economics and infrastructure, particularly in the reliance on GPU-based computing [9]. - Measurement technologies must evolve to handle the complexities of curved shapes, requiring higher resolution and faster measurement tools [11]. Group 3: EUV Masking Issues - EUV masks face challenges such as lower durability compared to 193i masks, necessitating frequent replacements that increase costs and complexity [13]. - The performance of EUV pellicles is currently suboptimal, leading to significant wafer throughput losses due to energy loss during transmission [13][15]. - The balance between using pellicles and the associated costs is contingent on the specific use case, with larger, high-value chips benefiting more from pellicles than smaller, redundant designs [16]. Group 4: Future Directions and Research - Research is ongoing into alternative materials for pellicles, such as carbon nanotube films, which could address current limitations but are not yet in mass production [17]. - The industry is exploring ways to improve the durability and transmission rates of EUV pellicles, which could lead to broader applications if successful [15][16].

公众号记得加星标⭐️，第一时间看推送不会错过。 台积电已与美国公司Amkor合作，在美国开发先进封装能力，但其首批芯片将运往台湾封装成集成电 路。封装产能一直是人工智能供应的关键瓶颈，今天的报告显示，台积电今年的产能可从去年的7.5 万片扩大到11.5万片。此次产能提升是为了应对CoWoS L/S封装技术，此前有报告称，到2025年中 期，台积电的封装产能可能达到7.5万片。 关于亚利桑那州的芯片生产，报道称，台积电已在该工厂生产了2万片晶圆，这是其首批芯片的一部 分。这些芯片包括NVIDIA、AMD和苹果的产品，这三家公司在该工厂正式投入使用后不久就宣布了 订单。据详细信息显示，这些晶圆包括用于NVIDIA Blackwell AI芯片的晶圆，这些芯片将运往台 湾，采用CoWoS技术进行先进封装。 除了英伟达的AI芯片外，亚利桑那州的工厂还生产苹果iPhone系列中使用的处理器以及AMD第五代 EPYC数据中心处理器。AI封装带来的高需求迫使台积电等公司扩大产能，同时也激励了其他参与者 进入市场。 其中包括台湾第二大芯片代工厂商联华电子。据报道，联华电子正与高通合作，利用其晶圆上晶圆 （WoW）技术封装芯片 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 来源：内容 编译自 IEEE 。 QuantumBloom首席运营官兼联合创始人安德里亚·穆罕默德 (Andrea Mohamed)表示，在这种支持 匮 乏 的 同 时 ， 预 计 会 出 现 严 重 的 劳 动 力 短 缺 。 QuantumBloom 致 力 于 帮 助 企 业 吸 引 、 留 住 和 提 升 STEM 领域早期职业女性。该公司专注于从高等教育到职场的过渡，这是许多女性离开 STEM 领域 的关键时期。 IEEE Spectrum采访了 Mohamed，谈到了对女性从事半导体工作的支持，以及为什么放弃这些举措 与行业需求相悖。 问：作为半导体行业的回归老手，请告诉我您的看法。 半导体行业的女性比例一直很低。根据4月份发布的一份报告，51%的公司报告称，其技术职位中女 性所占比例不到20%。同时，该报告发现，公开承诺在2024年实施平等机会措施的公司数量与前一年 相比有所减少。 安德里亚·穆罕默德： 20多年前，我在一家半导体初创公司工作，当时公司主要由男性主导。现在， 情况依然如此。以全新的视角看待半导体行业，我发现这个行业的发展速度不如其他 ...

Core Viewpoint - The Genesis project, involving 58 European companies and research institutions, aims to enhance the sustainability of semiconductor manufacturing, addressing environmental impacts and resource efficiency in the industry [1][2][3]. Group 1: Project Overview - The Genesis project has a budget of €55 million and focuses on making semiconductor production more sustainable globally, not just in Europe [1]. - The project includes four main workflows: monitoring and sensing, new materials, waste minimization, and critical raw materials mitigation [3]. - The initiative aims to produce 45 outcomes over the next three years, addressing emissions, material optimization, and recycling [3]. Group 2: Industry Challenges and Drivers - The semiconductor industry faces increasing pressure from customers to produce chips sustainably, managing water resources and achieving carbon neutrality [4]. - Regulatory measures are expected to strengthen over time, driven by climate change concerns, necessitating action from the industry [4]. - Major companies are pushing for sustainability in semiconductor production, indicating a shift in industry norms [4]. Group 3: Technological Innovations - The project will deploy integrated sensor systems to monitor and reduce emissions of harmful substances like PFAS and greenhouse gases [3]. - There is a focus on developing AI models based on sensor data to enhance wafer fabrication efficiency, although AI integration is not currently part of the Genesis project [7]. - The project aims to replace 30% of new materials used in lithography and packaging processes with more sustainable alternatives [8]. Group 4: Collaboration and Training - The project includes a partnership with Applied Materials to develop material engineering solutions for emerging infrastructure challenges in AI data centers [9][10]. - The FAMES Academy is being established to train engineers and technicians in low-power FD-SOI technology, supporting the European semiconductor community [11]. - The academy will focus on workshops and interactive sessions to equip the industry with necessary skills and knowledge [11].

随着半导体先进封装与FPD制造技术的不断演进，洁净室自动化生产设备面临的静电问题 日益严峻。为帮助行业同仁深入了解静电带来的潜在风险，并探索高效可靠的解决方案， 提升产能和良率， 戈尔诚邀您参与6月26日举办的半导体及FPD设备静电解决方案专题研 讨会 。 户经验,还曾负责东南亚市场,对国 内外大客户的设备及应用需求有深 入了解。 同 核心内容提要 本次研讨会将 聚焦于洁净室环境中静电控制的关键技术 ，分享前沿解决方案与真实应用案例， 助力您提升设备可靠性与产能表现。 > 痛点直击:半导体先进封装中的静电问题及风险 技术革新:戈尔新一代电缆技术:防止静电积聚, 提升可靠性和产效 全球案例: 1.全球知名先进封装设备商应用案例分析 2.全球知名FPD制造商在OLED设备为什么采用 抗静电电缆? ● Q&A环节:戈尔经验丰富的技术团队在线答疑 解惑。 Together, improving life 扫描下方二维码预约报名 即可激活抽奖资格 扫码立即锁定席位 倒计时提示 ⏳ 席位有限！ 6月26日前预约有效 （本文图源：戈尔） *免责声明：本文由作者原创。文章内容系作者个人观点，半导体行业观察转载仅为了传达一种不 ...

Core Viewpoint - The DRAM market is undergoing significant changes, highlighted by a rapid increase in DDR4 prices and shifts in market dynamics among major players like Micron, Samsung, and SK Hynix [1][5]. Group 1: Micron's Developments - Micron has announced the discontinuation of DDR4 production, leading to a dramatic price surge in DDR4 DRAM, with prices increasing over 100% this season [1]. - The company has introduced its 1γ (1-gamma) DDR5 technology, which boasts a 15% increase in data transfer speed compared to its predecessor and a 20% reduction in power consumption, crucial for AI and data center applications [2]. - Micron plans to invest $200 billion in expanding advanced DRAM manufacturing and R&D in the U.S., which is expected to significantly impact the future DRAM landscape [5]. Group 2: Samsung's Challenges - Samsung has faced difficulties with HBM certification, with reports indicating multiple failures in obtaining HBM3E certification, which is critical for its product offerings [7][9]. - Despite these challenges, Samsung has successfully delivered HBM3E chips to AMD, marking a significant step in its HBM product line [8]. - The company is also planning to expand its 1c DRAM production line, which is essential for its HBM4 technology, indicating a commitment to overcoming current production hurdles [9][10]. Group 3: SK Hynix's Strategy - SK Hynix has emerged as a leader in the DRAM market, capturing a 36% market share, surpassing Samsung's 34% [11]. - The company is taking a cautious approach to expanding its DRAM and HBM production capacity, delaying equipment investments and scaling back production expectations [12][13]. - SK Hynix is also focusing on future technology roadmaps, including the development of 4F² and 3D DRAM technologies to enhance performance and capacity [14]. Group 4: Future of DRAM Technology - The future of DRAM technology is promising, with advancements expected in 3D DRAM architectures and the transition to smaller nodes, including 0c/0d by 2033-2034 [19]. - Major manufacturers are exploring various architectural paths to achieve 3D DRAM integration, indicating a competitive landscape driven by innovation [19]. - The introduction of HBM4 and HBM5 is anticipated to significantly increase memory bandwidth and data transfer rates, with HBM4 expected to reach 2 TB/s by 2026 [21].