欧盟委员会已批准向德国提供6.23亿欧元（约合51亿人民币）的国家援助，用于支持德国的两个新的 半导体制造项目，这标志着欧洲在推进芯片自主权方面又迈出了切实的一步。具体而言，这笔资金将 用于支持GlobalFoundries在德累斯顿和X-FAB在埃尔福特运营的两座全新的、独一无二的晶圆厂。 对于eeNews Europe 的读者而言，这项决定意义重大，因为它直接影响欧洲未来获取先进制造业产 能的机会，尤其是在汽车、工业、航空航天和人工智能应用领域。它也揭示了《欧洲芯片法案》下公 共资金的流向，以及政策制定者认为哪些技术具有战略关键性。 公众号记得加星标⭐️，第一时间看推送不会错过。 援助资金中最大的一笔，即4.95亿欧元，将用于支持GlobalFoundries在德累斯顿的"SPRINT"项目。 这家总部位于美国的纯晶圆代工厂计划扩建并改造其现有工厂，以新增300毫米晶圆制造产能。 这些技术最初是在微电子和通信技术综合计划 (IPCEI) 下开发的，但现在将进行改造，以适应包括航 空航天、国防和关键基础设施在内的军民两用市场。这意味着要增加特定的安全性和可靠性功能，并 确保整个制造过程都在欧洲完成。欧盟委员 ...

Core Viewpoint - TSMC's transition to 2nm GAA technology marks a significant advancement in semiconductor manufacturing, with expectations of increased production capacity and efficiency, while the real bottleneck lies in advanced packaging technologies like CoWoS, rather than transistor density [1][40]. Group 1: 2nm Technology and Production - TSMC's 2nm technology is set to begin mass production in Q4 2025, utilizing nanosheet transistors that enhance performance and power efficiency across all process nodes [1]. - Compared to the 3nm N3E process, the 2nm technology offers a 10% to 15% speed increase at the same power level, and a 25% to 30% reduction in power consumption while increasing chip density by over 15% [2]. - TSMC plans to establish five 2nm fabs in Kaohsiung, with a total investment exceeding NT$1.5 trillion, creating 7,000 high-tech jobs [2]. Group 2: Advanced Packaging Challenges - The CoWoS (Chip-on-Wafer-on-Substrate) technology is critical for integrating advanced chips with HBM memory; without it, even the most advanced chips could become excess inventory [3][40]. - Advanced packaging capabilities are becoming the key limiting factor in the AI semiconductor sector, overshadowing the importance of transistor density [40]. - TSMC's CEO confirmed that supply constraints are expected to persist until 2025, despite plans to double production capacity in 2024 and 2025 [21]. Group 3: Market Dynamics and Competitors - NVIDIA is projected to secure over 70% of the CoWoS-L capacity, creating a structural advantage, while companies like Broadcom are also vying for a share of the remaining capacity [23][40]. - The AI chip market is evolving, with companies like Broadcom capturing approximately 70% of the custom AI accelerator market, and their AI revenue expected to reach $12.2 billion in FY2024, a 220% year-over-year increase [32]. - The competition in the AI chip market is intensifying, with major players like AMD and Intel also making significant strides in developing their own AI hardware solutions [35][37]. Group 4: Future Developments and Innovations - TSMC is diversifying its advanced packaging technologies, including the development of CoPoS (Chip-on-Package-on-Substrate) technology, expected to be introduced after 2027 [24]. - The transition from FinFET to GAA technology introduces new manufacturing complexities, requiring specialized equipment and processes, which could extend production timelines [11][40]. - The demand for advanced packaging is expected to grow significantly, with OSAT (Outsourced Semiconductor Assembly and Test) companies also ramping up their capabilities to meet the increasing needs of AI chip production [43].

Core Insights - The global AI infrastructure market is facing a severe supply shortage, particularly for GPUs, with an expected order volume of 2 million units this year against only 700,000 available units [1] - The demand for self-developed ASICs by cloud service companies is projected to grow at a rate of 44.6%, surpassing the 16.1% growth rate for GPUs, indicating a structural shift towards ASIC adoption due to GPU supply constraints [1] - The supply chain risks for GPUs are expected to peak this year, with production processes and high bandwidth memory (HBM) being interlinked, meaning any bottleneck could disrupt overall supply [1] Group 1 - TSMC is expanding its advanced packaging production lines, crucial for AI accelerators, but the gap between rapidly growing order volumes and actual shipments will persist due to the time required for capacity expansion [2] - ASIC chips, initially led by Google's TPU, are gaining attention as they are designed for specific AI workloads, offering advantages in energy efficiency, performance, and total cost of ownership (TCO) in the long run [2] - The AI accelerator market for ASIC users is expected to maintain a compound annual growth rate (CAGR) of approximately 28% until 2030, with the generative AI ASIC market projected to grow from about $24.9 billion in 2024 to approximately $186.7 billion by 2032, reflecting an annual growth rate of around 28.6% [2] Group 2 - This year is viewed as a critical turning point for the ASIC market, with industry executives noting that the current GPU supply shortage is a short-term issue but will have long-term implications on decision-making [3] - Major tech companies are increasingly viewing GPUs as strategic assets rather than stable commodities, leading to a shift towards reducing GPU dependency and increasing the share of ASICs in new data center investment plans [3]

2026年，全球半导体行业将进入转型期，市场结构和价值链将进行调整以适应人工智能基础设施的扩 张。预计整个市场规模将接近1万亿美元，其中存储半导体将成为需求和盈利能力的关键驱动力。尤 其值得一提的是，业内专家预计SK海力士将成为这一转变的主要推动力，因为这家芯片制造商拥有 独特的优势，是唯一一家能够可靠地交付HBM3E和下一代HBM4的供应商。 根据世界半导体贸易统计（WSTS）的数据，2026年全球半导体市场将同比增长超过25%，达到约 9750亿美元，其中存储器领域的增长率将达到30%。市场研究公司和投资银行预计服务器和数据中心 存储器市场将出现特别强劲的增长，一些机构估计2026年存储器市场规模将超过4400亿美元。 分析表明，随着人工智能训练和推理服务器投资的增加，每台服务器的DRAM和HBM内存容量也在 稳步增长。与此同时，对企业级固态硬盘（eSSD）等存储设备的需求也在上升，导致整个人工智能 基础设施中内存和存储的占比结构性增加。 自2024年以来，业内人士一直用"超级周期"来形容存储器行业的强劲增长势头。美国银行（BofA） 将2026年定义为"类似于上世纪90年代繁荣时期的超级周期"，并预测全 ...

行业分析认为，若交易顺利完成，紫光国微将通过整合在功率半导体领域拥有全球市场地位和制造 能力的瑞能半导体， 实现构建"设计+制造"的完整产业链，并将牢牢抓住汽车电子、工业控制等关 键领域的国产化机遇，改变中国功率半导体市场的竞争格局。 此外，本次交易也折射出新紫光集 团加速半导体全产业链整合的战略动向。 2025年12月30日，新紫光集团旗下紫光国微发布重大资产重组公告，拟通过发行股份及支 付现金方式收购瑞能半导体控股权或全部股权，并同步募集配套资金。 中国工程院院士丁荣军曾强调， 功率半导体是保障能源革命推进与国家产业安全的核心关键， 是 中国半导体自主突围的核心抓手。而瑞能半导体，作为 中资控股 下的功率半导体企业，不仅继承 了欧洲老牌半导体产业的深厚技术积淀，也在过去十年间完成了精准的赛道布局，使其在功率半导 体领域形成独特竞争力。 | 证券代码:002049 | 证券简称:紫光国微 | 公告编号:2025-108 | | --- | --- | --- | | 债券代码:127038 | 债券简称:国微转债 | | 设计+制造：强强联手的产业链协同 瑞能半导体前身为恩智浦半导体标准产品事业部，2015 ...

该公司的原型机于今年夏季搭乘SpaceX火箭发射升空，旨在测试太空环境如何提升材料性能。在微 重力环境下，半导体原子可以形成近乎完美的晶体结构，而地球上空的真空环境则几乎完全消除了空 气中颗粒物的污染。这种组合有望生产出结构均匀性更高、电子效率更强的材料。 "我们现在所做的工作使我们能够在太空制造出比我们今天在这里制造的纯度高出 4000 倍的半导 体，"太空锻造公司首席执行官乔什·韦斯特恩告诉 BBC。 他指出，这种高纯度材料对现代基础设施具有实际意义，从 5G 基站到电动汽车充电系统和下一代飞 机。 该公司总部位于卡迪夫，自卫星发射以来，一直持续监测和验证卫星的性能，并将此次任务视为一次 在轨技术演示。 有效载荷操作负责人维罗妮卡·维埃拉分享了来自内部摄像系统的图像，图像显示炉内有明亮的等离 子体发射：一种被加热到大约 1000°C 的气相，这是启动高温材料加工的关键条件。 维埃拉形容看到这张照片是"我人生中最激动人心的时刻之一"，并指出在微重力环境下实现稳定的等 离子体生成对公司的发展路线图意义重大。她补充说，这项测试证明了Space Forge公司实现其长期 目标——在太空制造——的"核心要素"，也初 ...

Core Insights - The article emphasizes the need for a collaborative design approach between microarchitecture and process technology to address the increasing challenges of thermal density, power consumption, and performance demands in semiconductor technology [1][3][34] Group 1: Thermal Density - Higher integration leads to increased thermal density, defined as power per unit area, which is exacerbated by shrinking feature sizes and higher integration levels [5] - Current silicon chips can reach critical temperatures rapidly, necessitating the consideration of thermal sensors and cooling measures from the outset [9] - Traditional cooling methods like heat sinks and fans are becoming inadequate, prompting a shift towards microarchitecture and chip layout as primary tools for thermal management [10] Group 2: Efficient Energy Performance - The relationship between performance and power consumption is critical, with voltage scaling showing that while performance increases with voltage, power consumption rises exponentially, highlighting the need for technologies that reduce leakage and capacitance [13][16] - Advances in process technology enable higher performance at constant power and lower power at constant performance, but aggressive size reductions may increase thermal density, requiring architectural responses [16] - Simplifying microarchitecture can reduce area, thereby lowering target frequency, capacitance, and leakage, which is essential for optimizing overall system power consumption [20] Group 3: System-Level Scalability - Amdahl's Law illustrates the limitations of performance scalability in parallel processing, indicating that performance is ultimately constrained by the serial portions of programs [23] - The utilization of active cores varies significantly under typical workloads, affecting power and bandwidth sharing among cores [27] - Key research directions in process technology must align with architectural needs, focusing on low leakage and low capacitance materials, thermal-aware 3D integration, and fine-grained power gating [31][32] Conclusion - Advanced semiconductor process technologies can deliver exceptional performance, but without architectural awareness, their advantages will be limited by power and thermal constraints. A new collaborative design paradigm between architecture and process technology is essential for sustainable, high-performance computing [34]

Core Viewpoint - The Taiwanese authorities announced the "Advanced Development Subsidy Program for IC Designers" for 2026, prioritizing support for IC designers in developing chips for drones, robots, and satellite communications to maintain Taiwan's critical position in the global semiconductor industry [1]. Group 1: Subsidy Program Overview - The total budget for this subsidy program in 2023 is set at NT$1.75 billion, with a duration of no more than three years [2]. - The subsidies are divided into two categories: - The first category focuses on "advantageous chip" development, allowing single applications with a maximum subsidy of NT$200 million, targeting innovative chips that address industry technology gaps or market demands, particularly in drones, robots, and satellite communications [2]. - The second category is for "core chip and system development," which allows joint applications with a maximum subsidy of NT$300 million, aimed at developing high-value core chips and modules/systems in collaboration with local system operators [2]. Group 2: Targeted Chip Types and Specifications - The program specifies the types and specifications of chips eligible for subsidies, including: - Communication chips for the drone sector - Composite sensing and control chips for the robotics sector - Ku band RF chips for the satellite communications sector [2].

Core Viewpoint - TSMC controls advanced CoWoS packaging capacity, which is crucial for determining which AI chip manufacturers can scale production, making it a key player in the explosive growth of the AI market [1][2]. Group 1: TSMC's Role in AI Development - TSMC's CoWoS capacity is becoming increasingly critical for the survival and growth of other chip manufacturers and designers, as advanced packaging technology has become a new industry bottleneck [1]. - The rapid development of AI since 2023 has created trillions of dollars in market value, but supply chain bottlenecks, particularly in advanced manufacturing, are limiting growth [1][3]. - TSMC is a key factor in determining the speed and scale of AI development, with its capacity expansion plans aiming to double advanced wafer capacity by 2028 [4]. Group 2: Impact on Competitors - Google has reduced its 2026 TPU production target from 4 million to 3 million units due to limited access to TSMC's CoWoS technology, while NVIDIA has secured over half of TSMC's CoWoS capacity until 2027 [3]. - The shortage of CoWoS capacity may intensify competition, prompting other manufacturers like Intel to fill the gap and compete with TSMC in the foundry services sector [4][5]. - Companies like Google and Apple are exploring alternative solutions, such as Intel's EMIB packaging technology and engaging with Samsung's factories to meet their needs [4].

Core Viewpoint - The article discusses the rapid growth and opportunities in the GPU market driven by the increasing demand for AI processing capabilities, highlighting the emergence of domestic GPU manufacturers like TianShu ZhiXin as key players in this evolving landscape [1][3]. Group 1: Market Dynamics - The demand for AI semiconductors is expected to surge, with revenue projected to reach $438.5 billion by 2029, reflecting a compound annual growth rate (CAGR) of 25.9% over five years [1]. - The domestic GPU market is experiencing significant growth due to international competition, providing local manufacturers with increased opportunities [1]. Group 2: Company Overview - TianShu ZhiXin is recognized as the first domestic general-purpose GPU manufacturer, established in 2015, and has become a significant player in the GPU sector [3]. - The company has developed two main product lines: the TianYuan series for AI model training and the ZhiKai series for inference, covering the entire AI computing process from development to deployment [4]. Group 3: Product Development and Achievements - As of June 30, 2025, TianShu ZhiXin has delivered over 52,000 general-purpose GPU products to more than 290 clients across various industries, including finance, healthcare, and transportation [5]. - The company ranks among the top five core participants in China's general-purpose GPU market, with significant market shares in both training and inference GPU products [6]. Group 4: Financial Performance - The company's revenue has shown remarkable growth, with figures of RMB 189.4 million in 2022, RMB 289 million in 2023, and RMB 539.5 million in 2024, reflecting a CAGR of 68.8% [6]. - For the first half of 2025, revenue reached RMB 324.3 million, a 64.2% increase compared to the same period in 2024 [6]. Group 5: R&D and Innovation - TianShu ZhiXin has a strong R&D team of over 480 professionals, with significant experience in semiconductor design and GPU software development [11]. - The company has maintained high R&D expenditures, with amounts of RMB 456.6 million, RMB 615.9 million, and RMB 772.8 million in 2022, 2023, and 2024, respectively, representing over 140% of total revenue in recent years [12]. Group 6: Future Outlook - The company plans to continue focusing on general computing core capabilities, enhance product performance, and expand market reach while participating in global market competition [14]. - TianShu ZhiXin aims to strengthen collaborations within the industry chain and promote the development of a domestic computing ecosystem [14].