Core Viewpoint - The article emphasizes the growing importance of radio frequency front-end modules in smartphones, particularly in the context of 5G technology, highlighting China's progress in this high-tech field and the competitive landscape among domestic and international players [1][2][6]. Summary by Sections Radio Frequency Front-End Modules - Radio frequency front-end modules, consisting of components like power amplifiers (PA), low noise amplifiers (LNA), switches, and filters, are critical for signal transmission and reception in smartphones [1]. - The complexity of these modules is increasing due to high integration requirements and the need to support multiple frequency bands, particularly in the Sub3G L-PAMiD category [1][2]. Technical Challenges - The development of high integration modules like Sub3G L-PAMiD faces significant challenges, including high design complexity, fragmented frequency bands, and stringent size and packaging requirements [1]. - The design and packaging of filters and duplexers for these modules require advanced techniques and materials, with a focus on minimizing size while maximizing performance [1][4]. Market Dynamics - Major smartphone manufacturers are increasingly adopting high integration L-PAMiD modules, with Chinese brands achieving significant milestones in domestic production and design capabilities [2][3]. - The market for radio frequency front-end components is evolving, with a shift from lower integration solutions to more complex, high-performance modules [3][6]. Future Trends - The future of radio frequency front-end technology is geared towards higher performance, greater integration, and smaller sizes, driven by the demands of 5G and beyond [4][5]. - Emerging technologies such as ultra-wideband and carrier aggregation are becoming critical for achieving high data rates in 5G, necessitating advancements in linearity and isolation in front-end components [5]. Industry Positioning - China's radio frequency front-end industry is transitioning from a technology follower to a standard setter, with opportunities to capture greater market share in the 5G and 6G eras [6]. - The industry's growth is supported by strong market demand, capital investment, and technological advancements, although challenges remain in certain core materials and high-end manufacturing equipment [6].

来源 ：内容 编译自 chipsandcheese 。 Condor Computing 是晶心科技的子公司，致力于开发可授权的 RISC-V 内核，其商业模式与 Arm （该公司）和 SiFive 类似。晶心科技于 2023 年成立 Condor，因此 Condor 在 RISC-V 领域相对年 轻。然而，晶心科技在 Condor 成立之前就拥有 RISC-V 设计经验，并在过去几年中开发了一些 RISC-V 内核。 Condor 将在 Hot Chips 2025 上展示其 Cuzco 核心。该核心是 RISC-V 领域的重量级产品，拥有广 泛 的 乱 序 执 行 功 能 、 先 进 的 分 支 预 测 器 以 及 一 些 新 的 基 于 时 间 的 技 巧 。 它 与 SiFive 的 P870 和 Veyron 的 V1 等高性能 RISC-V 设计处于同一级别。与这些核心一样，Cuzco 应该会比目前已投入 硅片的 RISC-V 核心（例如阿里巴巴 T-HEAD 的 C910 和 SiFive 的 P550）更胜一筹。 公众号记得加星标⭐️，第一时间看推送不会错过。 除了采用宽乱序设计外，Cuzco ...

公众号记得加星标⭐️，第一时间看推送不会错过。 佳能 LI8030SA 的定位并非面向大众市场，而是面向监控、医疗和工业图像处理等高度专业化的行 业。在 2025 年 P&I 展会上，这款传感器被放置在玻璃后方进行展示，这通常清楚地表明它仍处于 开发阶段。佳能已经开始接受意向书，尽管最初的型号并非用于传统相机。然而，这项技术未来也可 能影响佳能的商用传感器。 凭借4.1亿像素的传感器，佳能令人印象深刻地展示了这一领域的发展方向。然而，对于业余摄影师 来说，这款传感器仍然是一个遥不可及的梦想。毕竟，我们大多数人并不需要如此高的分辨率。然 而，在专业领域，它却开辟了新的维度。 据佳能介绍，这颗新开发的CMOS传感器拥有相当于24K的分辨率（相当于全高清的198倍，8K的12 倍）。用户可以裁剪该传感器捕捉到的图像的任意部分，并在保持高分辨率的同时进行大幅放大。许 多超高像素CMOS传感器通常采用中画幅或更大画幅，而这款超高分辨率传感器则采用35mm全画幅 格式。这使得它可以与全画幅传感器的镜头组合使用，并有望为拍摄设备的小型化做出贡献。由于 CMOS传感器的数据读取时间会随着像素数量的增加而延长，因此实现超高像素 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 来源 ：内容 编译自 tomshardware 。 尽管英伟达飙升的收入持续引人关注，但其对少数客户的严重依赖既带来了机遇，也带来了不确定 性。市场观察人士仍在关注客户构成和未来云计算支出的进一步明晰，因为这些因素正日益影响着对 该芯片制造商下一阶段增长的预测。 英伟达（Nvidia）最新财务报告显示，仅两位客户就贡献了该公司7月份当季39%的收入——这一集 中度再次引发了分析师和投资者的关注。根据提交给美国证券交易委员会（SEC）的文件，"客户 A"占英伟达总收入的23%，而"客户B"占16%。 这一收入集中度明显高于去年同期，当时 Nvidia 的前两大客户分别贡献了 14% 和 11%。 英伟达通常会按季度披露其主要客户。然而，这些最新数据引发了一场新的讨论：英伟达的增长轨迹 是否严重依赖于一小部分庞大的买家，尤其是大型云服务提供商。 外界普遍猜测，微软、Meta、亚马逊、谷歌和甲骨文等科技和云计算巨头可能是英伟达支出最高的 客户。然而，尽管关注度不断提升，英伟达却拒绝透露其文件中提到的客户的具体信息，这些客户的 身份目前仍不清楚。 该公司对直接和间接客户 ...

Core Viewpoint - The Basilisk project, presented at Hot Chips 2025, aims to redefine the potential of open-source hardware by demonstrating a fully functional RISC-V SoC that operates on a complete Linux system, developed entirely using open-source EDA tools [2][11]. Group 1: Project Overview - Basilisk is a 34 mm² RISC-V SoC manufactured using IHP Microelectronics' open-source 130nm BiCMOS process [2]. - The project signifies a shift from viewing open hardware as an academic toy to a reliable system platform [2]. - The chip integrates a single-issue, in-order RV64GC CPU core (CVA6) with MMU, instruction/data cache, and HyperRAM controller, supporting a Linux software stack [6]. Group 2: Industry Context - Many large semiconductor companies have joined the RISC-V International Organization but have not actively supported its ecosystem, indicating a reluctance to embrace the shift towards open-source chips [2][3]. - The high costs associated with advanced node fabrication, often reaching tens of millions of dollars, lead companies to prefer proprietary suppliers that offer security and support [3]. - The current semiconductor landscape shows a clear divide, with U.S. companies sticking to familiar licensing models while challengers in China and Europe are accelerating the adoption of open processes [4]. Group 3: Technological Advancements - The project aims to demonstrate that fully open processes can achieve industrial standards through reasonable engineering investments, with future projects targeting larger scales [9]. - The use of Yosys and OpenROAD tools is highlighted as essential for proving the viability of open-source chip design [5]. - The Basilisk chip achieved a peak frequency of 102 MHz at 1.64 V and demonstrated high energy efficiency at lower voltages, indicating the potential of open-source designs to leverage voltage scalability [7]. Group 4: Strategic Implications - The support for the Basilisk project by the Swiss government and research institutions reflects a broader trend of viewing investment in open silicon as a matter of strategic sovereignty [11]. - The emergence of open-source EDA tools presents both a challenge and an opportunity for existing companies, as universities can now train engineers in these processes, potentially leading to innovation in commercial tools [9].

Core Viewpoint - AMD's current Radeon RX 9000 series, based on RDNA 4 architecture, is not aimed at challenging NVIDIA in the high-end desktop GPU market, with the RX 9070 XT positioned against NVIDIA's mid-range GeForce RTX 5070 Ti [2] Group 1: AMD's Development and Future Plans - AMD's senior researcher Laks Pappu is involved in the development of next-generation GPUs, including Navi4x and Navi5x architectures, indicating potential advancements in chip design [2][3] - Pappu's experience at Intel, where he worked on high-end graphics processors, positions him to influence AMD's future GPU designs significantly [3] - The development cycle for high-end GPUs typically spans 2.5 to 3.5 years, suggesting that while RDNA 4 and CDNA 4 architectures are already defined, Pappu's input could impact the physical implementation and performance optimization of upcoming products [3][4] Group 2: Multi-Chip Design Challenges - Building multi-chip consumer GPUs presents significant challenges due to the need for high-speed, low-latency communication between processing units, which is critical for performance [5] - The complexity of software and driver integration for multi-chip GPUs adds another layer of difficulty, limiting such designs primarily to data center and HPC applications [5][6] - AMD's previous experience with multi-chip designs in CPUs and the Radeon RX 7900 series suggests that the company is well-positioned to explore multi-chip GPU architectures in the future [6] Group 3: Future Product Expectations - Pappu's involvement in the Navi 5x development indicates that AMD may adopt 2.5D or 3.5D packaging for future GPUs, potentially leading to innovative designs [4][7] - The expected release timeline for RDNA 5 is around late 2026 to early 2027, with the architecture likely entering the tape-out phase by mid-2025 [7][8] - AMD is anticipated to conduct tests on actual hardware in the coming months to evaluate the feasibility of multi-chip designs for consumer GPUs, which may lead to interesting developments [8]

Core Viewpoint - The article discusses the transformative Ultra Ethernet (UE) 1.0 standard, which defines a high-performance Ethernet protocol for artificial intelligence (AI) and high-performance computing (HPC) systems, emphasizing its innovative Ultra Ethernet Transport (UET) layer designed for reliable, high-speed communication in large-scale systems [2][4]. Group 1: Overview of Ultra Ethernet - Ultra Ethernet (UE) aims to standardize high-performance networking for AI and HPC, addressing limitations of existing protocols like InfiniBand and RoCE [4][8]. - The development of UE involved collaboration among major tech companies, leading to the formation of the Ultra Ethernet Consortium (UEC) in July 2023, with over 100 member companies by the end of 2024 [9][10]. - UE is designed to be compatible with existing Ethernet infrastructure, allowing for easy deployment and scalability in data centers [10][11]. Group 2: Technical Innovations - The UET layer allows for hardware-accelerated communication, significantly improving computational efficiency by a factor of 1000 for every bit of data transmitted [2][7]. - UE introduces a connectionless API and supports various topologies, including traditional fat tree and optimized structures, to meet the scalability needs of future AI systems [10][12]. - The protocol supports multiple delivery modes, including reliable unordered delivery and reliable ordered delivery, catering to different application requirements [49][50]. Group 3: Addressing Limitations of Existing Protocols - Previous protocols like RoCE faced challenges such as head-of-line blocking and congestion issues, which UE aims to resolve through innovative congestion management and packet delivery mechanisms [6][10]. - UE's design allows for packet spraying, which distributes packets across multiple paths to avoid traffic polarization and improve bandwidth utilization [22][21]. - The UET layer is built to operate seamlessly over existing Ethernet networks, ensuring compatibility while enhancing performance [14][27]. Group 4: Application and Use Cases - UE is applicable in various network types, including local networks connecting CPUs to accelerators, backend networks for high-performance connections, and frontend networks for traditional data center operations [12][13]. - The standard provides three configuration profiles (HPC, AI Full, and AI Base) to support different functionalities and complexities in implementation [24][25]. - The architecture of UE is designed to facilitate efficient communication in large-scale systems, making it suitable for modern AI workloads and HPC applications [28][29].

Core Viewpoint - The article emphasizes the urgent need for domestic production of semiconductor overlay measurement equipment in China, particularly in light of the low localization rate and the increasing demand driven by advanced process nodes and AI chip production [1][32]. Group 1: Semiconductor Equipment Landscape - China's semiconductor industry is making significant progress in equipment, but the localization rate for advanced process semiconductor equipment remains low [1]. - The manufacturing of a chip typically requires hundreds of devices and involves 400-500 processes, with overlay measurement being a critical step [1][5]. - Overlay measurement equipment is essential for ensuring the precision of layer alignment in semiconductor manufacturing, which directly impacts chip functionality and yield [5][11]. Group 2: Overlay Measurement Equipment - Overlay measurement devices are crucial for detecting and correcting alignment errors between layers during the chip manufacturing process [5][8]. - The acceptable range for overlay errors is closely related to the critical dimensions (CD) of the layers, with specific requirements for different process nodes [11][18]. - The demand for overlay equipment is increasing, particularly in advanced process nodes, with 80% of the demand coming from these processes [22][33]. Group 3: Market Dynamics - The overlay measurement market is dominated by KLA and ASML, which together hold over 90% of the market share [24]. - KLA has a significant presence in the market with a focus on IBO technology, while ASML has gained market share through DBO technology [24][26]. - The competitive landscape shows that KLA's equipment is preferred for memory chip manufacturing, while ASML's DBO technology is favored for logic chip processes [26]. Group 4: Domestic Challenges and Opportunities - The localization rate for overlay measurement equipment in China is less than 5%, highlighting the urgent need for domestic alternatives [33]. - Domestic manufacturers like Erwei Micro are emerging, with capabilities to develop competitive overlay measurement equipment, but challenges remain in achieving consistency and stability compared to international giants [34][38]. - The collaboration with local suppliers to enhance the domestic supply chain is crucial for the sustainable development of China's semiconductor industry [38][40].

公众号记得加星标⭐️，第一时间看推送不会错过。 来源 ：内容 编译自 etnews 。 除了台积电之外，随着韩国巨头三星恢复对其泰勒工厂的投资，该公司显然也在大力推动美国制造业 的发展。 鉴于过去几个季度三星的代工业务低迷，其在美国的投资也一直很少，因此其在美国的计划也随之调 整。然而，随着特朗普政府大力推崇"美国制造"的理念，以及美国客户对三星2纳米工艺的兴趣，据 ETNews报道，这家韩国巨头已恢复对其泰勒工厂的投资。这将包括人员部署、新代工设备的整合， 以及更重要的是，为2纳米工艺的生产做准备。 据业内人士31日透露，三星电子计划从9月开始部署人员，在泰勒工厂建立代工生产线。工程师将分 两批部署，分别在9月和11月。此外，已确认正在订购代工生产线建设所需的设备。 多位知情人士表示："我们已经完成人员选拔流程，计划在9月和11月部署人员。许多合作伙伴已经宣 布了设备订单，目前正在准备中。" 据报道， 三星电子还任命了泰勒代工厂的新负责人。此前，泰勒工厂由奥斯汀代工厂负责管理，但随着泰勒工 厂的运营全面展开，似乎内部已经任命了一位新负责人。 大约一年前，三星电子恢复了对泰勒工厂的投资。三星决定于2021年投 ...

公众号记得加星标⭐️，第一时间看推送不会错过。 如果一台个人电脑的大脑，其价格比一顿晚餐还便宜，会怎么样？1975 年，一群前摩托罗拉工程师 证明了这是可能的，并因此永远改变了计算产业。他们推出的 25 美元 MOS Technology 6502 处理 器，不仅为 Apple II、Commodore PET 和 Atari 2600 提供了动力，其设计理念也至今仍在新一代 精简指令集（RISC）CPU 中回响。 装在 DIP-40 塑料封装中的 MOS 6502。日期代码显示它制造于 1985 年 11 月。图片由 Dirk Oppelt via Wikimedia Commons 授权使用 (CC BY-SA 3.0) 撼动业界的廉价芯片 来源 ：内容来自 allaboutcircuits 。 1975 年 6502 处理器广告。图片由 MOS Technology via Wikimedia Commons 授权使用 (公共领域) 1975 年在 WESCON 展会上，6502 首次亮相，立刻成为了行业传奇。由于场馆内禁止现场销售， Peddle 的团队在附近的一家酒店套房里摆摊，从装满芯片的罐子里以 ...