Core Insights - The article discusses the rapid growth of Ethernet networks and the competition among major players like Broadcom, Cisco, and Nvidia in the Ethernet switch ASIC market, particularly in the context of AI advancements [1][2][3] - Broadcom's Tomahawk 6 ASIC is highlighted as a leading product, with capabilities of 102.4 Tb/s and future versions expected to reach 204.8 Tb/s and 409.6 Tb/s, which are crucial for AI applications [2][3][10] - The article emphasizes the shift in enterprise networks towards higher-speed Ethernet, driven by the demands of AI workloads, which may accelerate the adoption of 100 Gb/s, 200 Gb/s, and even 400 Gb/s Ethernet [2][3] Summary by Sections Ethernet Network Growth - Ethernet networks are experiencing significant growth, allowing switch manufacturers to maintain business growth despite challenges [1] - The UltraEthernet Consortium aims to support 1 million GPU endpoints, necessitating larger capacity switch ASICs [1] Competition in the ASIC Market - Broadcom faces competition from Cisco and Nvidia, with its Tomahawk 6 ASIC leading the market with a focus on high bandwidth and cost efficiency [2][3] - The introduction of co-packaged optical devices is anticipated to reduce costs and expand network coverage [2] AI and Ethernet Adoption - The enterprise market has been slow to transition from 10 Gb/s to 100 Gb/s Ethernet, but AI's influence may accelerate this shift [2] - AI backend demands are expected to drive the adoption of higher-speed Ethernet in enterprise settings [2] Tomahawk 6 ASIC Features - Tomahawk 6 is designed to meet the bandwidth, low latency, and high base requirements of AI training and inference applications [6] - The chip utilizes a 3nm process technology, offering significant improvements in performance and efficiency compared to previous generations [10][11] Cost and Efficiency - The article discusses how the design of Tomahawk 6 allows for a reduction in the number of chips needed for equivalent performance, thereby lowering costs [8][15] - The transition to Tomahawk 6 is expected to significantly reduce power consumption compared to older ASICs, which is critical for large-scale AI deployments [15] Market Demand and Future Outlook - There is immense pressure from OEMs and cloud builders to bring Tomahawk 6 to market quickly, with expectations for product readiness by early 2026 [12][15] - The architecture of Tomahawk 6 enables efficient scaling of AI clusters, which is essential for modern data center requirements [14]

Core Viewpoint - Micron Technology presented its latest 3D NAND flash technology, the ninth generation (G9), at the 2025 IEEE International Memory Workshop, highlighting significant advancements in storage density and data transfer speeds while maintaining the same storage capacity per chip as the previous generation [1]. Summary by Sections G9 3D NAND Flash Technology - The G9 3D NAND flash has a storage capacity of 1 Tbit per chip, the same as the G8, but with a 40% increase in storage density of the memory cell array and a 30% increase in chip storage density [1]. - The maximum data transfer speed of G9 has improved by 1.5 times compared to G8 [1]. - The number of word line layers in G9 is 276, only a 19% increase from the 232 layers in G8, indicating that innovations beyond just increasing layer count contributed to the density improvements [1]. Storage Density Improvements - The storage density of Micron's memory cell array increased from 17 Gbit/mm² in G7 to 25 Gbit/mm² in G8, and further to 35 Gbit/mm² in G9 [3]. - Innovations include the removal of virtual pillars, which reduced block height by approximately 14%, and a decrease in the number of page buffers from 16 in G8 to 6 in G9, halving the page buffer's chip area [3]. Future Technology Challenges - The future of 3D NAND flash technology, including G10 and beyond, will face increasing technical challenges, akin to climbing an infinitely long spiral staircase [5]. - The introduction of "Confined SN" technology aims to reduce interference between adjacent cells, resulting in a 10% reduction in programming time and a 50% decrease in coupling capacitance between adjacent cells [9]. Innovations and Solutions - The G9 stack height exceeds 13 μm, with a layer height of 6.5 μm, and a high aspect ratio of over 43 due to the small diameter of storage holes [7]. - To mitigate electrical interference, Micron introduced air gaps in the insulation film and limited the nitrogen film to the gate side of the cell transistors [7][8]. - The transition from charge trapping to ferroelectric polarization is proposed as a solution to reduce the risk of dielectric breakdown, which is critical as the number of layers increases [16]. Cost and Performance Considerations - Micron is exploring wafer bonding technology to optimize the performance of peripheral circuits and memory cell arrays, despite the initial increase in costs associated with wafer bonding [12]. - The cost of wafer bonding is expected to decrease with each new technology generation, potentially becoming more cost-effective than single-chip manufacturing in the future [12][14].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 IEEE 。 纳文·维尔马在普林斯顿大学的实验室就像一座博物馆，展示了工程师们尝试利用模拟现象而非数 字计算来提高人工智能效率的各种方法。其中一个工作台上摆放着迄今为止最节能的基于磁存储器 的神经网络计算机。在另一个工作台上，你会发现一个基于电阻存储器的芯片，它可以计算迄今为 止任何模拟人工智能系统中最大的数字矩阵。 维尔马表示，这两种材料都没有商业前景。更糟糕的是，他的实验室这部分简直就是一片坟场。 多年来，模拟人工智能一直吸引着芯片架构师的想象力。它结合了两个关键概念，可以大幅降低机 器学习的能耗。首先，它限制了存储芯片和处理器之间昂贵的比特移动。其次，它利用电流流动的 物理原理，而不是逻辑上的1和0，来高效地进行机器学习的关键计算。 在机器学习中，"很偶然地，我们的主要运算是矩阵乘法，"Verma 说。这基本上就是取一个数字 数组，将其与另一个数组相乘，然后将所有这些乘法的结果相加。很早以前，工程师们就注意到了 一个巧合：电气工程的两个基本定律可以精确地完成这样的运算。欧姆定律说，电压乘以电导就能 得到电流。基尔霍夫电流定律说，如果一束电流从 ...

Core Viewpoint - UWB technology, which gained popularity after Apple's iPhone 11 release, has not met expectations in terms of widespread adoption and application despite its advantages in precision and security [1][5][6]. Group 1: UWB Technology Overview - UWB technology, based on IEEE 802.15.4a and 802.15.4z standards, allows for centimeter-level precision in distance and location measurement, making it suitable for applications in smartphones and asset tracking [3][4]. - UWB's advantages include strong anti-interference capabilities and high positioning accuracy, making it a preferred choice for automotive passive entry systems over BLE and NFC [4][6]. Group 2: Challenges in UWB Adoption - The slow development of UWB in recent years is attributed to the complexity of early UWB solutions, which required additional configuration and programming, posing challenges for many automotive manufacturers and smaller companies [4][5]. - Compatibility issues with third-party MCUs and the high costs associated with complex hardware integration have hindered UWB's market penetration [4][6]. Group 3: Recent Developments and Innovations - Chip manufacturers like Qorvo, NXP, and Samsung have introduced UWB SoC solutions to simplify design and accelerate product launch, such as Qorvo's QM35825 and QPF5100Q [6][8]. - The QM35825 features an "All-in-One" design that integrates multiple components, reducing design barriers and enhancing application in both industrial and consumer markets [7][8]. Group 4: Future Applications and Market Potential - UWB technology is being explored for various applications, including access control, asset tracking, and automotive safety systems, particularly in detecting child presence in vehicles [15][16]. - The technology's ability to measure direction and distance positions it favorably against other wireless technologies, with potential growth in smart locks and automotive markets [14][15].

Core Viewpoint - Co-packaged optics (CPO) technology is emerging as a promising solution to enhance bandwidth and energy efficiency in data centers, particularly for applications involving generative AI and large language models. However, manufacturing challenges remain, particularly in fiber-to-photonics integrated circuit (PIC) alignment, thermal management, and optical testing strategies [1][20]. Group 1: CPO Technology and Benefits - CPO enables network switches to route signals at speeds of terabits per second while significantly improving bandwidth and reducing power consumption required for AI model training [1][20]. - The technology achieves a bandwidth density of 1 Tbps/mm, optimizing rack space in increasingly crowded data centers [1][6]. - CPO can reduce power consumption associated with high-speed data transmission from approximately 15 pJ/bit to around 5 pJ/bit, with expectations to drop below 1 pJ/bit [6][7]. Group 2: Manufacturing Challenges - Key challenges in CPO manufacturing include achieving precise alignment between fiber and PIC, which is critical for effective optical signal coupling [8]. - The most common passive alignment method is the V-groove technique, which connects the fiber directly to the PIC to minimize loss [8][9]. - Efficient coupling between standard single-mode fibers and silicon waveguides is complicated due to significant differences in size and refractive index, leading to potential light loss [8][9]. Group 3: Thermal Management - CPO systems are sensitive to temperature fluctuations caused by high-power devices like GPUs and ASICs, which can affect the performance of photonic devices [11][12]. - A temperature change of just 1°C can lead to approximately 0.1nm wavelength shift in most photonic systems, necessitating careful thermal management strategies [11][12]. - Advanced thermal interface materials and monitoring circuits are deployed to maintain PIC temperature within predefined ranges [11][13]. Group 4: Reliability Design - Ensuring reliability in CPO systems is crucial, especially with multi-chip integration, requiring known good die (KGD) testing and optical testing solutions [14][16]. - High reliability designs incorporate redundancy, such as backup lasers, to maintain operation in case of component failure [15][16]. - Integrated monitoring and self-correcting features are being developed to detect performance degradation and facilitate quick recovery [15][16]. Group 5: Integration Techniques - Both 2.5D and 3D packaging methods are utilized in CPO, with 2.5D placing electronic ICs and PICs side by side on a silicon interposer [17][18]. - 3D integration allows for optimal manufacturing processes for each chip type, enhancing performance while increasing complexity and cost [18][19]. - The integration of optical features with traditional CMOS processes is becoming more compatible, facilitating advancements in CPO technology [17][18].

Core Viewpoint - The rise of smart vehicles has significantly increased the attention on the SerDes chip market, which is expected to reach several billion dollars by 2023 and grow towards a hundred billion dollar scale in the next decade, with China potentially accounting for 40% of this market [1][2]. Group 1: Market Overview - The SerDes chip market is currently dominated by two major suppliers, ADI and TI, who have established a stronghold through proprietary protocols GMSL and FPD-Link [1][3]. - The GMSL technology, introduced by Maxim (acquired by ADI) in 2008, allows for high-speed data transmission over a single coaxial or shielded twisted pair cable, supporting various data types including video and audio [5][12]. - The FPD-Link standard, created by National Semiconductor (now part of TI), has been widely adopted for automotive applications, particularly in navigation and entertainment systems [3][8]. Group 2: Technological Developments - GMSL has evolved through multiple generations, with GMSL2 supporting data rates up to 6 Gbit/s and GMSL3 reaching 12 Gbit/s, enabling the transmission of multiple 4K video streams [9][11]. - The introduction of new standardized protocols such as MIPI A-PHY, ASA, and HSMT presents significant competition to the existing proprietary protocols [14][20]. Group 3: OpenGMSL Initiative - ADI announced the formation of the OpenGMSL association, transitioning GMSL from a proprietary protocol to a globally accessible standard, aimed at fostering innovation in automotive applications [24][28]. - The OpenGMSL standard will focus on edge connectivity, addressing the needs of modern software-defined vehicles (SDVs) by providing low-power, low-latency solutions [29][30]. - The association aims to ensure interoperability among different manufacturers' components, enhancing collaboration across the automotive ecosystem [30][32].

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容 编译自 9to5mac 。 苹果计划为2026款iPhone彻底革新其芯片设计，此举可能标志着该公司首次在移动设备中使用先 进的多芯片封装技术。这听起来很复杂，但这意味着什么呢？ 据分析师 Jeff Pu 在为广发证券撰写的新报告中称，iPhone 18 Pro、18 Pro Max 以及传闻已久的 iPhone 18 Fold预计将首次搭载苹果的 A20 芯片，该芯片基于台积电第二代 2nm 工艺（N2）打 造。 但这只是故事的一部分。更有趣的是这些芯片将如何组装。 苹 果 将 首 次 在 其 iPhone 处 理 器 中 采 用 晶 圆 级 多 芯 片 模 块 (WMCM ： Wafer-Level Multi-Chip Module) 封装。WMCM 允许将 SoC 和 DRAM 等不同组件直接集成在晶圆级，然后再切割成单 个芯片。 它采用一种无需中介层或基板即可连接芯片的技术，从而可以带来热完整性和信号完整性方面的好 处。 众所周知，在芯片行业，有一种根据硅晶圆的制造差异将芯片分级的技术，具体而言，将其划分为 不同性能等级的一种工艺。这些差异可能由 ...

Core Viewpoint - Cornelis Networks has launched the CN5000 series, a 400Gbps Omni-Path technology aimed at enhancing AI and HPC performance, with plans for future UltraEthernet integration [1][19]. Group 1: Product Overview - The CN5000 series is designed for AI and HPC applications, supporting deployments of up to 500,000 endpoints and providing advanced lossless data transmission and congestion avoidance features [19][20]. - The CN5000 utilizes Omni-Path architecture, which includes credit-based flow control and dynamic fine-grained adaptive routing to ensure high performance and reliability [20][22]. - The series includes both air-cooled and liquid-cooled switch options, addressing the cooling needs of large AI companies [5][22]. Group 2: Performance Metrics - The CN5000 demonstrates superior performance in HPC workloads, achieving up to 30% faster execution in computational fluid dynamics and climate modeling compared to InfiniBand NDR [22]. - For AI applications, the CN5000's collective communication speed is six times faster than RoCE, enhancing the efficiency of large language model training [19][22]. Group 3: Future Developments - The upcoming CN6000 series, set for release in 2026, will integrate Omni-Path with Ethernet support, doubling bandwidth capabilities [16][21]. - The CN7000 series, expected in 2027, will combine UltraEthernet standards with Omni-Path architecture, targeting the most demanding AI and HPC environments [17][21]. Group 4: Market Positioning - Cornelis Networks aims to provide a cost-effective alternative to NVIDIA's InfiniBand, capitalizing on the growing demand for high-performance networking solutions in AI and HPC sectors [18][19].

先进封装成为下１个技术帝国的边疆要塞，不是偶然，而是3股力道推动出来的必然结果。 第1股力道是算力井喷，但制程进展放缓，芯片必须被切割、堆叠、重组。陆行之表示，你能做到 5奈米，不代表你能塞进20倍算力，光罩极限挡住了芯片的面积，只有Chiplet 能绕过这道墙， Ncidia Blackwell 就是这样诞生的。 第2股力道则是应用百变，芯片不再单一适配，系统设计走向模组化。陆行之说，1种芯片搞定所 有应用的时代已经结束，AI训练、自驾决策、边缘运算、AR装置……每1个应用都需要不同组合 的矽，先进封装加Chiplet，就是设计弹性与效率的平衡解答。 如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内容来自 自由时报 。 半导体的改变正在加速，先进封装，不再是边角料。知名分析师陆行之表示，棋盘中央如果说先进 制程是矽时代的权力中枢，那么先进封装，正在成为下１个技术帝国的边疆要塞。 陆行之在脸书上贴文指出，10年前，这条路线曾被误解，甚至被忽视，但10年后的今天，它已悄 悄从「非主流的Plan B」变成「主流赛道的Plan A」。 第3股力道则是资料搬运成本飙升，能耗变成第１瓶颈。在AI 芯片里，搬资料的耗能 ...

如果您希望可以时常见面，欢迎标星收藏哦~ 来源：内 容 综合自 theinformation 。 虽然麻烦一直增加，但英伟达还是尝试向中国销售其人工智能芯片，人们可能会想知道为什么该公 司还要继续坚持。 答案是：它实在承受不起不这么做的后果。 英伟达上周发布的第一财季财报，向特朗普政府发出了一个相当严厉的信号，即将美国芯片公司排 除在中国人工智能市场之外的危险。英伟达首席执行官黄仁勋在公司电话会议上表示："无论有没 有美国芯片，中国的人工智能都会继续发展。" 黄仁勋指出，全球一半的人工智能开发者都在中 国，阻止美国公司在中国竞争最终可能会让美国失去在全球人工智能领域的领先地位。 "最终，赢得人工智能开发者的平台才能赢得人工智能，"黄仁勋说道。"出口管制应该加强美国平 台，而不是将全球一半的人工智能人才赶往竞争对手。" 英伟达也有充分的财务理由来支持这一论点。美国政府今年4月决定禁止该公司向中国市场销售其 H20芯片，导致该公司在截至4月底的季度损失了约25亿美元的销售额，并将在截至7月底的当前季 度再损失80亿美元。这是因为H20芯片是专门为中国市场设计的，以符合当时的出口限制，因此在 其他任何地方都无法销售 ...